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A novel bumping process using solder bump maker is developed for the maskless low-volume solder on pad (SoP) technology of fine-pitch flip chip bonding. The process includes two main steps: one is the aggregation of powdered solder on the metal pads on a substrate via an increase in temperature, and the other is the reflow of the deposited powder to form a low-volume SoP. Since the surface tension that exists when the solder is below its melting point is the major driving force of the solder deposit, only a small quantity of powdered solder adjacent to the pads can join the aggregation process to obtain a uniform, low-volume SoP array on the substrate, regardless of the pad configurations. Through this process, an SoP array on an organic substrate with a pitch of 130 μm is successfully formed.

Through silicon via (TSV)-based 3-D integrated circuit has introduced the solution to limitlessly growing demand on high system bandwidth, low power consumption, and small form factor of electronic devices. As the system design aims for higher performance, the physical dimensions of the channels are continuously decreasing. With TSV diameter of less than 10 $\mu \text{m}$ and pitch of several tens of micrometers, the I/O count has increased up to the order of tens of thousands for wide bandwidth data transmission. However, without highly precise fabrication process, such small structures are susceptible to a variety of defects. For the first time, in this paper, we propose a noninvasive defect analysis method for high-speed TSV channel. With designed and fabricated test vehicles, the proposed method is demonstrated with ${S}$ -parameter and time-domain reflectometry measurement results. In addition, we present equivalent circuit models of TSV daisy-chain structures, including the circuit components for open defect and short defect. With characterized dominant factors in each frequency range, $S_{11}$ is analyzed to distinguish and locate the defects by the amount of capacitance, resistance, and inductance that the signal experiences. ${S}$ -parameter measurement sufficiently allows high-frequency defect analysis of TSV channel without destroying the test sample. We experimentally verified the accuracy of the suggested model by comparing the ${S}$ -parameter results from circuit simulations and measurements. Finally, the model is modified to discuss the effects of open defect and short defect on the electrical characteristics of TSV channel.

A novel bumping process using solder bump maker (SBM) is developed for fine-pitch flip chip bonding. It features maskless screen printing process with the result that a fine-pitch, low-cost, and lead-free solder-on-pad (SoP) technology can be easily implemented. The process includes two main steps: one is the thermally activated aggregation of solder powder on the metal pads on a substrate and the other is the reflow of the deposited powder on the pads. Only a small quantity of solder powder adjacent to the pads can join the first step, so a quite uniform SoP array on the substrate can be easily obtained regardless of the pad configurations. Through this process, an SoP array on an organic substrate with a pitch of 130 μm is, successfully, formed.

Through silicon via (TSV) based 3DIC has allowed vertical integration of multiple dies for wide I/O configuration. With thousands of TSVs, data transfer rate can be reduced, while maintaining the highest bandwidth compared to the systems in conventional integrated chips and packages. The challenges lie on high yield fabrication process. The trend in dimension of TSV is continuously decreasing, which also causes bumps and redistribution layer (RDL) to be reduced for routing high number of I/Os. In this paper, we present the equivalent circuit models and analyze the TSV channels for investigation of the effect of possible defects. The verified models are used for characterizing the defects in TSV channel, and we validate the failure analysis method with electrical characteristic analysis in frequency-domain with S-parameter plots as well as time-domain waveforms with TDR.

Thermal and electrical designs were performed to implement a 3D T/R (Transmit/Receive)-module based on the Si interposers. Two types of 3D module structures were compared with respect to the thermal performance and manufacturability. The FEM simulations were conducted to check the feasibility of the Si interposers as the heat spreader in the 3D module. Two kinds of sintered silver pastes having the advantage of low temperature process were considered as a TIM (Thermal Interface Material) for the 3D module. Test vehicles with the adhesives were prepared, and their thermal performances were measured under the condition of the DC power consumption of 28W. The vertical transitions with redundant TSVs and solder bumps were designed to increase the yield of the 3D module. The effects of the open failure of the redundant TSVs on the electrical performance of the vertical transitions were simulated.

In previous work, novel maskless bumping and no-flow underfill technologies for three-dimensional (3D) integrated circuit (IC) integration were developed. The bumping material, solder bump maker (SBM) composed of resin and solder powder, is designed to form low-volume solder bumps on a through silicon via (TSV) chip for the 3D IC integration through the conventional reflow process. To obtain the optimized volume of solder bumps using the SBM, the effect of the volumetric mixing ratio of resin and solder powder is studied in this paper. A no-flow underfill material named "fluxing underfill" is proposed for a simplified stacking process for the 3D IC integration. It can remove the oxide layer on solder bumps like flux and play a role of an underfill after the stacking process. The bumping process and the stacking process using the SBM and the fluxing underfill, respectively, for the TSV chips are carefully designed so that two-tier stacked TSV chips are sucessfully stacked.

Using high-speed through-silicon via (TSV) channels is a potential means of utilizing 3-D interconnections to realize considerable high-bandwidth throughput in vertically stacked and laterally distributed integrated circuits. However, although the TSV and a silicon interposer in a high-speed TSV channel lead to a significant decrease of the interconnect length, the received digital signal after transmission through a TSV channel is still degraded at a high data-rate due to the nonidealities of the channel. Therefore, an analysis of the signal integrity in a high-speed TSV channel is necessary. In this paper, a single-ended high-speed TSV channel is measured and analyzed in the frequency-domain and the time-domain. To measure the high-speed TSV channel, two types of test vehicles are fabricated, consisting of TSVs and interposers. With these test vehicles, the channel losses are measured in the frequency-domain up to 20 GHz, and eye-diagrams are measured in the time-domain at 1 Gb/s and 10 Gb/s. Based on these measurements, the channel loss, characteristic impedance, and reflection of the high-speed TSV channel are analyzed and compared to those of the channel in multichip module (MCM) package. Because of the losses from the silicon-substrate and the thin oxide-layer used in the TSVs, the overall loss of the high-speed TSV channel is higher than that of the MCM channel. In addition, the characteristic impedance of the high-speed TSV channel is frequency-dependent, whereas that of the MCM channel is frequency-independent. Moreover, in contrast to the MCM channel, the reflection is negligible in the high-speed TSV channel because the channel is too short and the losses are too high to be affected by the reflection. Finally, the design guidance of a high-speed TSV channel for wide bandwidth is determined based on the analysis of the measurements.

In this paper, measurements of high-speed TSV channel were performed in frequency- and time-domains for the signal quality test. The channel loss was measured up to 20 GHz in frequency-domain and the eye-diagram was measured up to 10 Gbps in time-domain. To analyze the measurement results, the equivalent-circuit model of high-speed TSV channel and the worst eye-diagram estimation algorithm were introduced. By using them, the impacts of silicon-conductance and oxide-capacitance on channel loss were analyzed. Moreover, the negligible impact of reflection on the signal quality of the high-speed TSV channel was also analyzed. These measurement-based signal quality analyses can provide the useful insight and design guidance for high-speed TSV channel.

As an isotropic conductive adhesive, that is, a hybrid Cu paste composed of Cu powder, solder powder, and a fluxing resin system, has been quantitatively characterized. The mechanism of an electrical connection based on a novel concept of electrical conduction is experimentally characterized using an analysis of a differential scanning calorimeter and scanning electron microscope energydispersive X-ray spectroscopy. The oxide on the metal surface is sufficiently removed with an increase in temperature, and intermetallic compounds between the Cu and melted solder are simultaneously generated, leading to an electrical connection. The reliability of the hybrid Cu paste is experimentally identified and compared with existing Ag paste. As an example of a practical application, the hybrid Cu paste is used for LED packaging, and its electrical and thermal performances are compared with the commercialized Ag paste. In the present research, it is proved that, except the optical function, the electrical and thermal performances are similar to pre-existing Ag paste. The hybrid Cu paste could be used as an isotropic conductive adhesive due to its low production cost.

A novel bumping material, which is composed of a resin and Sn3Ag0.5Cu (SAC305) solder power, has been developed for the maskless solder-on-pad technology of the fine-pitch flip- chip bonding. The functions of the resin are carrying solder powder and deoxidizing the oxide layer on the solder power for the bumping on the pad on the substrate. At the same time, it was designed to have minimal chemical reactions within the resin so that the cleaning process after the bumping on the pad can be achieved. With this material, the solder bump array was successfully formed with pitch of 150 µm in one direction. 150 µm. The proposed technologies were solder jetting, controlled collapse chip connection new process (C4NP), electro-plating, micro-ball placement, super solder, and so on. Each technology has its own disadvantages, such as expensive equipment, low throughput, and environmental problems. In this letter, we propose a novel bumping material for SoP technology. The basic idea is similar to the solder bump maker (SBM), which is based on the rheological behavior of the solder in resin (3)-(5). However, the major component of the resin in the SBM was epoxy, the solder of which has a low- melting-point, making the SBM inapplicable to the SoP technology. To resolve those problems, we adopted the Sn3Ag0.5Cu (SAC305) solder and developed a new resin which can endure high temperature process so that a cleaning process can be performed after the bumping process. This SBM with SAC solder has the same features as the SBM with low-melting-point solder (3). The characteristics of the resin with and without solder were analyzed using differential scanning calorimetry (DSC) and a dynamic mechanical analyzer (DMA). The wetting behavior of SAC305 solder in the resin on Au finish and Cu finish electrodes was observed. Finally, an SAC solder bump array with pitch of 150 µm in one direction was formed using the SBM with SAC, and its morphologies were characterized.

In this paper, we present the fabrication of 40 Gb/s traveling-wave electroabsorption modulator-integrated laser (TW-EML) modules. A selective area growth method is first employed in 40 Gb/s EML fabrication to simultaneously provide active layers for lasers and modulators. The 3 dB bandwidth of a TW-EML module is measured to be 34 GHz, which is wider than that of a lumped EML module. The 40 Gb/s non-return-to-zero eye diagram shows clear openings with an average output power of +0.5 dBm.

Integration of a 40-Gb/s electroabsorption modulator integrated distributed feedback (DFB) laser (EML) module with a driver amplifier and bias tee was investigated. For the EML fabrication the selective area growth (SAG) technique was adopted for the first time. It is shown that, with the SAG technique, the 3-dB bandwidth of about 45 GHz was measured in the electrical to optical response, and the return loss (S11) of below -10 dB was achieved for up to 50 GHz . To integrate a bias tee within the module, a right-angle bent coplanar waveguide (CPW) was developed. The right-angle bent CPW was characterized with S11 of below - 10 dB for up to 35 GHz and insertion loss (S21) of about -1.4 dB for up to 40 GHz . The whole integrated module including the EML, a driver amplifier, and bias tee was characterized under the conditions of an operating temperature of 25degC, the modulator bias of 1.4 V, and the DFB laser current of 40 mA. S11 of below -10 dB was obtained for up to 14 GHz and the measured electrical-to-optical response has 3-dB bandwidth of about 20 GHz.

We have developed 40-Gb/s traveling-wave electroabsorption-modulator-integrated distributed feedback laser (TW-EML) modules using several advanced technologies. First, we have adopted a selective area growth (SAG) method in the fabrication of the 40-Gb/s EML device to provide active layers for the laser and the electroabsorption modulators (EAMs) simultaneously. The fabricated device shows that the measured 3-dB bandwidth of electrical-to-optical (E/O) response reaches about 45 GHz and the return loss (S11) is kept below -10 dB up to 50 GHz. For the module design of the device, we mainly considered electrical and optical factors. The measured S11 of the fabricated 40 Gb/s TW-EML module is below -10 dB up to about 30 GHz and the 3-dB bandwidth of the E/O response reaches over 35 GHz. We also have developed two types of coplanar waveguide (CPW) for the application of the driver amplifier integrated 40 Gb/s TW-EML module, which is a system-on-package (SoP) composed of an EML device and a driver amplifier device in a module. The measured S11 of the two-step-bent CPW is below -10 dB up to 35 GHz and the measured S11 of the parallel type CPW is below -10 dB up to 39 GHz.

A system-on-packaging (SoP) with an electroabsorption modulator (EAM) for a 60 GHz band radio-over-fiber (RoF) link is described. The system consists of an EAM device, a microstrip filter, and a low noise amplifier (LNA). The microstrip filter was used to achieve impedance matching between the EAM device and the LNA and to reject the local oscillator (LO) frequency of the heterodyne system. The frequency response and the effect of the EAM bias voltage were measured for a simple RF/optical link. A 60 GHz band RoF link with 2.5 GHz intermediate frequency (IF) was prepared to measure the transmission characteristics of the 16 QAM data.

We developed an analog optical system-on-package (SoP) transmitter for a 60-GHz-band radio-over-fiber (RoF) link. The SoP transmitter consisted of an electroabsorption modulator, radio frequency amplifiers, and a bandpass filter. The 60-GHz RoF wireless link was prepared to measure the performance of the SoP transmitter. The transmission characteristics of 64-quadrature amplitude modulation (64-QAM) data of the 60-GHz RoF wireless link, including the SoP transmitter, were investigated by measuring the error vector magnitude (EVM) and signal-to-noise ratio (SNR) with a baseband frequency. The EVM of the 60-GHz RoF wireless link was between 2.25% and 2.80%, and the SNR was between 27.36 and 29.31 dB from 140 and 770 MHz, at input baseband power of -9 dBm. The noise figure had the minimum of 8.44 dB at 500 MHz. We successfully transmitted digital community antenna television (CATV) system signals through the 60-GHz RoF wireless link, including the SoP transmitter. Digital CATV signals of 86 channels could be transmitted through the 60-GHz RoF wireless link, and the total throughput was found to be 2.61 Gb/s.

As the interests in wearable devices are become growing, flexible substrates is being extensively investigated. In this study, new hybrid underfill for a low temperature process to create an electrical interconnection system on flexible substrate was studied. Hybrid underfill material is composed with underfill materials and 54Bi27In19Sn solder powder which has melting temperature at 83°C. For the stable chemical reaction, process temperature was set to 130°C. Hybrid underfill material has advantage of reducing processing step because the processing step such as solder joint formation, fluxing, cleaning, underfill step can proceed at a time. To optimize the wettability of solder powder, compositions and the ratio or the materials and processing conditions are controlled. By controlling the various conditions such as reductant and catalyst of hybrid underfill material, we optimize the low temperature process. As a result, solder joint is formed stably at a low temperature.

The material designs of the Si interposers are optimized for a 3D RF module. The high resistivity Si wafers are used for the Si interposer fabrication: 1,000 Ω·cm ∼ 10,000 Ω·cm. To reduce the capacitance and mechanical stress between Cufilled TSV and Si substrate, a polyimide insulation layer is applied as a TSV liner. We designs several types of the transmission line structures and measures their electrical properties. For the 3D interconnection between the Si interposers, fluxing underfill material is developed and used as a pre-applied underfill for the thermocompression bonding process. With these optimizations of materials design of the Si interposers, the microstrip line shows the electrical loss of 0.065 dB/mm at 10 GHz, and the insertion loss of the vertical transition is 0.4 dB at 10 GHz.

In this letter we present a right-angle-bent coplanar waveguide (CPW) which we developed for the application of the driver amplifier-integrated (DAI) 40 Gbps traveling wave electroabsorption modulated laser module. The developed CPW realized parallel progression of the radio frequency (RF) and light using a dielectric overlay structure and wedge bonding on the bending section. The measured S11 and S21 of the developed CPW were kept below -10 dB up to 35 GHz and -3 dB up to 43 GHz, respectively. These measured results of the CPW were in good agreement with the simulation results and demonstrated the applicability of the CPW to the 40 Gbps communication module.

We developed high-speed optoelectronics packaging technologies for a waveguide photodiode and a traveling wave electro-absorption modulator device for 40-Gb/s digital communication systems. The effects of the device and the packaging designs on the broadband performance were investigated to optimize broadband characteristics. For the receiver, inductive peaking was used for bandwidth control and an internal bias tee was implemented; in addition, two types of preamplifier devices were used to develop high-gain receiver and wide-bandwidth receiver. In the optical-to-electrical response, a 3-dB bandwidth of the high-gain module was about 32 GHz as compared to 42 GHz for the wide-bandwidth module. The clear 40-Gb/s nonreturn-to-zero (NRZ) eye diagrams showed a good system applicability of these modules. In addition, an optimized modulator module showed a 3-dB bandwidth of 38 GHz in the electrical-to-optical response, an electrical return loss of less than 10 dB at up to 26 GHz, an rms jitter of 1.832 ps, and an extinction ratio of 5.38 dB in a 40-Gb/s NRZ eye diagram

This letter proposes a new impedance matching scheme of a traveling wave electro-absorption modulator (TWEAM) module for a 60 GHz band radio-over- fiber (ROF) link. A microstrip band pass filter (BPF) was used to achieve impedance matching at the 60 GHz band, and termination resistance was carefully designed to obtain an input impedance close to 50 Ω.. Also, a bias circuit for the device was designed in the module. The measured return loss and frequency response show that the modulator module observes the characteristics of a filter without the need of a further tuning process.

We developed an analog 60-GHz module for RF/optic conversion by using an electroabsorption modulator (EAM) device associated with a traveling-wave electrode. The impedance matching of the module was accomplished with the 30-/spl Omega/ termination such that the resonance was precisely located at 60 GHz and the fractional bandwidth at S/sub 11/=-15 dB was as large as 1.0 GHz. The RF/optic conversion gain of the EAM device revealed a strong dependence on the input optical power and was closely related with the slope change in the optical transmission characteristic with reverse bias. From the EAM module with the composite-type multiple-quantum-well electroabsorption core consisting of both 8- and 12-nm quantum wells, we obtained the optimal RF/optic conversion gain at the reverse bias between 1.5-2 V in a wide range of input optical power from -6 to +9 dBm. In the same bias range, the third-order intermodulation distortion was

In this study, scattering from a general high-order inhomogeneousimpedance cylinder is investigated by series expansion of the surface impedance for an incident TM wave. A similar procedure can also be applied for the TE incidence case. It is observed that when N increases, the results converge more rapidly. The proposed method and the MoM technique are also applied for a 1 st -order inhomogeneous impedance cylinder. The obtained results are compared by those obtained using the numeric MoM technique and good agreement is observed. The proposed method also significantly reduces the computer calculation time according the MoM. For instance, using the same computer, the calculation times of Figure 2 by proposed method with N 30 coefficients and discretization number N 400 points (MoM) are 3.859 and 38.65 s, respectively. REFERENCES

We fabricated 40 Gb/s front-end optical receivers using spot-size converter integrated waveguide photodiodes (SSC-WGPDs). The fabricated SSC-WGPD chips showed a high responsivity of approximately 0.8 A/W and a 3 dB bandwidth of approximately 40 GHz. A selective wetetching method was first adopted to realize the required width and depth of a tapered waveguide. Two types of electrical pre-amplifier chips were used in our study. One has higher gain and the other has a broader bandwidth. The 3 dB bandwidths of the higher gain and broader bandwidth modules were about 32 and 42 GHz, respectively. Clear 40 Gb/s non-return-to-zero (NRZ) eye diagrams showed good system applicability of these modules.

Packaging technologies for a broadband and narrowband modulator with a traveling wave electro-absorption modulator (TWEAM) device were developed. In developing a broadband modulator, the effects of the device and packaging designs on the broadband performance were investigated. The optimized designs were obtained through a simulation with the result that we developed a broadband modulator with a 3 dB bandwidth of 38 GHz in the electrical-to-optical (E/O) response, an electrical return loss of less than -10 dB at up to 26 GHz, an rms jitter of 1.832 ps, and an extinction ratio of 5.38 dB in a 40 Gbps non-return to zero (NRZ) eye diagram. For analog application, the effect of the RF termination scheme on the fractional bandwidth was studied. The microstrip line with a double stub as a matching circuit and a laser trimming process were used to obtain an S 1 1 of -34.58 dB at 40 GHz and 2.9 GHz bandwidth of less than -15 dB.

Reaction characteristics of the In-15Pb-5Ag (wt.%) solder with a Au/Ni/Cu pad during reflow soldering and aging treatment were examined. Interfacial reaction during reflow resulted in either an AuIn2 or Ni28In72 layer, depending on reflow time. The AuIn2 layer became thinner and disappeared from the interface, and only the Ni28In72 layer grew with the progress of aging treatment at 130°C. Based on those observations, the dissolution rate of the Au top layer was estimated, and the behavior of the AuIn2 layer during reflow and aging treatment was discussed. In addition, peak shear load and fracture energy of the solder bump were measured as a function of reflow time and aging treatment. The results were compared with those measured with the Sn-37Pb solder bump.

Comparing with a lumped electroabsorption modulator (EAM), we show the merits of a long EAM with traveling-wave electrode with high radio-frequency (RF) gain that could be used in high-frequency analog application. By terminating the RF output port with the characteristic impedance of 30 /spl Omega/, the device exhibited a large enhancement of 6 dB above 10 GHz in the electrical-to-optical response and a wide fractional bandwidth as estimated from simulation. In addition, an input impedance matching circuit of stub embedded on the device chip was found to be very effective for improving RF characteristics in the narrow band of frequency.

Traditionally, ACF (Anisotropic Conductive Adhesive) technology has been used for CoG (Chip-on-Glass) and FoG (Flex-on-Glass) interconnections in display packaging area. The electrical contacts of ACF technology are based on the mechanical contacts between the electrodes on substrates and conductive particles in ACF. As pitches of these interconnections tend to get finer than 30 μm and bonding temperature needs to be decreased because of warpage concerns during the bonding process, a novel interconnection technology for the advanced display systems is necessary. In this paper, a maskless screen printing technology is proposed to form and bond 20 μm-pitch, 52InSn solder interconnections for advanced display systems. InSn solder is selected to decrease the bonding temperature because its melting point is 118°C. A novel material, called as solder bump maker (SBM) is developed to have InSn solder powder in SBM used for InSn bumping process. The polymer matrix and deoxidizing agent in SBM are carefully designed to make InSn solder powder in SBM wet on Cu or Au electrodes on a substrate during the bumping process. Since InSn solder powder resides only on electrodes on a substrate with temperature variations because of the surface tensions between the solder powder and metal electrodes, a maskless screen printing process can be adopted for the InSn, fine-pitch bumping process. Using a maskless screen printing process with SBM, 20 μm-pitch, InSn solder interconnections on a glass substrate are successfully formed. We, also, developed a no-flow underfill material, name as fluxing underfill, for a bonding material of InSn interconnections. It plays roles of flux and underfill at the same time during the bonding process. The bonding process for 20 μm-pitch, InSn solder interconnections is successfully achieved using fluxing underfill. Its peak temperature of the bonding process is 130°C.

A novel, maskless, low-volume bumping material, called solder bump maker, which is composed of a resin and lowmelting-point solder powder, has been developed. The resin features no distinct chemical reactions preventing the rheological coalescence of the solder, a deoxidation of the oxide layer on the solder powder for wetting on the pad at the solder melting point, and no major weight loss caused by outgassing. With these characteristics, the solder was successfully wetted onto a metal pad and formed a uniform solder bump array with pitches of 120 μm and 150 µm.

Copper lead frame was chosen as an on-board reliability enhancement for the BLP (bottom leaded plastic) package. Adopting the copper lead frame needed a verification process for the package reliability because of its high affinity with oxygen that degrades package reliability. A series of tests were performed to select the best copper material and to determine the adhesion index parameter. The experimental results showed that the adhesion strength between the copper lead frame and EMC (epoxy molding compound) was affected by alloy composition, oxide layer thickness, and cupric/cuprous oxide ratio, Among them, the adhesion index parameter proved to be the cupric/cuprous oxide ratio. When it falls between 0.2-0.3, the highest adhesion strength was obtained regardless of alloy composition and oxide thickness. From the adhesion test results, the Cr-Zr-Cu copper alloy was employed as the lead frame for the 54-pin BLP package. The package reliability and on-board reliability tests including surface mountability, mechanical robustness, and solder joint reliability were carried out to compare the 54-pin BLP package, with Cr-Zr copper alloy and alloy 42 lead frame.

Harmonic signal generation and frequency up-conversion are demonstrated using a hybrid mode-locked multisection distributed-feedback (MS-DFB) laser. Hybrid mode-locking is realized by direct injection of electrical local oscillator (LO) signals into the laser gain control section. The harmonic signals are generated when multiple optical modes produced by the hybrid mode-locked MS-DFB laser are detected in a photodiode (PD). In addition, if data signals at fIF are applied to the device along with LO signals at fLO, optical sidebands separated from the optical modes by fIF are generated and harmonic up-converted signals are obtained by mode-beating in PD. Using this method, we demonstrate generation of the third-harmonic millimeter-waves at 30.79 GHz with fLO at 10.263 GHz, and up-conversion of 12.5-Mb/s 32 quadrature amplitude modulation data at 300-MHz fIF into 30-GHz band

We present high-sensitivity photoreceivers based on a vertical- illumination-type 100% Ge-on-Si p-i-n photodetectors (PDs), which operate up to 50 Gb/s with high responsivity. A butterfly-packaged photoreceiver using a Ge PD with 3-dB bandwidth (f(-3dB)) of 29 GHz demonstrates the sensitivities of -10.15 dBm for 40 Gb/s data rate and -9.47 dBm for 43 Gb/s data rate, at BER of 10(-12) and λ ~1550 nm. Also a photoreceiver based on a Ge PD with f(-3dB)~19 GHz shows -14.14 dBm sensitivity at 25 Gb/s operation. These results prove the high performance levels of vertical-illumination type Ge PDs ready for practical high-speed network applications.

A sampled-grating distributed Bragg reflector laser module having an integrated multiwavelength locker has been developed and evaluated. The uniquely designed wavelength locker made of thermally controlled etalon has provided uniform wavelength monitoring and very stable wavelength locking in the 188-ITU grid channels (37 nm) with 25-GHz spacing. Over the case temperature from -5/spl deg/C to 65/spl deg/C, the laser wavelength was locked within /spl plusmn/0.5 GHz, and the total power consumption of the module was less than 4 W.

Microstrip lines and coplanar waveguides (CPWs) for RF three-dimensional (3D) modules were characterized on high-resistivity Si interposers: 2,000 Ω·cm. The diameter and thickness of through-silicon-vias (TSVs) in Si interposers were 50 and 250 µm, respectively. A signal TSV around five ground TSVs, and a signal solder bump around five ground solder bumps were designed to obtain the vertical transitions with low electrical loss between the transmission lines. For the 3D interconnections between Si interposers, a fluxing underfill material was developed and used as a preapplied underfill during the thermocompression bonding. The S-parameters of transmission lines and stacked transmission lines were measured from 0.5 to 10 GHz using a vector network analyzer (VNA) and de-embedded so that their electrical losses were obtained and compared. By comparing with the electrical loss of the transmission line on low-temperature cofired ceramics (LTCC), we found that both transmission lines were sufficiently good for applications in RF 3D modules.

Low-volume, low-cost and lead-free Solder-on-Pad (SoP) process using solder bump maker (SBM) is proposed for the fine-pitch flip-chip bonding process. The SBM is composed of a lead-free solder powder and a resin. The resin in the SBM consists of a polymer matrix, a deoxidizing agent and additives. The deoxidizing agent and additives remove the oxide layer on the surface of the solder powder. The bumping process features no-mask process so that a fine pitch bump array can be easily achievable. It mainly consists of two thermal steps; one is for the aggregation of the solder powder on the metal pads on a substrate and the other for the reflow process to make the round solder bump array. The thermo-rheological behavior of the SBM was characterized using a differential scanning calorimetry (DSC) and a dynamic mechanical analyzer (DMA). With this material and process, the solder bump array was successfully formed with pitch of 130μm.

In this paper, a three-dimensional system in packaging (3D SiP) module in which a bottom interposer and a top interposer are interconnected vertically with the low-volume solder-on-pad (SoP) and through-silicon vias (TSVs) has been presented. A novel solder bumping material has been developed for the low-volume SoP and the thickness of SoP was measured about 10 μm. The low-volume SoP was evaluated by the cross-sectional photographs and the measurement of dc resistance using daisy-chain patterns. 3D SiP module composed of a GPU and two SRAM on the interposers were fabricated with this bumping material, a fluxless underfill and the vertical interconnection processes.

Skew of balanced receiver was measured using O/E response measurement setup and optical splitter. Using the function of balanced receiver, its skew is obtained precisely from the oscillation period of O/E response.

We present a hybrid-integrated coherent receiver module using flip-chip technology for coupling a silica-based 90o-hybird planar lightwave circuit (PLC) chip to a spot-size converter integrated waveguide photodiode (SSC-WG-PD) array chip for a balanced photodiode (BPD) and interconnecting with a dual-channel transimpedance amplifier (TIA).

A novel solder bumping material and process for low-volume solder-on-pad (SoP) have been developed to be applied in the flip chip bonding using Au stud bumps. It features a maskless, low-cost, and lead-free material. The thicknesses of the solder bumps on pads on a substrate were measured about 10 μm. With this material and optimized process, as well as, fluxing underfill, a 3D IC module composed of a GPU, two SRAM, two Si interposer with TSVs, and passives were successfully developed.

We present a hybrid-integrated coherent receiver module using a chip-to-chip bonding technology to integrate a spot-size converter integrated photodiode array chip and an optical hybrid chip using a silica-based PLC technology.

We propose and demonstrate the use of subcarrier/polarization-interleaved training symbols for channel estimation and synchronization in polarization-division multiplexed (PDM) coherent optical orthogonal frequency-division multiplexed (CO-OFDM) transmission. The principle, the computational efficiency, and the frequency-offset tolerance of the proposed method are described. We show that the use of subcarrier/polarization interleaving doubles the tolerance to the frequency offset between the transmit laser and the receiver’s optical local oscillator as compared to conventional schemes. Using this method, we demonstrate 43-Gb/s PDM CO-OFDM transmission with 16-QAM subcarrier modulation over 5,200-km of ultra-large-area fiber.

A novel, maskless, low-volume bumping material, called solder bump maker, which is composed of a resin and low-melting-point solder powder, has been developed to make solder bumps on TSVs. With the coining process, the standard deviation of bump heights became 1μm. Fluxing underfill which features an extremely low-weight loss with temperature, has been, also, developed to simplify the chip-to-chip and chip-to-wafer bonding processes and implement the mass reflow process for them. Therefore, these processes can be reduced to only three steps: dispensing fluxing underfill, pick and place of TSV chips, and reflow. With the fluxing underfill, a 4 × 4 array of 4 tier-stacked TSV chips on a Si wafer was, successfully, developed.

A hybrid-integrated coherent receiver module has been achieved using flip-chip bonding technology, consisting of a silica-based 90°-hybrid planar lightwave circuit (PLC) platform, a spot-size converter integrated waveguide photodiode (SSC-WG-PD), and a dual-channel transimpedance amplifier (TIA). The receiver module shows error-free operation up to 40Gb/s and OSNR sensitivity of 11.5 dB for BER = 10−3 at 25 Gb/s.

We propose a computationally efficient and frequency-offset-tolerant channel estimation and synchronization method for polarization-division-multiplexed (PDM) coherent optical OFDM (CO-OFDM). Using this method, we demonstrate a 43-Gb/s PDM CO-OFDM transmission with 16-QAM subcarrier modulation over 5,200-km of ultra-large-area fiber.

The electroplating and screen printing are widely used in the micro-electric industry but they have disadvantages of a complicated series of bumping process, equipments and materials. Furthermore, they are not suitable for the fine pitch bumping technology. To overcome these weak points, a maskless bumping technology using SBM has been developed. Solder Bump Masker (SBM) technology does not need any special equipment and mask tools. It is composed of solder powder and a resin. The solder is Sn58Bi and the resin is designed to have low viscosity for theological characteristics of the solder droplets. In this paper, we optimized the bumping condition with controlling the process time. After bumping, the coining process, which the various loads were applied, has been investigated to get the bump with the extremely uniform heights. Finally, low-volume bumps with the excellent uniformity were successfully achieved.

Solder-on-pad (SoP) technology gives the fine-pitch flip chip bonding manufacturability and reliability. For the SoP technology with pitch equal to or less than 150 µm pitch, there are many candidates. The cost-effectiveness will be one of the major criteria determining the industry preference. A novel bumping material, which is composed of a resin and Sn3Ag0.5Cu (SAC305) solder power, has been developed for the maskless solder-on-pad technology (SoP) of the fine pitch flip chip bonding. With this material, the solder bump array was successfully formed with pitch of 150 µm in one direction.

In this paper, a 3D system in package (SiP) module using through silicon vias (TSV) and novel solder bump maker (SBM) has been presented. The SBM is a paste material which is composed of the solder powder and polymer resin. The polymer resin had the smart properties to eliminate the oxide layers on the solder powder and electrode and to form the solder bumps on the electrodes using the rheological behavior of the droplets without any aligning methods. The five chips with TSVs were stacked on a Si interposer with the three redistribution layers (RDL) using the solder bumps formed by SBM and a fluxless underfill material.