305 results on '"Kikuchi, Katsuya"'
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52. Thermal Stress Comparison of Annular-Trench-Isolated (ATI) TSV with Cu and Solder Core
53. Development of Backside Buried Metal Layer Technology for 3D-ICs
54. In-Place Power Noise and Signal Waveform Measurements on LVDS Channels in Fan-Out Multiple IC Chip Packaging
55. Development of Three-Dimensional Integration Technology for Magnetic Random Access Memories
56. Design, Manufacturing, and Packaging Technology for Superconducting Quantum Annealing Machines
57. 3D-IC Technology for Contribution to the IoT Society
58. Advancement of Power Integrity Utilizing Device Embedded Technology
59. 3D IC Stacking Technology for Reducing Power Consumption of Logic LSI System
60. Toward Practical-Scale Quantum Annealing Machine for Prime Factoring
61. Influence on Particle Double-Network Gels by Gamma Irradiation and Improvement of Radiation Tolerance
62. Fabrication and stacking of through-silicon-via array chip formed by notchless Si etching and wet cleaning of first metal layer
63. Wafer-level hybrid bonding for Cu/Interlayer-dielectric bonding
64. Investigation of mechanism of corrosion resistance of Pd coated Cu wire joint by pseudo process
65. A Thick Cu Layer Buried in Si Interposer Backside for Global Power Routing
66. Hardness Characteristics of Au Cone-Shaped Bumps Targeted for 3-D Packaging Applications
67. Cool Interconnect: A 1024-bit Wide Bus for Chip-to-Chip Communications in 3-D Integrated Circuits
68. Fine Cone-shaped Bumps for Three-dimensional LSI Package—An Optimization of Thermocompression Bonding Process
69. X-ray detection using superconducting tunnel junction with polyimide insulation layer
70. Heat transfer study of 3D packaging structure with superconducting TSV for practical-scale quantum annealing machines
71. Synthesis of Particle Double-Network Gels by Redox Polymerization
72. Interlayer Dielectric Bonding for 300mm Wafers
73. Residual stress investigation of via-last through-silicon via by polarized Raman spectroscopy measurement and finite element simulation
74. 3D Integration System Group, Nanoelectronics Research Institute (NeRI), National Institute of Advanced, Industrial Science and Technology (AIST)
75. Process evaluation of pyramidal and cone-shaped nanoparticle deposition (NPD) bumps using a thermally resistant resist
76. Investigation of transient thermal dissipation in thinned LSI for advanced packaging
77. Evaluation of substrate noise suppression method to mitigate crosstalk among trough-silicon vias
78. Measurement and Analysis of Power Noise Characteristics for EMI Awareness of Power Delivery Networks in 3-D Through-Silicon Via Integration
79. Fluidic platform with embedded differential capacitively coupled contactless conductivity detector for micro-object sensing
80. Designing Efficient Parallel Processing in 3D Standard-Chip Stacking System with Standard Bus
81. Development of a high-yield via-last through silicon via process using notchless silicon etching and wet cleaning of the first metal layer
82. Coplanar differential capacitively coupled contactless conductivity detection (CD-C4D) sensor for micro object inside fluidic flow recognization
83. Three-dimensional integration technology of magnetic tunnel junctions for magnetoresistive random access memory application
84. Metal Contamination Evaluation of Via-Last Cu TSV Process Using Notchless Si Etching and Wet Cleaning of the First Metal Layer
85. Superior decoupling capacitor for three-dimensional LSI with ultrawide communication bus
86. Substrate monitoring system for inspecting defects in TSV-based data buses
87. (Invited) Direct Bonding and Its Interface for High-Density Integration of Superconducting Qubits.
88. 局所剛性行列を用いた弾性体シミュレーション手法の提案
89. Low-cost optical subassembly using VCSEL pre-self-aligned with optical fiber for optical interconnect applications
90. Wet cleaning process for high-yield via-last TSV formation
91. EMI performance of power delivery networks in 3D TSV integration
92. Low Residual Stress in Si Substrate of Annular-Trench-Isolated TSV
93. A Prospective Low-k Insulator for Via-Last through-Silicon-Vias (TSVs) in 3D Integration
94. Copper-Filled Through-Silicon Vias With Parylene-HT Liner
95. Developing a leading practical application for 3D IC chip stacking technology
96. Developing an application for 3D IC chip stacking technology
97. High-speed optical three dimensional measurement method for micro bump inspection in 3D LSI chip stacking technology
98. Sensitivity of the thermal profile of bump-bonded 3D systems to inter-die bonding layer properties
99. Investigation into the thermal effects of thinning stacked dies in three-dimensional integrated circuits
100. Investigation of effects of metalization on heat spreading in bump-bonded 3D systems
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