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SUMMARY The conventional magnetic tunneling junction (MTJ)-based non-volatile D flip-flop (NVDFF) has a slow D-Q delay and a tradeoff between its D-Q delay and its sensing current. In addition, a sufficient write current cannot be obtained with the core device, since two MTJs exist in the write path and a write current degradation problem occurs due to the precharge transistors. The proposed MTJ-based non-volatile semidynamic flip-flop (NVSDFF) has a semidynamic structure that ensures a fast D-Q delay and separates the sensing circuit from the D-Q signal path to reduce the sensing current without affecting the D-Q delay. The proposed NVSDFF also provides a sufficient write current by merely using the core device, since only one MTJ exists in the write path. In addition, the head switch, which is added to remove the write current degradation problem, further reduces the sensing current. Thus, the proposed NVSDFF has a higher read disturbance margin than the previous NVDFF with an IO device. The HSPICE simulation results with the industry-compatible 45 nm model parameter show that the D-Q delay in the proposed NVSDFF is 50.5% of that of the previous NVDFF with an IO device, and the sensing current, 32.3%. In the proposed NVSDFF, the read disturbance margin is 15.9% larger than in the previous NVDFF with an IO device, and the area is 17.8% smaller. Copyright © 2012 John Wiley & Sons, Ltd. [ABSTRACT FROM AUTHOR]

Commercializing spin-transfer-torque magnetic random access memory (STT-MRAM) requires thorough investigation of magnetic tunnel junctions (MTJs) at temperature corners. In this paper, high-temperature behaviors of MTJs are investigated in conjunction with temperature-dependent transistor characteristics in order to ensure reliable high-temperature operation of STT-MRAM. [ABSTRACT FROM AUTHOR]

Back-end-of-the-line (BEOL) interconnect becomes a limiting factor to circuit performance in scaled complementary metal-oxide-semiconductor design. To accurately extract its paratactic capacitance for circuit simulation, compact models should be scalable with wire geometries and should capture the latest technology advances, such as the air gap and Cu diffusion barrier. This paper achieves these goals based on the distribution of the electric field in on-chip BEOL structures. By decomposing the electric field into various regions, the proposed method physically solves each basic capacitance component into a close-form solution; the total ground and coupling capacitances are then the sum of all related components. Such a component-based approach is convenient in incorporating new interconnect structures. Its physics basis minimizes the complexity and the error in a traditional model fitting process. Compared with Raphael simulations at the 45-nm node, the new compact model accurately predicts the capacitance value, even in the presence of the air gap and diffusion barrier, covering a wide range of BEOL dimensions. The complete set of equations will be implemented at http://www.eas.asu.edu/∼ptm. [ABSTRACT FROM AUTHOR]

The inherent switching current asymmetry (β) pertaining to ordinary magnetic tunnel junctions (MTJs) significantly reduces the write margin of spin-transfer-torque magnetoresistive random access memory (STT-MRAM). In this letter, we report how β can be controlled by the effective magnetostatic field (He) that develops along the easy axis of the MTJs. As He is varied by 24% of the effective uniaxial anisotropy field,β measured at 100 ns is reduced from 1.51 to 1.04. The results suggest that tuning the magnetostatic offset field (Hoff) arising from the dipolar coupling between adjacent ferromagnetic layers can control β and improve the write margin of STT-MRAM. [ABSTRACT FROM AUTHOR]