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A spatial light modulator (SLM) is the key component for a digital holographic display system. It requires both ultrahigh- resolution fine pixel integration and large-area panel to get a wide viewing angle and large realistic 3D images. Because these requirements collide with each other, it is very difficult to develop the digital holography system satisfying the standard of the general public. Unlike conventional SLMs, which are based on small size semiconductor ICs, we have developed larger size, highresolution SLM on glass (SLMoG) using both semiconductor and display fabrication technologies. 1-μm channel length oxide TFTs are integrated for pixel switching and the liquid crystal (LC) of high refractive index anisotropy was used to modulate the phase of incident light. Multiple high-speed interface boards and large channel driver ICs are used to drive large size holographic image data. 2.16-inch 16K SLMoG panel with 3-μm horizontal pixel pitch was successfully developed for the first time. Without the aid of additional instruments, it was possible to observe a simple 3D objects with the naked eye. For even wider viewing angle and larger size SLMoG, the proof of concept SLMoG panel for still image hologram with smaller pixel pitches was developed to evaluate cross-talk between adjacent LC pixels.

In this paper, a new light-adaptable display (LAD) structure with minimum power consumption is proposed for the future advertising service, and the demonstrated results are reported. An organic light-emitting diode with color reflection (colored OLED) was applied for the reflective- and emissive-mode device, and a guest-host liquid-crystal device (GH-LC) was adopted for the light shutter device. The current efficiency and reflectance of the colored OLED were 35.15 cd/A at 457 cd/m2 luminance and 63% for the yellow color, respectively. The measured contrast ratio of GH-LC was 15.5:1 at dark-room conditions, respectively. Transparent oxide thin-film transistors were used for the backplane, and their average mobility was 9.08 cm2/V s, with a 0.5 standard deviation. Through the optimization of the fabrication process and the structures of each device, the LAD adaptively operating according to the environmental illuminance from dark to 10,000 nits was successfully demonstrated. Moreover, a new LAD driv...

We fabricated high performance back channel etch (BCE) IZO/AIZTO double-layer channel oxide thin-film transistors (TFTs) and analyzed their electrical characteristics and photostability of the devices. The field-effect mobility of 53.2 cm2/Vs was obtained, and we expect IZO/AIZTO double-layer BCE TFT can be used as a backplane devices for next generation high performance display applications.

The realization of high performance solution-processable metal oxide thin-film transistors (TFTs) with low annealing temperatures remains a challenge in the field of flexible and/or transparent electronics. Indium-based metal oxides are one of the most widely used materials as channel layers of metal oxide TFTs. However, the need for developing indium-free metal oxide materials has become urgent because of the high cost and limited supply of indium. Herein, we report high-performance solution-processed indium-free metal oxide TFTs prepared with low annealing temperatures by introducing ZnO/SnO2 bilayer heterostructures. After photo- and thermal annealing, ZnO/SnO2 bilayers form a unique nanostructure composed of three zones: Zn-only, Zn–Sn-mixed, and Sn-rich zones. The resulting ZnO/SnO2 TFTs exhibit outstanding mobility values as high as 15.4 cm2 V−1 s−1 with a low annealing temperature of 300 °C. These values are the highest yet measured among indium-free and solution-processed metal oxide TFTs prepared under similar annealing conditions. The ZnO/SnO2 TFTs also show remarkable outstanding operational stabilities under various external bias stresses. Their high performances and excellent stabilities can be attributed to the combinational effects of the highly conductive ultrathin Sn-rich channel and balanced carrier concentrations in the Zn–Sn-mixed region. We believe that our work provides a facile route to prepare inexpensive solution-processed electronic devices with earth-abundant materials such as backplane circuits for large-area and flexible displays.

New circuit architecture composed of nonvolatile memory thin-film transistors (M-TFTs) and oxide–semiconductor TFTs (Ox-TFTs) has been proposed to realize low-power consumption and compact size for dynamic driving circuit applications. In order to compensate the slow operation speed of the nonvolatile M-TFTs in the dynamic driving circuits, we proposed the read-out modulation (ROM) scheme. The device operation characteristics of the M-TFTs were confirmed under various specified conditions to effectively apply the ROM, in which a top-gate structure was fabricated to be ferroelectric poly(vinylidene fluoride-trifluoroethylene) gate insulator/Al2O3/In–Ga–ZnO active layers. Full fabrication processes for the M-TFTs were optimized, so that they can be integrated with Ox-TFTs on the same glass substrate. The memory device characteristics, including the current ratios between ON- and OFF-programmed drain current ( $I_{D}$ ) values ( $I_{p-\mathrm {\mathrm{\scriptscriptstyle ON}}}/I_{p-\mathrm {\mathrm{\scriptscriptstyle OFF}}})$ before and after the ROM, drain-bias dependence of the $I_{p-\mathrm {\mathrm{\scriptscriptstyle ON}}}/I_{p-\mathrm {\mathrm{\scriptscriptstyle OFF}}}$ , and the program $I_{D}$ scalability, were confirmed for the fabricated M-TFT. These results suggest the feasibility of a low-power display driver circuit embedded with the nonvolatile M-TFTs.

In this letter, high-performance back-channel etch type oxide thin-film transistors (TFTs) with very narrow channel length, $1~\mu \text{m}$ , are presented. To cover the steep slope at the dry-etched gate pattern edge with a thin gate insulator, a triangular-shaped gate spacer was introduced. A 1- $\mu \text{m}$ short-channel oxide TFT is particularly adaptable to next-generation display applications requiring very high resolution. The field-effect mobility ( $\mu _{\mathrm{ FE}})$ , subthreshold slope, turn-on voltage ( $\text{V}_{on})$ , and the on/off ratio were 55.2 cm2/Vs, 0.11 V/decade, 0.13 V, and $6.8\times 10^{9}$ , respectively.

We propose rewritable full-color computer-generated holograms (CGHs) based on color-selective diffraction using the diffractive optical component with the resonant characteristic. The structure includes an ultrathin layer of phase-change material Ge2Sb2Te5 (GST) on which a spatial binary pattern of amorphous and crystalline states can be recorded. The CGH patterns can be easily erased and rewritten by the pulsed ultraviolet laser writing technique owing to the thermally reconfigurable characteristic of GST. We experimentally demonstrate that the fabricated CGH, having a fine pixel pitch of 2 μm and a size of 32.8 × 32.8 mm2, reconstructs the three-dimensional holographic images. In addition, the feasibility of the rewritable property is verified by erasing and rewriting part of the CGH.

To make high mobility oxide thin-film transistors (TFTs) for transparent large displays, the authors fabricated all-oxide TFTs having amorphous mixed-oxide channels of indium oxide (InOx) and zinc oxide (ZnOy). Liquid precursors of 3-(dimethyl amino)propyl-dimethyl indium (C7H18InN) and diethyl zinc [(C2H5)2Zn] and oxygen plasma were used to form mixed-oxide channels by plasma-enhanced atomic layer deposition (ALD). The authors varied the cycle ratio of InOx and ZnOy to deduce the optimal ratio of InOx:ZnOy for high performance TFTs. X-ray photoelectron spectroscopy analyses were performed to reveal the decrease in the oxygen-deficient state as the fraction of InOx increases. At a deposition cycle ratio of InOx:ZnOy = 2:1, the TFT demonstrated the best performance of field effect mobility of 30.3 cm2/V s, subthreshold of 0.14 V/decade, and Ion/Ioff ratio of 3.1 × 109. By adjusting the relative cycles of different oxides in an ALD process, one may obtain the desired mixed-oxide channel TFT properties, which is not readily possible in the sputtering process. By varying the compositions of the oxide channel layer, the latitude of device fabrication could be widening, thereby enabling performance customization.To make high mobility oxide thin-film transistors (TFTs) for transparent large displays, the authors fabricated all-oxide TFTs having amorphous mixed-oxide channels of indium oxide (InOx) and zinc oxide (ZnOy). Liquid precursors of 3-(dimethyl amino)propyl-dimethyl indium (C7H18InN) and diethyl zinc [(C2H5)2Zn] and oxygen plasma were used to form mixed-oxide channels by plasma-enhanced atomic layer deposition (ALD). The authors varied the cycle ratio of InOx and ZnOy to deduce the optimal ratio of InOx:ZnOy for high performance TFTs. X-ray photoelectron spectroscopy analyses were performed to reveal the decrease in the oxygen-deficient state as the fraction of InOx increases. At a deposition cycle ratio of InOx:ZnOy = 2:1, the TFT demonstrated the best performance of field effect mobility of 30.3 cm2/V s, subthreshold of 0.14 V/decade, and Ion/Ioff ratio of 3.1 × 109. By adjusting the relative cycles of different oxides in an ALD process, one may obtain the desired mixed-oxide channel TFT properties, whic...

SLM (Spatial Light Modulator) with ultra fine pixel pitch (circa 1 micron meter) has been thought as a big issue to realize electronic hologram with wide viewing angle. Two types of approach are proposed for accomplish SLM panel with 1 micron meter pitch pixel. SLM with LC light modulator controlled by TFT based backplane constructed on glass substrate is proposed according to the methods of scaling down flat-panel display technology. Introduction of sub micron meter patterning processes, the SLM panel with 3 micron meter pitch pixel was successfully developed for the first time. The SLM with 2 inch diagonal length had the resolution of 16K by 2K. Hologram with depth was reconstructed with manufactured SLM. Oxide semiconductor TFTs of 1 micron meter channel length with high performance have been developed for the SLM. Technical issues to accomplish 1 micron meter pitch pixel will be discussed. PCM (phase change material) has been used for memory devices and information recording devices. In former case, information is recorded and read using electrical signal. For latter case, information is recorded and read using light (laser) signal. We propose a SLM with PCM such that information is recorded using electrical signal and read using light signal. The light modulation of PCM pattern recorded by pulsed laser was successfully demonstrated using reconstruction of hologram images. Operation of arrayed pixels with PCM pattern driven by Si MOSFET is under development. Technical challenges for SLM with PCM will be discussed.

We report the electrical characteristics of backchannel etch (BCE) metal–oxide–semiconductor thin-film transistor (TFT) comprised of aluminum-doped tin–zinc–indium oxide (ATZIO). It has high etch selectivity in wet chemical etchants, which consist of H3PO4, CH3COOH, and HNO3. This is contrary to the conventional metal–oxide–semiconductors of indium–gallium–zinc oxides, which are highly soluble in the acidic chemicals. As a result, no etch stop layer is needed to protect the backchannel from the wet etchant damage during the source and drain patterning in the bottom-gate-staggered TFT structure. This provides the possibility of oxide TFT fabrication process made as simple as that of the current amorphous silicon TFT using three or four photomasks with short channel length and less parasitic capacitance. The electrical characteristics of our ATZIO BCE-TFTs have the mobility of 21.4 cm2/ $\text{V}\cdot \text{s}$ , subthreshold swing (S.S) of 0.11 V/decade, and threshold voltage of 0.8 V. In spite of the BCE structure, they have excellent stability against bias temperature stress, which shows the threshold voltage shifts of +0.75 V and −0.51 V under the prolonged positive (+20 V) and negative (−20 V) gate bias stresses for 10 000 s at 60 °C, respectively.

Nonvolatile memory thin-film transistors (TFTs) fabricated on paper substrates were proposed as one of the eco-friendly electronic devices. The gate stack was composed of chicken albumen gate insulator and In-Ga-Zn-O semiconducting channel layers. All the fabrication processes were performed below 120 °C. To improve the process compatibility of the synthethic paper substrate, an Al2O3 thin film was introduced as adhesion and barrier layers by atomic layer deposition. The dielectric properties of biomaterial albumen gate insulator were also enhanced by the preparation of Al2O3 capping layer. The nonvolatile bistabilities were realized by the switching phenomena of residual polarization within the albumen thin film. The fabricated device exhibited a counterclockwise hysteresis with a memory window of 11.8 V, high on/off ratio of approximately 1.1 × 10(6), and high saturation mobility (μsat) of 11.5 cm(2)/(V s). Furthermore, these device characteristics were not markedly degraded even after the delamination and under the bending situration. When the curvature radius was set as 5.3 cm, the ION/IOFF ratio and μsat were obtained to be 5.9 × 10(6) and 7.9 cm(2)/(V s), respectively.

Amorphous indium gallium zinc oxide thin-film transistors (TFTs) were fabricated and characterized on flexible poly(ethylene naphthalate) (PEN) substrates. A hybrid inorganic/organic double-layered barrier layer structure was proposed for enhancing the permeability and the surface roughness of the PEN substrates, which was composed of a 3 μm-thick spin-coated organic layer and a 50 nm-thick atomic-layer-deposited Al2O3 inorganic layer. The saturation mobility, subthreshold swing, and on/off ratio of the TFTs on the PEN substrates with the proposed hybrid barrier structure were found to be approximately 15.5 cm2 V−1 s−1, 0.2 V dec−1, and 2.2 × 108, respectively. These good TFT performances were not degraded even under the mechanical bending situation at a curvature radius of 3.3 mm and after the repetitive bending cycles. Furthermore, the variations in turn-on voltage of the TFT were evaluated to be approximately as small as −0.1 and +1.6 V under the negative and positive-bias stress tests, respectively.

Active matrix organic light-emitting diodes (AMOLEDs) are considered to be a core component of next-generation display technology, which can be used for wearable and flexible devices. Reliable thin-film transistors (TFTs) with high mobility are required to drive AMOLEDs. Recently, amorphous oxide TFTs, due to their high mobility, have been considered as excellent substitutes for driving AMOLEDs. However, the device instabilities of high-mobility oxide TFTs have remained a key issue to be used in production. In this paper, we present the charge-trapping and device instability mechanisms of high-mobility oxide TFTs with double active layers, using In-Zn-O (IZO) and Al-doped Sn-Zn-In-O (ATZIO) with various interfacial IZO thicknesses (0-6 nm). To this end, we employed microsecond fast current-voltage (I-V), single-pulsed I-V, transient current, and discharge current analysis. These alternating-current device characterization methodologies enable the extraction of various trap parameters and defect densities as well as the understanding of dynamic charge transport in double-active-layer TFTs. The results show that the number of defect sites decreases with an increase in the interfacial IZO thickness. From these results, we conclude that the interfacial IZO layer plays a crucial role in minimizing charge trapping in ATZIO TFTs.

We adopted SiO2 film by means of plasma enhanced atomic layer deposition (PEALD) as the first gate insulator of top gate IGZO TFT. TFT post-annealed at 300oC shows mobility, Vth, and S.S of 39.9 cm2/V.s, -1V, and 0.32 V/dec., respectively. We investigated the effect of H in the gate insulator during the annealing with the comparison of bottom gate coplanar TFT with ALD grown alumina film as the gate insulator.

Oxide TFTs have been considered as a good candidate for the application to backplane device for high quality TFT-LCD and large area OLED panel. It is well known that the passivation play the very important role for the development of the high quality oxide TFTs. The criteria for good passivation layer can be a barrier for environmental factors, not having doping source during thermal annealing, and playing a role of curing the defective interface. The evolution of the resistance of active films during thermal annealing was monitored under the split of passivation layers and active layers. ALD deposited Al2O3 layer and PECVD SiO2 layer were applied for the passivation layer and sputter deposited Al-doped InZnSnO and InGaZnO were applied for the active layer. It is found that Al2O3 passivation layer supplies dopants to the active interface (possibly H) during high temperature annealing and the side wall of AIZTO pattern contains many defects, which become dopants during high temperature annealing through detailed measurement of resistance of patterned oxide thin films with various sizes. It is suggested that PECVD SiO2 with proper pre-treatment (possibly N2O plasma treatment) will be best candidate for the passivation layer in the oxide TFTs, especially in the case of oxide TFTs with high mobility.

ZnO–SnO 2 nanocomposite thin films were produced using pulsed laser ablation of pie-shaped ZnO–SnO 2 oxides target, and their field effect electronic transport properties investigated as a function of annealing temperature. The films have a nanocomposite structure consisting of ZnO and SnO 2 nanoparticles. The amorphous ZnO–SnO 2 nanocomposite thin films, as oxide semiconductors, exhibited excellent electronic transport properties with saturation mobility of around 16.9 cm 2 /V s, turn-on voltage of ~−1 V, subthreshold swing of 0.22 V/decade, and high drain current on-to-off ratio of over 10 10 , enough to operate for next-generation microelectronic devices. These results are presumed due to the unique electronic structure of amorphous nanocomposite coupled with two heavy-metal Zn and Sn cations having spherically symmetric s-orbitals.

In oxide thin-film transistors (TFTs), light illumination effect is a big concern due to its operating condition. Light illumination can change many electrical properties in oxide TFTs such as mobility and threshold voltage (V th ). In many researches, Oxygen vacancy is suspected as a main cause of the changes by light illumination. Recently, the back channel formation by field-induced macroscopic barrier model is reported under light illumination. This is also related to Oxygen vacancy. In this letter, we investigate the gradual changes in DC and CV characteristics depending on the dual-channel thicknesses. For this purpose, we use the aluminum-doped indium zinc tin oxide (AIZTO)/indium zinc oxide (IZO) dual-channel TFTs. The main goal of this paper is to find the main cause of the changes by light illumination in various dual-channel thicknesses.

A simple and selective technique which immobilizes protein onto a solid substrate by using UV illumination has been developed. In protein immobilization, a Bovine serum albumin (BSA) performed bifunctional role as a cross-linker between substrate and proteins and as a blocker inhibiting a nonspecific protein adsorption. A new photo-induced protein immobilization process has been investigated at each step by fluorescence microscopy, ellipsometry, and Fourier transform infrared (FT-IR) spectroscopy. A UV photomask has been used to induce selective protein immobilization on target regions of the surface of the SiO2 substrates under UV illumination with negligible nonspecific binding. The UV illumination also showed improved photostability than the conventional methods which employed bifunctional photo-crosslinker molecules of photo-reactive diazirine. This new UV illumination-based photo-addressable protein immobilization provides a new approach for developing novel protein microarrays for multiplexed sensing as well as other types of bio-immobilization in biomedical devices and biotechnologies.

This paper describes a new technique for the detection of uncharged or feebly charged small molecules (

We demonstrate the application of ‘top-down’ fabricated Si nanochannel field effect transistor biosensors in measuring the configuration of charged proteins immobilized on the Si surface. We have immobilized monoclonal antibodies of PSA (anti-PSA) on the p-type Si channel surface, and monitored the channel conductance in response to the variation of ionic strength (salt concentration) and pH level of the buffer solution. The dependency of channel conductance on the salt concentration is consistent with the screening of protein charges by dissolved counterions, enabling quantitative estimation of the distance from the Si surface to anti-PSA molecules based on calculated Debye screening lengths (λD) for each salt concentration. The effect of salt concentration on the pH-dependency of channel conductance has also been studied, and explained in terms of the net charge of anti-PSA as a function of pH.

We fabricated amorphous AlZnSnInO TFT with back channel etch structure. Source/drain electrode of molybdenum (Mo) was formed using mixed acid based Mo/Al/Mo etchant for the first time in the fabrication of a-oxide BCE TFT. SEM and ESCA analysis showed no Mo residue on the surface of active layer. The BCE AlZnSnInO TFT showed mobility of 23.2 cm2/V.s, S.S of 0.13 V/dec., and Von of -0.5V. We show highly stable high mobility BCE TFT achieved by optimizing passivation process and active layer deposition condition.

We report highly stable and high mobility aluminum-doped indium zinc tin oxide (AIZTO) thin-film transistor with field effect mobility larger than 30 cm2/Vs in the bottom gate, etch-stopper structure. The electrical instabilities against positive gate bias stress, negative gate bias stress, and negative gate bias under illumination stress are investigated..

Optical absorbers have been a topic of intense research due to their importance in many applications. In particular, multi-band and perfect absorption features in a desired frequency range are essential in broadband applications. In this work, we numerically studied the absorption properties of subwavelength metallic gratings coated with a dielectric layer. Here, the structure is considered to be an integration between a resonant cavity and a subwavelength metallic grating. Two appropriately designed structures can exhibit multi-band absorption properties. In addition to the numerical simulation results, we elaborate on determining the appropriate structural parameters that yield the desired spectral absorption profile in the visible range. We also numerically identify critical coupling conditions for perfect absorption.

In this study, we have developed a new detection method using Si field effect transistor (FET)-type biosensors, which enables the direct monitoring of antigen-antibody binding within very high-ionic-strength solutions such as 1×PBS and human serum. In the new method, as no additional dilution or desalting processes are required, the FET-type biosensors can be more suitable for ultrasensitive and real-time analysis of raw sample solutions. The new detection scheme is based on the observation that the strength of antigen-antibody-specific binding is significantly influenced by the ionic strength of the reaction solutions. For a prostate specific antigen (PSA), in some conditions, the binding reaction between PSA and anti-PSA in a low-ionic strength reaction solution such as 10 µM phosphate buffer is weak (reversible), while that in high-ionic strength reaction solutions such as 1×PBS or human serum is strong.

In order to identify changes in the levels of key proteins in response to the onset or development of a disease, the research fields of proteomics and genomics seek to develop new biomarkers. Specifically, simple and fast biomarker screens have a central role in many areas of healthcare, including disease diagnosis and drug discovery. Biologically modified field-effect transistor (BioFET) is one of the most attractive approaches because of the on-chip integration of the sensor array, fast response, high reliability and low-cost mass production. However, the BioFETs used to detect macromolecules have been operated only in buffer solution with low salt concentrations because of the Debye screening length of blood or serum. Here we report a novel detection technique for direct label-free immunodetection of cancer markers in human serum using a Si-FET that was fabricated by conventional photolithographic processes. The proposed sensing method shows no dissociation of antigen-antibody binding as in general immunoassays, unlike the previous reports on Si-FET sensors. This method therefore overcomes the Debye length problem of immunodetection in human fluids, such as serum, that are generally encountered by FET-based biosensors. Our results demonstrate specific label-free and real-time immunodetection of a cancer marker at a concentration of 0.2 ng/mL in human serum, quantitative detection of the marker from 0.2 to 114 ng/mL, and successful multiplexed sensing of three different cancer markers. We believe that connecting our simple electrical detection method, which does not require pretreatment of serum, with well-established whole blood filter technology will contribute to the development of new point-of-care testing (POCT) sensors.

We developed a high-resolution active matrix spatial light modulator on a glass substrate. To integrate a switching device on the glass substrate, we designed a high-performance oxide thin-film transistor with a minimum channel length of 1 μm and a maximum processing temperature of 380°C. To drive a large number of data lines, we used multiple source drivers and data drivers as well. For an optical modulation, we optimized a liquid crystal of a high anisotropic refractive index of 0.25 with a cell gap of 2.5 μm, which was effectively operated until pixel pitch is 1.6 μm. Hologram was successfully reconstructed by fabricated SLM with 7-μm pixel pitch. For the other approach for a high-resolution spatial light modulator, we tested a phase change material of Ge2Sb2Te5 [GST]. The variation of refractive index between a polycrystalline phase and an amorphous phase of the GST film is used for a hologram reconstruction. By optimizing the underlying oxide thickness, we can show a color hologram without color filters.

Correction for ‘Rewritable full-color computer-generated holograms based on color-selective diffractive optical components including phase-change materials’ by Chi-Young Hwang et al., Nanoscale, 2018, DOI: 10.1039/c8nr04471f.

We present a simple semiconductor process to fabricate nanogap arrays for application in molecular electronics and nano-bio electronics using a combination of freestanding silicon nanowires and angle evaporation. The gap distance is modulated using the height of the silicon dioxide, the width of the Si nanowires, and the evaporation angle. In addition, we fabricate and apply the nanogap arrays in single-electron transistors using DNA-linked Au nanoparticles for the detection of DNA hybridization.

In this paper, a Schottky barrier polycrystalline silicon thin-film transistor (SB TFT) with erbium silicide source/drain is demonstrated using low temperature processes. A low temperature oxide is used for a gate dielectric and the transistor channel is crystallized by a metal-induced lateral crystallization process. An n-type SB TFT shows a normal electrical performance with subthreshold slope of 239 mV/dec, ION/IOFF ratio of 5.8 × 104 and ION of 2 μA/µm at VG = 3 V, VD = 2.5 V for 0.1 μm device. A process temperature is maintained at less than 600 °C throughout the whole processes. The SB TFT is expected to be a promising candidate for a next system-on-glass technology and an alternative 3D integration technology.

Three-dimensionally stacked CMOS inverters were fabricated by using the poly-Si thin film transistor (TFT) with hafnium-oxide (HfO"2) gate dielectric and Pt gate electrode. For fabrication of 3-D stacked CMOS inverters consist of poly-Si NMOS/interlayer dielectric film (ILD)/poly-Si PMOS, a reduced process temperature is necessary to avoid the degradation of NMOS at lower poly-Si layer fabricated prior to PMOS at upper poly-Si layer. The high quality of laser crystallized poly-Si film was obtained with smooth surface and excellent crystallinity. The 3-D stacked CMOS inverters fabricated by stacking the poly-Si NMOS TFT and PMOS TFT showed good output characteristics, DC voltage transfer characteristics, transient characteristics and voltage gain for applications of the vertical integrated CMOS circuits.

The fabrication methods and characteristics of polycrystalline silicon (poly-Si) thin film transistor (TFT) stacked complementary metal oxide semiconductor (CMOS) inverters were demonstrated the feasibility for high performance logic circuit applications was verified. The laser crystallization processes were compatible with the poly-Si TFT stacked CMOS inverters and the laser crystallized poly-Si films showed uniform grain size with low surface roughness and excellent crystallinity. In order to fabricate three-dimensional (3-D) stacked poly-Si CMOS inverters, the p-channel MOSTFTs (PMOS) at upper poly-Si layer were stacked on the n-channel MOSTFT (NMOS) at lower poly-Si and interlayer dielectric (ILD) layer. The HfO2 gate dielectrics and Pt metal gates were applied to the upper PMOSTFT to avoid the degradation of lower NMOSTFT. The CMOS inverters fabricated by stacking the poly-Si TFTs revealed good characteristics for the 3-D integrated CMOS applications.

3D stacked poly-Si CMOS inverters with a high quality laser crystallized channel were fabricated on bulk Si wafers. In order to fabricate 3D stacked poly-Si CMOS inverters, the PMOS thin-film-transistor (TFT) at upper poly-Si layer were stacked on the NMOS TFT at lower poly-Si layer and interlayer dielectric film. After laser crystallization, grains in poly-Si films were very uniform and the dominant crystalline orientation was (1 1 1) direction. The sub-threshold swing of NMOS and PMOS TFTs was very good, showing 78 mV/dec. and 86 mV/dec., respectively. And the maximum/minimum current ratio of both TFTs was larger than 10 7 which is equivalent to those at the bulk or SOI MOSFET. The DC voltage transfer characteristics and transient characteristics of stacked poly-Si CMOS inverter were good enough for the vertical integrated CMOS applications. We verified the feasibility of 3D stacked CMOS inverter circuit by poly-Si TFT technology.

The effects of barrier layers and channel compositions on the device performances including the bending characteristics and bias-stress stabilities were investigated for the flexible In-Ga-Zn-O (IGZO) thin-film transistors (TFTs). The IGZO TFTs fabricated on the PEN treated with inorganic/organic double-layered barrier layer showed superior properties under the bending situation even at a curvature radius of 3.5 mm, which corresponded to the bending strain of 1.8 %. The IGZO channel composition was controlled by modulating the oxygen partial pressure during the sputtering process and the TFTs demonstrated highly stable performance at a O 2 /(Ar+O 2 ) ratio of 2 %. The threshold shifts for the IGZO TFT were −0.1 and +0.1 V for negative- and positive-bias stress, respectively.

Ultra shallow and abrupt n+–p junctions were formed on a silicon-on-insulator (SOI) using solid phase diffusion from arsenic-doped spin-on dopant source with various rapid thermal annealing (RTA) conditions. Their doping profiles and electrical characteristics were investigated and compared with those of junctions prepared from phosphorous-doped spin-on-dopant. Analysis of arsenic doped n+–p junctions prepared at the drive-in temperature of 950 °C revealed that the junction depth and junction abruptness are 27 nm and 8.5 nm/dec., respectively, which are superior to phosphorus-doped junctions. Moreover, the SOI n-type metal-oxide-semiconductor field effect transistor (MOSFET) with the gate length of 90 nm which source and drain extensions were doped from arsenic spin-on-dopant had good short channel properties.

We have obtained systematic simulation and experimental results for 30-nm-gate-length metaloxide-semiconductor field-effect transistor (MOSFET) fabricated on ultra-thin silicon-on-insulator (SOI) substrates. The two-dimensional process simulation and the device simulation were carried out to optimize the fabrication process conditions and the device characteristics of 30-nm-gatelength SOI MOSFETs. A new simple source/drain formation technique using the solid-phase diffusion (SPD) method was developed. Based on the simulation results and the SPD ultra-shallow junction formation technique, we successfully fabricated 30-nm-gate-length SOI nMOSFETs. The experimental results for the 30-nm-gate-length SOI nMOSFETs showed good transistor behaviors and superior device scalability.

In this work, a switchable plasmonic structure is proposed for reflection-type spatial light modulation in the visible range with subwavelength resolution. This structure is based on a metallic grating in which each resonant cavity couples the incident light into a gap surface plasmon mode and then reflects the light modulated in the cavity. By incorporating an ultrathin layer of the phase-change material Ge2Sb2Te5 at the entrance of the cavity, the optical modulation characteristic of the structure can be switched between two modes. Numerical investigations are conducted to verify the proposed structure, with the focused analysis of two common types of binary modulations: amplitude-only and phase-only modulations.

A novel ultrathin body SOI MOSFET with a recessed source-drain (S/D) structure is proposed to reduce the S/D extension (SDE) resistance and the feasibility on the proposed device is checked. A recessed buried oxide under the SDE regions is completely filled with the heavily doped polysilicon, which can lead to a low SDE resistance. A recessed S/D SOI MOSFET with 30 nm gate length and 5 nm thick undoped channel, was successfully fabricated and showed the good SCE immunities; little punch-through, the drain-induced barrier lowering of 140 mV/V, and the subthreshold slope of 79 mV/dec.

High performance silicon nanowire (SiNW) sensors with SiO2/HfO2/Al2O3 (OHA) engineered sensing thin films were fabricated. A lower interface state density, a larger capacitance and a stronger chemical immunity, which are essential for enhancing the performance of devices, were accomplished by stacking thin SiO2, HfO2, and Al2O3 layers, respectively, in sequence on the SiNW channel. Compared with the conventional single SiO2 thin film, the staked OHA thin films demonstrated improved sensing performances; a higher sensitivity, a lower hysteresis voltage, and a smaller drift rate, as well as a higher output current. Therefore, the SiNW sensors with OHA stacked sensing thin films are very promising to biological and chemical sensor applications.

A plasma-doping technique for fabricating nanoscale silicon-on-insulator (SOI) MOSFETs has been investigated. The source/drain (S/D) extensions of the tri-gate structure SOI n-MOSFETs were formed by using an elevated temperature plasma-doping method. Even though the activation annealing after plasma doping was excluded to minimize the diffusion of dopants, which resulted in a laterally abrupt S/D junction, we obtained a low sheet resistance of 920 /spl Omega///spl square/ by the elevated temperature plasma doping of 527 /spl deg/C. A tri-gate structure silicon-on-insulator n-MOSFET with a gate length of 50 nm was successfully fabricated and revealed suppressed short-channel effects.

Strenuous efforts are being focused on further scaling of metal-oxide-semiconductor field-effect transistors (MOSFETs) into the sub-100 nm regime. Complementary MOS devices (CMOS) fabricated on silicon-oninsulator (SOI) wafers have attracted a lot of attention because of the advantages of full dielectric isolation and reduced junction capacitance over those on bulk silicon wafers in regard to integrated circuit (IC) applications for low stand-by power and high performance. Moreover, the fabrication technique involved in SOI MOSFET can remove or relax some of the process and material constraints on the MOSFET scaling, because it provides a low leakage current, latch-up elimination, high soft error immunity, smaller subthreshold swing, and a simple device structure and process. However, one of the major challenges to overcome is the ultra-shallow junction formation method, which prevents short channel effects for deep sub-100 nm devices [1, 2]. The conventional approach for junction formation is ion implantation with low-energy ion beams. The crystal defects associated with the energetic ion beam bombardment are unavoidable and act as the primary source of junction leakage currents. The junction leakage degrades the device performance and leads to an increase in power consumption. Therefore, an alternative method is required to make use of the advantages of the SOI devices. Doping using solid-phase diffusion (SPD) is an effective method to form damage-free ultra-shallow junctions. In this paper, we report the doping properties of the SPD method and the electrical characteristics of sub-100 nm SOI MOSFETs fabricated using the SPD technique for ultra-shallow source and drain junction formation. The phosphorus doped oxide films used as the SPD source are usually prepared by chemical vapor deposition (CVD), but we used a liquid-state dopant source containing silicon, oxygen and phosphorus. A wafer was coated with the dopant source using a spin coating technique. After baking at 250 ◦C for 20 min, the liquid source was converted to a solid phosphorus doped silicon oxide layer on the top of the wafer. The refractive index and density of this oxide layer were 1.42 and 2.05 g/cm3, respectively. Then the coated wafer was placed in a rapid thermal annealing (RTA) system and a PN junction was created after the phosphorus had diffused into the silicon. In this way, N+P junction diodes and SOI MOSFETs were fabricated. Fig. 1 shows the secondary ion mass spectrometry (SIMS) depth profile of phosphorus for various RTA process temperatures. The RTA process was performed for 30 s in N2 ambient. The diffusion depth of the phosphorus increases with RTA temperature. The surface concentration of phosphorus also increased with the RTA temperature due to the enhanced solid solubility of phosphorus atoms. In nano-scale MOSFET devices, a channel impurity concentration of 1018 cm−3 is required to suppress the short channel effect. It is clear that a shallow junction, less than the 50 nm deep, defined at 1 × 1018 cm−3 can be obtained when the RTA temperature is below 925 ◦C. Fig. 2 shows the relationship between the sheet resistance (Rs) measured using the four-point probe and RTA temperature. The Rs monotonically decreases as the RTA temperature and junction depth increase. The Rs is lower than 1 k Ohm/cm2 at 925 ◦C, which is the maximum drain extension sheet resistance required for 32 nm-technology [3]. Since the surface dopant concentration increased as the RTA temperature increased, more improvements can be expected with control of RTA duration time. Fig. 3 shows the current-voltage (I-V) characteristics of N+P diodes fabricated on SOI substrates by SPD methods. In order to verify the effectiveness of the SPD process, the I-V characteristics of N+P diodes fabricated by the plasma doping method, which is often used in ultra-shallow junction formation, are also shown in Fig. 3 for comparison. It is observed that the forward bias current depends on the RTA temperature. As the RTA temperature increased, the forward bias current increased, while the reverse bias current remained almost constant. The increase in forward bias current could be attributed to the reduction of sheet resistance resulting from high temperature RTA. In the case of the plasma doping sample, the forward bias cur

We report the effect of a rapid thermal annealing process (RTP) on the electrical properties of an aluminum-doped indium zinc tin oxide (Al-IZTO) thin film transistor (TFT) with a back-channel etched (BCE) structure. First, the RTP temperatures were varied from 250 to 350 °C, and their effect on Al-IZTO TFT was investigated. The 250 °C RTP produced the best transfer characteristics (subthreshold swing = 0.11 V/dec, hysteresis = −0.25 V, and mobility = 26.42 cm2 V−1s−1), and as the temperature increased, the TFTs showed slightly degraded properties in hysteresis and subthreshold swing. Through the transmission line method (TLM), the channel shortening effect and contact properties according to the annealing temperature were studied. The reliability against a negative gate bias stress under illumination (NBIS) was also analyzed. At high RTP temperature (>300 °C), stability under NBIS was considerably improved, and the 350 °C RTP device showed turn-on voltage shift of −1.7 V. The microwave photoconductivity decay (μ-PCD) method revealed that the RTP effectively reduced shallow localized states, which enhanced the NBIS stability at high temperature. Finally, the RTP was compared with the conventional furnace process at the same temperature in terms of transfer characteristics and uniformity. Even with a much shorter process time for the RTP, Al-IZTO TFTs exhibited similar or better transfer properties and uniformity to or than the furnace annealing.