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Etheostoma sitikuense (Citico Darter), a federally protected fish endemic to the southeastern United States, was extirpated from Abrams Creek in Great Smoky Mountains National Park in 1957. The species was reintroduced from 1993–2001, but recovery efforts have thus far achieved only partial success, due in part to limited knowledge of Citico Darter habitat use. After distribution of the reintroduced population was established, we monitored Citico Darters in a 4-km section of Abrams Creek using underwater observation. We evaluated macro- and microhabitat use over four summers using principal components analysis to determine macrohabitat variables influencing Citico Darter distribution, and used classification tree methods to analyze microhabitat use. We analyzed dispersal using linear regression to compare historical stocking data with current Citico Darter distribution data. We identified percentage of pools and cobble/small boulder substrates as the most significant macrohabitat variables influe...

Habitat use by smoky madtoms (Noturus baileyi) and yellowfin madtoms (Noturus flavipinnis) was quantified in lower Abrams Creek within the Great Smoky Mountains National Park during the summers of 2007–2010. Variables were measured at both macrohabitat and microhabitat spatial scales within locations where each species was present. Reach-level macrohabitat data were analyzed using principal component analysis to identify variables associated with each species’ presence within a reach. Classification trees were developed to describe microhabitat use for each species and to compare differences in microhabitat use between species. Distributions of both species were similar in lower Abrams Creek with each becoming more abundant within downstream reaches. Smoky madtoms predominantly used riffle and run microhabitats with gravel and cobble basal substrates, while yellowfin madtoms used pool microhabitats away from riffles with low velocity and cobble-sized cover rocks. Neither species was ever encountered withi...

© 2017 IEEE. Power and thermal limitations make it impossible to run all cores on a multicore system at their maximum frequency. Therefore, modern systems require careful power management. These systems must manage complex tradeoffs between energy, power, and frequency, choosing which cores to accelerate to achieve good performance while maintaining energy efficiency or operating under a power budget. Navigating these tradeoffs is especially hard with multi-threaded applications, where performance depends on the relative progress of parallel worker threads between synchronization points. Prior work on chip-level power management for multi-threaded applications has largely relied on indirect heuristics and metrics calculated from low-level performance counters to estimate each thread's progress. However, these indirect metrics are often inaccurate. Instead, we propose to gather progress information directly from software itself. We present ThreadBeats, a simple application-level annotation framework that directly and accurately conveys thread progress information to hardware. We design DVFS controllers that exploit ThreadBeats information for two purposes: (i) improving performance by equalizing thread progress and (ii) minimizing runtime under a power budget constraint. These controllers reduce wait time at barriers by 77% on average and improve energy-delay product under a power budget by 23% over prior work.

The purpose of this review is to provide an analysis of the latest developments on the functions of the carbon catabolite-repression 4-Not (Ccr4-Not) complex in regulating eukaryotic gene expression. Ccr4-Not is a nine-subunit protein complex that is conserved in sequence and function throughout the eukaryotic kingdom. Although Ccr4-Not has been studied since the 1980s, our understanding of what it does is constantly evolving. Once thought to solely regulate transcription, it is now clear that it has much broader roles in gene regulation, such as in mRNA decay and quality control, RNA export, translational repression and protein ubiquitylation. The mechanism of actions for each of its functions is still being debated. Some of the difficulty in drawing a clear picture is that it has been implicated in so many processes that regulate mRNAs and proteins in both the cytoplasm and the nucleus. We will describe what is known about the Ccr4-Not complex in yeast and other eukaryotes in an effort to synthesize a unified model for how this complex coordinates multiple steps in gene regulation and provide insights into what questions will be most exciting to answer in the future.

Underwater observation is a widely used fish-sampling method, but capture efficiencies of this method are often unknown. For accuracy, survey counts require correction by measuring capture efficiencies of sampling protocols. Capture efficiencies for underwater observation were calculated for three small imperiled fishes—Etheostoma sitikuense (Citico Darter), Noturus flavipinnis (Yellowfin Madtom), and Noturus baileyi (Smoky Madtom)—using modified mark-recapture methods. Fishes were tagged with visual implant elastomer tags, released at sites within Abrams Creek in the Great Smoky Mountains National Park, and then recaptured. Efficiencies were calculated by comparing numbers of released individuals to recaptures. In the propagation facility, tag retention was 100 percent, and no post-tagging mortality was observed. Capture efficiency (CE = 0.12) was low for all species and potentially influenced by predation upon marked fish, emigration of fish from sites, or difficulty in sampling some habitats. ...

This paper presents a self-aware processor with energy monitoring circuits that can measure actual energy consumption of the key blocks. The monitors are embedded into on-chip DC/DC converters and generate results within 10% of accuracy with minimal power (

It is now known that the synthesis and decay of mRNAs are coordinated; however, the factors involved in this process and the mechanism of how these two distinct events are linked are not known. The...

Recent advances in nanophotonic device research have led to a proliferation of proposals for new architectures that employ optics for on-chip communication. However, since standard simulation tools have not yet caught up with these advances, the quality and thoroughness of the evaluations of these architectures have varied widely. This paper provides the first complete end-to-end analysis of an architecture using on-chip optical interconnect. This analysis incorporates realistic performance and energy models for both electrical and optical devices and circuits into a full-fledged functional simulator, thus enabling detailed analyses when running actual applications. Since on-chip optics is not yet mature and unlikely to see widespread use for several more years, we perform our analysis on a future 1000-core processor implemented in an 11nm technology node. We find that the proposed optical interconnect can provide between 1.8x and 4.8x better energy-delay product than conventional electrical-only interconnects. In addition, based on a detailed energy breakdown of all processor components, we conclude that a thermal ring resonators and on-chip lasers that allow rapid power gating are key areas worthy of additional nanophotonic research. This will help guide future optical device research to the areas likely to provide the best payoff.

Inspired by BIO2010 and leveraging institutional and external funding, Truman State University built an undergraduate program in mathematical biology with high-quality, faculty-mentored interdisciplinary research experiences at its core. These experiences taught faculty and students to bridge the epistemological gap between the mathematical and life sciences. Together they created the infrastructure that currently supports several interdisciplinary courses, an innovative minor degree, and long-term interdepartmental research collaborations. This article describes how the program was built with support from the National Science Foundation's Interdisciplinary Training for Undergraduates in Biology and Mathematics program, and it shares lessons learned that will help other undergraduate institutions build their own program.

Based on current trends, multicore processors will have 1000 cores or more within the next decade. However, their promise of increased performance will only be realized if their inherent scaling and programming challenges are overcome. Fortunately, recent advances in nanophotonic device manufacturing are making CMOS-integrated optics a reality-interconnect technology which can provide significantly more bandwidth at lower power than conventional electrical signaling. Optical interconnect has the potential to enable massive scaling and preserve familiar programming models in future multicore chips. This paper presents ATAC, a new multicore architecture with integrated optics, and ACKwise, a novel cache coherence protocol designed to leverage ATAC's strengths. ATAC uses nanophotonic technology to implement a fast, efficient global broadcast network which helps address a number of the challenges that future multicores will face. ACKwise is a new directory-based cache coherence protocol that uses this broadcast mechanism to provide high performance and scalability. Based on 64-core and 1024-core simulations with Splash2, Parsec, and synthetic benchmarks, we show that ATAC with ACKwise out-performs a chip with conventional interconnect and cache coherence protocols. On 1024-core evaluations, ACKwise protocol on ATAC outperforms the best conventional cache coherence protocol on an electrical mesh network by 2.5x with Splash2 benchmarks and by 61% with synthetic benchmarks., National Science Foundation (U.S.) (Grant No. 0811724)

Community colleges are emerging as important institutions for the production of science, technology, engineering, and mathematics (STEM) graduates. More than 40% of all undergraduate engineering majors nationally attended community colleges at some point in their academic careers (Tsapogas, 2004). Most importantly, community colleges are used by greater numbers of minority and female students, older students and students from lower socioeconomic strata; all underrepresented in engineering. The demographics of community college students are certainly not static—a rise in attendance by traditionally aged students and a decline in attendance by older students is predicted to continue (Bryant, 2001). Since women and underrepresented minorities attend community colleges in high numbers, the community college pathway to four-year institutions is an important context for research. It is likely this trend will continue during lean economic times as community colleges are a less expensive option in comparison with other kinds of institutions. As such, researchers and STEM educators are calling for more research into understanding the transfer experience for female and underrepresented minority students.

This paper introduces the Graphite open-source distributed parallel multicore simulator infrastructure. Graphite is designed from the ground up for exploration of future multi-core processors containing dozens, hundreds, or even thousands of cores. It provides high performance for fast design space exploration and software development. Several techniques are used to achieve this including: direct execution, seamless multicore and multi-machine distribution, and lax synchronization. Graphite is capable of accelerating simulations by distributing them across multiple commodity Linux machines. When using multiple machines, it provides the illusion of a single process with a single, shared address space, allowing it to run off-the-shelf pthread applications with no source code modification. Our results demonstrate that Graphite can simulate target architectures containing over 1000 cores on ten 8-core servers. Performance scales well as more machines are added with near linear speedup in many cases. Simulation slowdown is as low as 41× versus native execution.

The maximal convexity ridge is not well suited for the anal- ysis of medial functions or, it can be argued, for the analysis of any func- tion that is created via convolution with a kernel based on the Gaussian. In its place one should use the maximal scale ridge, which takes scale’s distinguished role into account. We present the local geometric structure of the maximal scale ridge of smooth and Gaussian blurred functions, a result that complements recent work on scale selection. We also discuss the subdimensional maxima property as it relates to the maximal scale ridge, and we prove that a generalized maximal parameter ridge has the subdimensional maxima property as well.

This paper evaluates the Raw microprocessor. Raw addresses thechallenge of building a general-purpose architecture that performswell on a larger class of stream and embedded computing applicationsthan existing microprocessors, while still running existingILP-based sequential programs with reasonable performance in theface of increasing wire delays. Raw approaches this challenge byimplementing plenty of on-chip resources - including logic, wires,and pins - in a tiled arrangement, and exposing them through a newISA, so that the software can take advantage of these resources forparallel applications. Raw supports both ILP and streams by routingoperands between architecturally-exposed functional units overa point-to-point scalar operand network. This network offers lowlatency for scalar data transport. Raw manages the effect of wiredelays by exposing the interconnect and using software to orchestrateboth scalar and stream data transport.We have implemented a prototype Raw microprocessor in IBM's180 nm, 6-layer copper, CMOS 7SF standard-cell ASIC process. Wehave also implemented ILP and stream compilers. Our evaluationattempts to determine the extent to which Raw succeeds in meetingits goal of serving as a more versatile, general-purpose processor.Central to achieving this goal is Raw's ability to exploit all formsof parallelism, including ILP, DLP, TLP, and Stream parallelism.Specifically, we evaluate the performance of Raw on a diverse setof codes including traditional sequential programs, streaming applications,server workloads and bit-level embedded computation.Our experimental methodology makes use of a cycle-accurate simulatorvalidated against our real hardware. Compared to a 180 nmPentium-III, using commodity PC memory system components, Rawperforms within a factor of 2x for sequential applications with a verylow degree of ILP, about 2x to 9x better for higher levels of ILP, and10x-100x better when highly parallel applications are coded in astream language or optimized by hand. The paper also proposes anew versatility metric and uses it to discuss the generality of Raw.