11,298 results on '"Integrated circuits -- Intellectual property"'
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52. Patent Application Titled 'Semiconductor Packages With Multiple Types Of Solder Balls' Published Online (USPTO 20250006682)
53. Patent Application Titled 'Semiconductor Package' Published Online (USPTO 20250006625)
54. Patent Application Titled 'Semiconductor Package And Method For Identifying Integrated Circuit Layers In Stack' Published Online (USPTO 20250004045)
55. Patent Application Titled 'Electrostatic Discharge (Esd) Protection Circuit Including An Avalanche Semiconductor Controlled Rectifier (Scr) With Parallel Connected Static Trigger Control Circuit (Tcc)' Published Online (USPTO 20250006724)
56. 'Semiconductor Package With Retreating Metal Layers' in Patent Application Approval Process (USPTO 20250006607)
57. 'Semiconductor Device' in Patent Application Approval Process (USPTO 20250006604)
58. 'Double-Sided Integrated Circuit With Electrostatic Guard Ring' in Patent Application Approval Process (USPTO 20250006663)
59. Researchers Submit Patent Application, 'System, Method And Apparatus For Total Storage Encryption', for Approval (USPTO 20250007689)
60. Researchers Submit Patent Application, 'Method And System For Emulating Ic Design With Fpga, And Storage Medium', for Approval (USPTO 20250005240)
61. Researchers Submit Patent Application, 'Main Word Line Driver And Memory Apparatus Using The Same', for Approval (USPTO 20250006247)
62. Researchers Submit Patent Application, 'Machine-Readable Code In Integrated Circuit', for Approval (USPTO 20250006650)
63. Patent Issued for Systems and methods for exporting design data using near-optimal multi-threading scheme (USPTO 12182613)
64. Patent Issued for Signal processing in bridge chip in semiconductor storage device and memory system (USPTO 12182411)
65. Patent Issued for Processing system, related integrated circuit, device and method (USPTO 12184448)
66. Patent Issued for Multi-purpose IO pads/bumps on semiconductor chips to maximize chip-to-chip data connectivity (USPTO 12182051)
67. Patent Issued for Integrated circuit having test circuitry for memory sub-systems (USPTO 12181522)
68. Patent Issued for Interface circuit and information processing system for detecting a connection state based on a notification received through a hot plug detect line (USPTO 12184589)
69. Patent Issued for Display panel, integrated chip, and display apparatus (USPTO 12183238)
70. Patent Issued for Display driver integrated circuit and display driving method for generating clock pattern (USPTO 12183251)
71. Patent Issued for Application processors and electronic devices including the same (USPTO 12183388)
72. Patent Application Titled 'System And Method For Secure Cloud Fpga Deployment' Published Online (USPTO 20250007710)
73. Patent Application Titled 'Processing System, Integrated Circuit, Device, And Method For Data Transfer For Secure Processing' Published Online (USPTO 20250005204)
74. Patent Application Titled 'Configurable Mesh Network Node Aggregation For Mitigating Voltage Droop In An Integrated Circuit (Ic) Chip And Related Methods' Published Online (USPTO 20250004515)
75. Data from Taiyuan University of Technology Provide New Insights into Information and Data Encoding and Encryption (Novel 3d-pchcs Design and Application On Ophthalmic Medical Image Copyright Protection With Fpga Implementation)
76. 'Quantum Device' in Patent Application Approval Process (USPTO 20250005416)
77. 'Network On Chip (Noc) Memory Addressable Encryption And Authentication' in Patent Application Approval Process (USPTO 20250007724)
78. Researchers Submit Patent Application, 'Multichip Package With Protocol-Configurable Data Paths', for Approval (USPTO 20240427721)
79. Researchers Submit Patent Application, 'Integrated Circuit Device Including Peripheral Circuit And Cell Array Structures, And Electronic System Including Same', for Approval (USPTO 20240429187)
80. Researchers Submit Patent Application, 'Electrical Connection Apparatus', for Approval (USPTO 20240426903)
81. Patent Application Titled 'Optical Memory Module And Optical Computing System Including The Same' Published Online (USPTO 20240427715)
82. Patent Application Titled 'Integrated Circuit Device' Published Online (USPTO 20240429303)
83. 'Transformer-Based Distributed Multicore Oscillator And Integrated Circuit And Terminal Thereof' in Patent Application Approval Process (USPTO 20240429863)
84. Researchers Submit Patent Application, 'Adaptive Local Throttle Management Of Processing Circuits Based On Detected States In An Integrated Circuit (Ic) Chip', for Approval (USPTO 20240427367)
85. Patent Application Titled 'Throttle Control Circuits For Throttling Activity In Processing Segment Circuits In An Integrated Circuit (Ic) Chip And Related Methods' Published Online (USPTO 20240427368)
86. Patent Application Titled 'Hierarchical Power Estimation And Throttling In A Processor-Based System In An Integrated Circuit (Ic) Chip' Published Online (USPTO 20240427410)
87. Patent Application Titled 'Method Of Forming Photomask, Layout Pattern And System For Patterning Semiconductor Substrate By Using Photomask' Published Online (USPTO 20240427230)
88. Patent Application Titled 'Integrated Circuits (Ic) Chips Including Throttle Request Accumulate Circuits For Controlling Power Consumed In Processing Circuits And Related Methods' Published Online (USPTO 20240427397)
89. Patent Application Titled 'Broadcasting Power Limiting Management Responses In A Processor-Based System In An Integrated Circuit (Ic) Chip' Published Online (USPTO 20240428024)
90. 'Hierarchical Power Estimation And Throttling In A Processor-Based System In An Integrated Circuit (Ic) Chip' in Patent Application Approval Process (USPTO 20240427411)
91. 'Adaptive Local Throttle Management Of Processing Circuits Based On Detected States In An Integrated Circuit (Ic) Chip' in Patent Application Approval Process (USPTO 20240427369)
92. Researchers Submit Patent Application, '8-T Sram Bitcell For Fpga Programming', for Approval (USPTO 20240428848)
93. Patent Issued for Regression neural network for identifying threshold voltages to be used in reads of flash memory devices (USPTO 12175363)
94. Patent Issued for Processing of ethernet packets at a programmable integrated circuit (USPTO 12174782)
95. Patent Issued for Method for detecting reverse engineering on a processor using an instruction pointer and corresponding integrated circuit (USPTO 12174950)
96. Patent Issued for FPGA-based USB 3.0/3.1 control system (USPTO 12174779)
97. Patent Issued for Apparatus for on demand access and cache encoding of repair data (USPTO 12174698)
98. Patent Application Titled 'Receivers And Semiconductor Memory Devices Including The Same' Published Online (USPTO 20240430140)
99. Patent Application Titled 'Decision Feedback Equalization In Semiconductor Devices' Published Online (USPTO 20240428822)
100. 'Traffic Management And Control Method And Apparatus, And Device And Readable Storage Medium' in Patent Application Approval Process (USPTO 20240430210)
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