102 results on '"Integrated Circuit Design"'
Search Results
52. 2.4-GHz Highly Selective IoT Receiver Front End With Power Optimized LNTA, Frequency Divider, and Baseband Analog FIR Filter
- Author
-
Philip Quinlan, Bram Nauta, Bart J. Thijssen, Eric A.M. Klumperink, and Integrated Circuit Design
- Subjects
Noise measurement ,Computer science ,business.industry ,Electrical engineering ,Noise figure ,Frequency conversion ,Receivers ,Frequency divider ,CMOS ,baseband ,Operational transconductance amplifier ,Phase noise ,Baseband ,Adjacent channel ,Power demand ,Inductors ,Electrical and Electronic Engineering ,business ,Transconductance - Abstract
High selectivity becomes increasingly important with an increasing number of devices that compete in the congested 2.4-GHz industrial, scientific, and medical (ISM)-band. In addition, low power consumption is very important for Internet-of-Things (IoT) receivers. We propose a 2.4-GHz zero-intermediate frequency (IF) receiver front-end architecture that reduces power consumption by 2 $\times $ compared with state-of-the-art and improves selectivity by >20-dB without compromising on other receiver metrics. To achieve this, the entire receive chain is optimized. The low-noise transconductance amplifier (LNTA) is optimized to combine low noise with low power consumption. State-of-the-art sub-30-nm complementary metal–oxide–semiconductor (CMOS) processes have almost equal strength complementary field-effect transistors (FETs) that result in altered design tradeoffs. A Windmill 25%-duty cycle frequency divider architecture is proposed, which uses only a single NOR-gate buffer per phase to minimize power consumption and phase noise. The proposed divider requires half the power consumption and has 2 dB or more reduced phase noise when benchmarked against state-of-the-art designs. An analog finite impulse response (FIR) filter is implemented to provide very high receiver selectivity with ultralow power consumption. The receiver front end is fabricated in a 22-nm fully depleted silicon-on-insulator (FDSOI) technology and has an active area of 0.5 mm2. It consumes 370 $\mu \text{W}$ from a 700-mV supply voltage. This low power consumption is combined with a 5.5-dB noise figure. The receiver front end has −7.5-dBm input-referred third-order-intercept point (IIP3) and 1-dB gain compression for a −22-dBm blocker, both at maximum gain of 61 dB. From three channels offset onward, the adjacent channel rejection (ACR) is ≥63 dB for Bluetooth Low-Energy (BLE), BT5.0, and IEEE802.15.4.
- Published
- 2021
53. We can do better than Moore's law
- Author
-
Nauta, Bram, MESA+ Institute, Digital Society Institute, and Integrated Circuit Design
- Published
- 2021
54. Computers kunnen zelf de chips van hun opvolgers ontwerpen
- Author
-
Verhagen, Laurens, Nauta, Bram, MESA+ Institute, Digital Society Institute, and Integrated Circuit Design
- Abstract
Computers zijn in staat om de chips van hun opvolgers zelf vorm te geven. Decennialang werd het tekenen van de plattegrond van de chips door mensen gedaan, maar ook dit gebied moeten zij prijsgeven aan de automatisering.
- Published
- 2021
55. RFIC Plenary Speaker 1: Transceiver Roadmap for 2035 and Beyond
- Author
-
Bram Nauta, MESA+ Institute, Digital Society Institute, and Integrated Circuit Design
- Subjects
Digital electronics ,business.industry ,Computer science ,Bandwidth (signal processing) ,Electrical engineering ,law.invention ,Bluetooth ,CMOS ,Hardware_GENERAL ,law ,Hardware_INTEGRATEDCIRCUITS ,Wireless ,RFIC ,22/1 OA procedure ,Transceiver ,business ,Electronic circuit - Abstract
Summary form only given, as follows. The complete presentation was not made available for publication as part of the conference proceedings. During the past decades wireless communication has made an enormous growth. Triggered by a large R&D effort, the integration of transceivers in CMOS technology has made low-cost mass production possible. For many applications like Bluetooth, a single-chip CMOS transceiver can now do the job. On the other hand, for complex transceivers like in modern smartphones, still more discrete RF components such as filters, switches and diplexers are being added to protect the transceiver from strong interferers which are often produced by the device itself. To satisfy the future bandwidth hunger, the number of frequency bands will further increase, modulation schemes will become more complex, more antennas will be used and carrier aggregation will be the norm. To limit the number of discrete RF components, linearity of the transceivers is key. Since more computing power will be needed in future transceivers as well, newer CMOS technologies are also wanted. CMOS technology will scale in favor of fast-switching digital circuits, but not for classical analog functions, like amplifiers. For the next fifteen years re-thinking of basic circuits and systems will be needed to make highly integrated linear transceivers, in a technology that is designed for digital circuits.
- Published
- 2021
56. Uw auto, smartphone en spelcomputer zijn moeilijk leverbaar: de chips zijn op
- Author
-
Verhagen, Laurens, Nauta, Bram, MESA+ Institute, and Integrated Circuit Design
- Abstract
Chips zitten overal in. In koffieapparaten, tv’s, oortjes, webcams en uiteraard ook in mobieltjes, tablets en laptops. Normaal gesproken doen ze op de vierkante millimeter onverstoorbaar hun noodzakelijke werk. Ze kosten bijna niets en zijn onmisbaar geworden in het dagelijks leven. En nu zitten we in een wereldwijde chipcrisis. Hoe komt dat? Verstoord evenwicht Het korte antwoord: corona. ‘Jarenlang heeft de wereldwijde chipindustrie prima gefunctioneerd’, legt Bram Nauta, hoogleraar elektrotechniek aan de Universiteit Twente, uit. De industrie plaatste zijn bestellingen bij de grote chipfabrikanten en die zorgden ervoor dat hun fabrieken constant op volle toeren draaiden. Dit evenwicht is nu verstoord.
- Published
- 2021
57. A 0.7-5.7 GHz Reconfigurable MIMO Receiver Architecture for Analog Spatial Notch Filtering Using Orthogonal Beamforming
- Author
-
Eric A.M. Klumperink, Bram Nauta, Sajad Golabighezelahmad, and Integrated Circuit Design
- Subjects
Transimpedance amplifier ,Beamforming ,Computer science ,Local oscillator ,MIMO ,02 engineering and technology ,Software defined radio ,Interference (wave propagation) ,Noise figure ,Receiver ,Antenna array ,0202 electrical engineering, electronic engineering, information engineering ,Electronic engineering ,Multiple-input–multiple-output (MIMO) ,Electrical and Electronic Engineering ,Spatial filtering ,Interference rejection ,Spatial filter ,Amplifier ,020208 electrical & electronic engineering ,Bandwidth (signal processing) ,Vector modulator ,Software-defined radio ,Filter (signal processing) ,Analog beamforming ,Chip ,Modulation ,Baseband - Abstract
A highly reconfigurable direct-conversion software-defined multiple-input multiple-output (MIMO) receiver with four RF inputs and four I/Q baseband outputs is proposed. It allows for digital MIMO but also analog interference rejection by spatial notch filtering through four flexible and simultaneous orthogonal beams. A segmented constant-Gm vector modulator (VM) with improved interference tolerance and wide RF frequency range targeting the sub-6-GHz bands is proposed. It exploits current-domain beamforming before $I$ – $V$ conversion by transimpedance amplifiers. A 0.7–5.7-GHz 22-nm fully depleted silicon-on-insulator (FD-SOI) prototype chip achieves >29 dB spatial filtering for a single notch and an ultrawideband 20-dB notch suppression bandwidth of 2.3 GHz at broadside excitation at an local oscillator (LO) frequency of 2.5 GHz. In the notches, an IIP3 of +16 dBm and B1dB of −11.5 dBm at a 41-dB gain is achieved, improving IIP3 and B1dB by 35 and 27 dB, respectively, by spatial filtering. A single-element noise figure (NF) of 5.5–7 dB is achieved on the VM constellation corners, degrading about 2 dB on the points nearby the biggest circle fitting into a square constellation. However, sub-3-dB system NF is potentially achievable, taking into account up to 6-dB improvement by the four-element beamforming. Given both gain and phase control provided by the VM, spatial patterns with up to three independent nulls can be synthesized with the four-element antenna array. The chip of 0.52 mm2 active area consumes 77–139 mW at an LO-frequency of 0.7–5.7 GHz from a 0.8-V supply.
- Published
- 2021
58. Design Procedure for Integrated Microwave GaAs Stacked-FET High-Power Amplifiers
- Author
-
Peter de Hek, Frank E. van Vliet, Gijs van der Bent, and Integrated Circuit Design
- Subjects
Materials science ,Hardware_PERFORMANCEANDRELIABILITY ,02 engineering and technology ,Nonlinear circuits ,Capacitance ,law.invention ,law ,Radio frequency (RF) signals ,Hardware_INTEGRATEDCIRCUITS ,0202 electrical engineering, electronic engineering, information engineering ,Breakdown voltage ,Electrical and Electronic Engineering ,Power-integrated circuits ,Microwave-integrated circuits ,Radiation ,business.industry ,Amplifier ,Transistor ,020206 networking & telecommunications ,Condensed Matter Physics ,n/a OA procedure ,Transmitters ,Logic gate ,Optoelectronics ,Field-effect transistor ,Radio frequency ,business ,Hardware_LOGICDESIGN ,Voltage - Abstract
The application of stacked-FETs in power amplifiers allows for a supply voltage higher than supported by the breakdown voltage of a single transistor. Potential benefits of the increased supply voltage are reduced supply currents and a lower matching ratio at the output of the amplifier. Furthermore, an increased output power per chip area is obtained due to the reduction in passive structures resulting in more area-efficient power combining. In this paper, the procedure for the design of integrated microwave stacked-FET is discussed. Several options for the correct distribution of RF voltage and current swings are investigated and the relationship between the number of stacked transistors and bandwidth is addressed. The procedure is demonstrated by the design of an S-band GaAs stacked-FET containing three transistors. This stacked-FET is applied in an S-band HPA that has a PAE of more than 40% at an output power of 20 W, which is more than twice the output power of any previously reported GaAs stacked-FET HPA.
- Published
- 2019
59. Maximizing the Data Rate of an Inductively Coupled Chip-to-Chip Link by Resetting the Channel State Variables
- Author
-
Anoop Narayan Bhat, Madhulatha Bonu, Nagendra Krishnapura, Kumar Anurag Shrivastava, Subhashish Mukherjee, MESA+ Institute, and Integrated Circuit Design
- Subjects
Physics ,chip-to-chip link ,isolator ,Matched filter ,inductively coupled link ,state-variable reset ,020208 electrical & electronic engineering ,Matched filters ,time varying circuits ,02 engineering and technology ,Topology ,Chip ,Signal ,n/a OA procedure ,Channel capacity ,Signal-to-noise ratio ,Interference (communication) ,Hardware and Architecture ,0202 electrical engineering, electronic engineering, information engineering ,Bandwidth (computing) ,Electrical and Electronic Engineering ,Communication channel - Abstract
A technique is proposed for increasing the data rate transmitted through an inductively coupled chip-to-chip link by resetting the channel state variables. This allows the data rate to be increased well beyond what is implied by the channel bandwidth. In the proposed scheme, the two sides of the link are resonated at the highest possible quality factor, maximizing link gain, and minimizing interference. The transmit signal is a binary matched pulse which maximizes the received signal for a given transmitter voltage limit. High-efficiency switching transmitters can be used for this type of signal. The proposed technique can be applied to communication links in which channel state variables are accessible for reset. For increasing the data rate, it is shown that the proposed state-variable reset technique results in a higher signal-to-noise ratio of the received signal and a higher energy efficiency compared to reducing the quality factor to widen the bandwidth, using equalization, or using multi-level signaling. The technique is demonstrated on a chip-to-chip link with coupled 1.5 mm $\times1.5$ mm planar inductors separated by 0.5 mm in a 0.18 $\mathrm {\mu m}$ CMOS process. 500 Mb/s data rate is achieved over a link which has a band-pass bandwidth of 185 MHz.
- Published
- 2019
60. Design and analysis of a DCO-based phase-tracking RF receiver for IoT applications
- Author
-
Yao-Hong Liu, Christian Bachmann, Robert Bogdan Staszewski, Vijaya Kumar Purushothaman, MESA+ Institute, and Integrated Circuit Design
- Subjects
Frequency response ,Frequency-shift keying ,Computer science ,Carrier-frequency tracking (CFT) ,Circuit design ,Local oscillator ,020208 electrical & electronic engineering ,Bluetooth low-energy (BLE) receivers ,IEEE802154 receivers ,02 engineering and technology ,Phase-tracking receivers ,Chip ,Low-power transceivers ,n/a OA procedure ,Image response ,Phase-locked loop ,CMOS ,Modulation ,Phase-locked loop (PLL)-free receivers ,0202 electrical engineering, electronic engineering, information engineering ,Electronic engineering ,Digitally controlled oscillator ,Electrical and Electronic Engineering ,Low-voltage transceivers - Abstract
This paper presents an energy-/area-efficient digitally controlled oscillator (DCO)-based phase-tracking Receiver for Internet-of-Things (IoT) applications. The RX leverages the constant-envelope nature of frequency shift keying modulation adopted in many IoT protocols, e.g., IEEE802.15.4 and Bluetooth low energy (BLE), to enhance the energy efficiency and to reduce the chip area. The proposed RX, with the DCO acting as a local oscillator (LO) and binary frequency feedback, promotes low-power and low-voltage circuit design, while a data-aided carrier-frequency tracking ensures the received carrier stability without a power-/area-hungry phase-locked loop (PLL). The RX avoids a compromise between a power-hungry I/Q LO generation and the image rejection in traditional RXs. An equivalent mathematical model is further presented, which helps to analyze and optimize the frequency response of the proposed RX. Fabricated in 40-nm CMOS, the RX consumes 1.55 mW from a 0.85-V supply and has a −87-dBm sensitivity at 2 Mb/s, which leads to a 0.77-nJ/b energy efficiency and 178-dB RX sensitivity FoM.
- Published
- 2019
61. IoT receiver techniques
- Author
-
Bart J. Thijssen, Nauta, Bram, Klumperink, Eric A.M., and Integrated Circuit Design
- Subjects
business.industry ,Computer science ,Power consumption ,Phase noise ,Electronic engineering ,Internet of Things ,business - Abstract
The wireless receiver has a significant impact on the connectivity performance and battery lifetime of Internet-of-Things (IoT) devices. High selectivity becomes increasingly important with an increasing number of devices that compete in the congested 2.4GHz industrial, scientific and medical (ISM) band. In addition, low power consumption is very important for IoT receivers as the burden of changing batteries increases proportionally with the number of the devices. Complementary metal-oxide-semiconductor (CMOS) technology allows for highly integrated IoT devices with small form factor, low digital processing power consumption and low costs. The dissertation presents circuit innovations for a CMOS wireless IoT receiver, that allow to improve the performance of an IoT receiver while reducing its power consumption. An analog FIR filter is proposed that allows for a >20dB increased selectivity. Furthermore, the analog FIR techniques proposed in the dissertation have many other potential applications. The proposed Windmill divider architecture halves the power consumption while reducing the phase noise. The feedforward phase noise cancellation architecture reduces the PLL rms jitter by 7.2dB without significantly increasing its power consumption. These innovations help to pave the way to an all connected world – not just connecting everyone, but connecting everything.
- Published
- 2021
62. Crystal oscillator circuit and method of operation
- Author
-
van der Zee, Ronan A.R., Lechevallier, Joeri Boris, Integrated Circuit Design, and MESA+ Institute
- Subjects
Condensed Matter::Superconductivity ,Physics::Optics - Abstract
A crystal oscillator circuit (100, 200) is described that includes a crystal resonator (220); and a voltage source (204) configured to apply a voltage step across the crystal oscillator (220) where a polarity of the voltage source (204) applied to the crystal resonator (220) is switched in response to a sign of a current passing through the crystal resonator (220) and in response thereto a self-timed energy injection waveform is provided to the crystal resonator (220).
- Published
- 2021
63. Systems and methods for analog finite impulse response filters
- Author
-
Thijssen, Bart J., Klumperink, Eric A.M., Nauta, Bram, Quinlan, Philip, MESA+ Institute, Integrated Circuit Design, and Mesa+
- Subjects
Hardware_INTEGRATEDCIRCUITS ,Hardware_PERFORMANCEANDRELIABILITY ,Hardware_ARITHMETICANDLOGICSTRUCTURES - Abstract
Systems and methods for analog finite impulse response (FIR) filters are provided. In certain embodiments, a receiver includes a cascade of a mixer, an analog FIR filter, and an analog-to-digital converter (ADC). By including the analog FIR filter along the signal path between the mixer and the ADC, design constraints of the ADC are relaxed. For example, the ADC can operate with relaxed specifications with respect to resolution and/or dynamic range when the analog FIR filter is included. The analog FIR filter can include a controllable transconductance circuit that delivers an integration current to a capacitor over an integration period, with the analog FIR filter's coefficients used to change the transconductance setting of the controllable transconductance circuit to different values over the integration period.
- Published
- 2021
64. EVM-based performance evaluation of Co-channel interference mitigation using spatial filtering for digital MIMO-receivers
- Author
-
Eric A.M. Klumperink, Sajad Golabighezelahmad, Bram Nauta, MESA+ Institute, and Integrated Circuit Design
- Subjects
Beamforming ,Computer science ,MIMO ,02 engineering and technology ,Data_CODINGANDINFORMATIONTHEORY ,Interference (wave propagation) ,law.invention ,Interference (communication) ,law ,Error Vector Magnitude ,0202 electrical engineering, electronic engineering, information engineering ,Electronic engineering ,digital demodulation ,Dipole antenna ,interference rejection ,Over-the-Air Measurement ,Spatial filtering ,Spatial filter ,020208 electrical & electronic engineering ,Co-channel interference ,020206 networking & telecommunications ,Constellation diagram ,Chip ,Constellation Diagram ,QAM - Abstract
—Digital Multiple-Input Multiple-Output (MIMO) receivers, exposed to strong co-channel interference, require high dynamic range Analog-to-Digital Converters (ADCs) and a highly linear RF front-end. Hybrid analog-digital beamforming can mitigate this co-channel interference by spatial filtering before the ADC and improve interference robustness. This paper demonstrates and characterizes this mitigation effect in detail utilizing Error Vector Magnitude (EVM) as a criterion. A 4-element 22 nm FD-SOI CMOS prototype MIMO Receiver chip is characterized with a linear 4-element dipole antenna array with half-wavelength spacing in the 2.4 GHz ISM-band. EVM measurements demonstrate the effectiveness of spatial filtering for co-channel interference mitigation and dynamic range extension. The receiver is exposed to interference while using different QAM formats (16-QAM to 256-QAM). It is demonstrated how interference reduces the acceptable-EVM input power range, while hybrid beamforming extends this range. This is done by extensive conductive measurements for reliable results, while also demonstrating an Over-the-Air (OTA) result
- Published
- 2020
65. Reverse Intermodulation in Multi-Tone Array Transmitters
- Author
-
Anton N. Atanasov, Mark S. Oude Alink, Frank E. van Vliet, MESA+ Institute, and Integrated Circuit Design
- Subjects
Power amplifiers ,Computer science ,Amplifier ,Interleaved arrays ,Transmitter ,Linearity ,Predistortion ,Reverse intermodulation ,Power (physics) ,law.invention ,law ,Electronic engineering ,Radar ,Intermodulation ,Nonlinearity ,Electrical efficiency - Abstract
The modern spectral, and thereby linearity, requirements force 5G phased-array transmitter systems to operate at reduced power efficiency, as they can no longer use voluminous filtering. To reduce the linearity requirements of the transmitter, we consider the case of an array consisting of closely spaced radiating elements operating at different frequencies. The coupled tones from one element to another create reverse intermodulation distortion (RIMD). We explain how RIMD is created within a power amplifier (PA), and derive an estimate for the power of the RIMD components. We provide a set of measurements for an X-Band GaAs PA and draw a direct comparison between RIMD and IMD. We show that RIMD has a third-order behaviour up to very high reverse power levels, opening up the perspective for higher output power operation as well as simpler and lower-power predistortion in multi-tone array systems such as 5G and radar.
- Published
- 2020
66. Analysis of a 1kbps Backscatter Receiver with up to -80dBm Tag-to-tag Receive Sensitivity
- Author
-
R. A. R. van der Zee, R. J. de Jong, Andre B.J. Kokkeler, Radio Systems, and Integrated Circuit Design
- Subjects
Radio Transceivers ,Backscatter ,Computer science ,Acoustics ,010401 analytical chemistry ,Detector ,22/2 OA procedure ,020206 networking & telecommunications ,Semi-passive RFID tags ,02 engineering and technology ,Noise figure ,01 natural sciences ,Signal ,Wireless sensor networks ,0104 chemical sciences ,Link budget ,Phase noise ,0202 electrical engineering, electronic engineering, information engineering ,Exciter ,Tag-to-tag ,Sensitivity (electronics) - Abstract
Merging developments in RFID and wireless sensor networks have increased the interest in using backscatter radio for tag-to-tag communication. Low power consumption is a major concern, often limiting the choice to incoherent receivers such as diode envelope detectors. Link budget calculations require receiver sensitivity specifications, however accurate characterizations are scarce. In this work, we show that the receiver sensitivity is strongly related to the exciter incident power. Full-range analysis of a zero-bias diode detector shows a decreasing noise factor at higher incident powers, which leads to improved sensitivity. On the other side, at strong incident powers, the phase noise of the exciter interferes with the received signal, setting an lower bound to the sensitivity of the backscatter receiver. This work proposes a semi-passive RFID tag capable of 1kbps to 10kbps data rates in the 434MHz band using off the shelf components. The tag has a low power consumption of 85μW during receive, 45μW during transmit and less than 4μW in sleep. The receiver sensitivity at 1kbps shows a 25dB variation as a function of exciter incident power between -50 to 10dBm, while a peak sensitivity of around -80dBm is measured at an incident power of -25dBm.
- Published
- 2020
67. Wat kan China zonder chips?: Wie geavanceerde chips kan maken heeft de wereldmacht in handen
- Author
-
Verhagen, Laurens, van Bemmel, Noël, Nauta, Bram, MESA+ Institute, and Integrated Circuit Design
- Abstract
China maakt zeer geavanceerde technologie, maar niet de microchips waarop die draait. Dus hoe moet dat nu Chinese techbedrijven in de VS op een zwarte lijst staan? De strijd tussen wereldmachten in de technologie.
- Published
- 2020
68. Preserving Polar Modulated Class-E Power Amplifier Linearity under Load Mismatch
- Author
-
Anne-Johan Annema, Maikel Huiskamp, Awani Khodkumbhe, Ali Ghahremani, Bram Nauta, and Integrated Circuit Design
- Subjects
Computer science ,Power amplifiers ,Amplifier ,Adjacent channel power ratio ,Linearity ,Adaptive control ,Impedance ,020206 networking & telecommunications ,Distortion ,02 engineering and technology ,CMOS integrated circuits ,Predistortion ,QAM ,Modulation ,0202 electrical engineering, electronic engineering, information engineering ,Electronic engineering ,Antennas ,Quadrature amplitude modulation ,Symbol rate - Abstract
Power amplifiers (PAs) need digital predistortion (DPD) linearization to handle high-order complex modulation schemes in next-generation communication systems. While load variation is inevitable, DPD is generally designed considering only the nominal load impedance for PAs. This paper presents a polar class-E PA with an on-chip waveform characterizer enabling adaptive digital predistortion (ADPD) to preserve the linearity of the PA under load mismatch. The presented ADPD corrects both AM/AM and AM/PM distortions, which are prominent in the demonstrated PA, while simultaneously correcting for slow memory effects without the need for complex memory DPD algorithms. Load-pull measurements demonstrate that target error vector magnitude (EVM) and adjacent channel power ratio (ACPR) can be maintained in a significantly larger area on the Smith chart going from 50 Ω optimized static DPD to our ADPD for a 2 GHz 1024 QAM signal with 1 MSym/s symbol rate.
- Published
- 2020
69. Analysis of short-circuit transients in the LHC main dipole circuit
- Author
-
Anne-Johan Annema, Jurriaan Schmitz, Cora Salm, M. Prioli, Arjan Verweij, Z. Charifoulline, Lorenzo Bortot, A. Liakopoulou, Michal Maciejewski, Emmanuele Ravaioli, Integrated Circuit Design, and Integrated Devices and Systems
- Subjects
Physics ,History ,Large Hadron Collider ,Ground ,Time constant ,Mechanics ,Accelerators and Storage Rings ,Computer Science Applications ,Education ,Power (physics) ,Dipole ,Fuse (electrical) ,Short circuit ,Voltage - Abstract
After the occurrence and detection of a short circuit to ground in the LHC main dipole circuit, a fast power abort is triggered and the current in the circuit starts decaying semi-exponentially from a maximum value of 11.85 kA to zero, with a time constant of 103 s. If a short to ground occurs, the current flows through the fuse that is present in the grounding subcircuit. Depending on the value of the thermal load, the fuse first enters a pre-arcing region where it starts intermittently blowing up, until the blow-up threshold is reached, after which it definitively blows up. A simulation scheme utilising a common interface between PSpice and Matlab is proposed in order to simulate the blow-up behaviour of the fuse and hence increase the accuracy of the circuit model for short circuits to ground. A parametric analysis of the short circuit to ground parameters is performed and a better understanding of the behaviour of the circuit under different conditions is obtained. The worst-case values of the voltage to ground in the LHC main dipole circuit are identified for both the case where the intermittent behaviour of the fuse is included in the model as well as for the case where the fuse is not modelled and a comparison between the two is given.
- Published
- 2020
70. A Linear Array of Skewed Dipoles with Asymmetric Radiation Pattern for Angular Filtering
- Author
-
C. Yepes, Stefania Monni, Erio Gandini, Andrea Neto, Frank E. van Vliet, Daniele Cavallo, and Integrated Circuit Design
- Subjects
Scanning angles ,Physics::Optics ,Pattern asymmetry ,02 engineering and technology ,Stopband ,Grating ,Dipole antennas ,law.invention ,Radiation pattern ,Optics ,law ,Angular filtering ,0202 electrical engineering, electronic engineering, information engineering ,Dipole antenna ,Front to back ratio ,Antenna arrays ,Electrical and Electronic Engineering ,Tilted dipole array ,Physics ,business.industry ,020206 networking & telecommunications ,Artificial dielectric ,n/a OA procedure ,Wavelength ,Dipole ,Front-to-back ratio ,Asymmetric radiation ,Dipole arrays ,business ,Artificial dielectrics ,Measured results - Abstract
In this letter, we present a design of a linear array of tilted dipoles to achieve radiation patterns with asymmetric angular filtering characteristics. To realize the asymmetric radiation, the dipole elements are spaced by a distance larger than half a wavelength, thus allowing for grating lobes to occur in the visible region. Moreover, the dipoles are loaded with artificial dielectrics to increase the front-to-back ratio and consequently to enable higher gain in certain desired angular regions. Based on the design, a linear array with ten elements is manufactured and tested. The measured results show the ability of such an array to achieve stable gain from broadside up to 90° scanning while implementing a stopband angular filter for negative scanning angles. © 2002-2011 IEEE.
- Published
- 2020
71. 30.4 A 370µW 5.5dB-NF BLE/BT5.0/IEEE 802.15.4-Compliant Receiver with >63dB Adjacent Channel Rejection at >2 Channels Offset in 22nm FDSOI
- Author
-
Philip Quinlan, Bram Nauta, Bart J. Thijssen, Eric A.M. Klumperink, and Integrated Circuit Design
- Subjects
Noise measurement ,Sinc function ,Computer science ,020208 electrical & electronic engineering ,020206 networking & telecommunications ,Logic gates ,02 engineering and technology ,Filter (signal processing) ,Noise figure ,Interference (wave propagation) ,Receivers ,Mixers ,Finite impulse response filters ,Logic gate ,0202 electrical engineering, electronic engineering, information engineering ,Adjacent channel ,Electronic engineering ,IEEE 802.15 Standard ,Power demand ,IEEE 802.15 ,Communication channel - Abstract
Upcoming Internet-of-Things (IoT) applications require low-power multi-standard RF receiver (RX) front-ends. Interference rejection becomes increasingly important as ever more devices compete in the scarce 10w-GHz spectrum. Typically, low-power RXs do not possess very steep filtering [1]–[6]. On the other hand, very selective RXs - e.g. using analog FIR or Filtering-by-Aliasing [7] - have very high power consumption, not suitable for IoT applications. A recent Analog Finite-Impulse-Response (AFIR) filter [8] shows promising results to improve channel filtering. [8] uses a much lower FIR update rate than [7] to considerably reduce power consumption. This comes at the cost of a filter alias, but the inherent windowed integration sinc filtering mitigates this filter alias. Achieving low RX Noise Figure (NF), while improving selectivity is challenging at ultra-low power, where all blocks tend to contribute significantly to the total power consumption [1]–[6].
- Published
- 2020
72. Inductor arrangement
- Author
-
Dekker, Thomas, Oude Alink, Mark Stefan, and Integrated Circuit Design
- Abstract
An inductor arrangement has a first inductor structure having one or more inductors at least partially on a first layer and a second inductor structure having one or more inductors at least partially on a second layer. The inductors are arranged such that currents induced by an external magnetic field are substantially cancelled in at least one of the first inductor structure and the second inductor structure. The, or each, inductor of the second inductor structure overlaps, at least partially, the, or each, inductor of the first inductor structure. An oscillator circuit having an inductor arrangement is also presented.
- Published
- 2020
73. Analysis of Tilted Dipole Arrays: Impedance and Radiation Properties
- Author
-
Frank E. van Vliet, Stefania Monni, Erio Gandini, Andrea Neto, C. Yepes, Daniele Cavallo, and Integrated Circuit Design
- Subjects
Physics ,business.industry ,pattern shaping ,020206 networking & telecommunications ,Reflector (antenna) ,02 engineering and technology ,Radiation ,Method of moments (statistics) ,method of moments (MoM) ,Radiation properties ,n/a OA procedure ,Dipole ,symbols.namesake ,Optics ,Fourier transform ,Floquet analysis ,0202 electrical engineering, electronic engineering, information engineering ,symbols ,Antenna arrays ,Electrical and Electronic Engineering ,business ,Electrical impedance ,Ground plane - Abstract
In this article, we investigate the radiation and impedance properties of arrays of tilted dipoles. A spectral periodic method of moments (MoM) is developed for the analysis of infinite arrays with arbitrarily tilted dipole elements, in free space or with a backing reflector. With the aid of this analysis method, the radiation characteristics of arrays of stacked dipoles over a ground plane are studied, explaining the variation of the patterns as a function of the interelement distance and the angle of inclination of the elements. Finite linear arrays of tilted dipoles are also investigated, to assess the dependence of the array characteristics on the number of elements. The developed method can be used to design arrays with nonsymmetric radiation patterns for angular filtering or pattern shaping.
- Published
- 2020
74. Angularly Stable Frequency Selective Surface Combined With a Wide-Scan Phased Array
- Author
-
Daniele Cavallo, Stefania Monni, C. Yepes, Frank E. van Vliet, Erio Gandini, Andrea Neto, and Integrated Circuit Design
- Subjects
Materials science ,Phased array ,Frequency selective surface (FSS) ,02 engineering and technology ,Harmonic analysis ,Optics ,Transmission line ,spatial filters ,0202 electrical engineering, electronic engineering, information engineering ,Electrical and Electronic Engineering ,Spatial filters ,business.industry ,Bandwidth (signal processing) ,020206 networking & telecommunications ,Conical surface ,Physics::Classical Physics ,021001 nanoscience & nanotechnology ,n/a OA procedure ,Antenna efficiency ,Surface wave ,phased array antennas ,Equivalent circuit ,Antennas ,0210 nano-technology ,business - Abstract
A five-layer frequency selective surface (FSS) composed of subwavelength elements with large harmonic rejection bandwidth is presented. The FSS design is based on an equivalent circuit model, where the interlayer interaction is only described with a single transmission line representing the fundamental Floquet wave. A prototype of the designed FSS is fabricated, and the measured response exhibits good stability over a wide conical incidence range up to 45°. The FSS is combined with a wide-scanning connected array of dipoles to implement a phased array with integrated filtering properties. A dispersion analysis is performed to define the distance between the array and the FSS that avoids the propagation of surface waves between the combined structures, allowing to maximize the radiation efficiency. The performance of the array combined with the FSS is experimentally characterized, showing high-order harmonic rejection better than 17 dB over a large bandwidth.
- Published
- 2018
75. Optical Power Efficiency Versus Breakdown Voltage of Avalanche-Mode Silicon LEDs in CMOS
- Author
-
Gerard J. M. Wienk, Anne-Johan Annema, Satadal Dutta, Raymond J. E. Hueting, Jurriaan Schmitz, and Integrated Circuit Design
- Subjects
Silicon ,chemistry.chemical_element ,02 engineering and technology ,Electroluminescence ,01 natural sciences ,law.invention ,020210 optoelectronics & photonics ,law ,Electric field ,0103 physical sciences ,0202 electrical engineering, electronic engineering, information engineering ,Breakdown voltage ,Power efficiency ,Electrical and Electronic Engineering ,Diode ,010302 applied physics ,Physics ,Internal quantum efficiency (IQE) ,business.industry ,LED ,Avalanche breakdown ,Electronic, Optical and Magnetic Materials ,CMOS ,chemistry ,2023 OA procedure ,Optoelectronics ,Atomic physics ,business ,Light-emitting diode - Abstract
We report on the dependency of the optical power efficiency $\eta $ on the breakdown voltage ${V}_{\text {BR}}$ of avalanche-mode (AM) light-emitting diodes (LEDs) in silicon. Lateral p+-n-n+ LEDs have been designed in a 65-nm bulk CMOS technology, where ${V}_{\text {BR}}$ is varied between 2 and 9 V. This tunes both the magnitude and the spatial distribution of the reverse electric field, which governs AM electroluminescence. Experiments show that a maximum $\eta $ of $\sim 1.7 \times 10^{-6}$ is obtained for ${V}_{\text {BR}} \sim 6$ V. For ${V}_{\text {BR}} V, non-local avalanche results in a lower $\eta $ , while for ${V}_{\text {BR}} > 6$ V, a gradual reduction in $\eta $ with increasing ${V}_{\text {BR}}$ is obtained. This trend is compared with two recently proposed opto-electronic models. A maximum in $\eta $ at relatively low voltages is attractive for monolithic opto-electronic integration in silicon
- Published
- 2017
76. Densely Interleaved Arrays for Dual-Tone Transmitters
- Author
-
Mark S. Oude Alink, Frank E. van Vliet, Anton N. Atanasov, and Integrated Circuit Design
- Subjects
Physics ,Acoustics ,Interleaved arrays ,Antenna aperture ,RF power amplifier ,Planar array ,ComputingMethodologies_IMAGEPROCESSINGANDCOMPUTERVISION ,Data_CODINGANDINFORMATIONTHEORY ,law.invention ,Antenna array ,law ,Distortion ,Phased arrays ,Mutual coupling ,Dipole antenna ,Antenna (radio) ,Intermodulation ,Nonlinearity ,Computer Science::Information Theory - Abstract
Power amplifier nonlinearity introduces intermodulation distortion when transmitting dual-tone signals from an antenna array. To reduce distortion levels and increase output power for dual-tone systems we propose to densely interleave two antenna arrays without increasing the antenna aperture. Each array is excited with a different tone, resulting in a single-tone input for the power amplifiers, thereby reducing intermodulation distortion. In order to compare the performance of the densely interleaved array with a regular, planar array, when excited by two-tone signals, a procedure for evaluating the S-parameters matrix of an interleaved dipole array is presented. Simulations with a realistic RF power amplifier model show 13 to 31 dB intermodulation reduction for the same output power and total antenna aperture.
- Published
- 2019
77. De Wet van Moore: Computer Chip op sterven na dood?
- Author
-
Keulen, Jean-Paul, Nauta, Bram, MESA+ Institute, and Integrated Circuit Design
- Subjects
22/4 OA procedure - Abstract
Meer dan veertig jaar geleden voorspelde Gordon Moore dat het aantal componenten op computerchips elke twee jaar zou verdubbelen. Tot nu toe weet de computerindustrie daar aardig aan te voldoen. Maar volgens veel deskundigen is het eind van deze razendsnelle vooruitgang in zicht. Hebben de doemdenkers gelijk?
- Published
- 2019
78. Inverter-Based Subthreshold Amplifier Techniques and Their Application in 0.3-V ΔΣ -Modulators
- Author
-
Lishan Lv, Zhiliang Qiao, Xiong Zhou, Qiang Li, and Integrated Circuit Design
- Subjects
Physics ,Spurious-free dynamic range ,Subthreshold conduction ,Transconductance ,Amplifier ,020208 electrical & electronic engineering ,Frequency compensation ,02 engineering and technology ,Delta-sigma modulation ,Topology ,n/a OA procedure ,Amplifiers ,delta-sigma modulators ,subthreshold ,inverter-based ,CMOS ,Operational transconductance amplifier ,feedforward ,0202 electrical engineering, electronic engineering, information engineering ,OTA ,Electrical and Electronic Engineering ,ultralow voltage ,frequency compensation - Abstract
Subthreshold amplifiers suffer from the limited voltage headroom which leaves little space for conventional analog techniques to enhance performance and efficiency. This paper presents an evolution process of implementing conventional structures with inverters, allowing ultralow-voltage operation with increased flexibility in adopting traditional circuit techniques. Based on the proposed inverter-based elementary structure and CMFB, both the Miller-compensated (MC) operational transconductance amplifier (OTA) and the feedforward-compensated (FFC) OTA achieve significantly improved performance as compared to previous works. The proposed amplifier techniques are verified in $\Delta \Sigma $ modulator (DSM) design, with MC-OTA for a DT-DSM and FFC-OTA for a CT-DSM, both fabricated in a 0.13- $\mu \text{m}$ CMOS. The 0.3-V DT-DSM achieves 74.1-dB SNDR, 83.4-dB SFDR and 20-kHz bandwidth with 79.3- $\mu \text{W}$ power, resulting in a Schreier figure of merit (FoM) of 158 dB. The 0.3-V CT-DSM achieves 68.5-dB SNDR, 82.6-dB SFDR, and 50-kHz bandwidth with 26.3- $\mu \text{W}$ power, leading to a Schreier FoM of 161 dB. Both DSMs exhibit highly competitive performance among sub-0.5-V designs, validating the proposed subthreshold amplifier techniques.
- Published
- 2019
79. The influence of energy recovery on the overall efficiency of acoustic sources at low frequencies
- Author
-
A. de Boer, Arthur P. Berkhoff, R.A.R. van der Zee, Farnaz Tajdari, Applied Mechanics, and Integrated Circuit Design
- Subjects
Materials science ,Acoustics and Ultrasonics ,Mechanical Engineering ,Acoustics ,Amplifier ,22/2 OA procedure ,Piezoelectric stack actuator ,Voice coil ,Condensed Matter Physics ,Lead zirconate titanate ,Piezoelectricity ,Power (physics) ,Energy recovery ,chemistry.chemical_compound ,chemistry ,Overall efficiency ,Mechanics of Materials ,Class-D amplifier ,Class D amplifier ,Flat acoustic source ,OE ,Electric power ,Actuator - Abstract
This paper defines a criterion called the overall efficiency (OE) for evaluating the efficiency of acoustic sources. In practice, the conventional efficiency (CE), is not capable of giving a comprehensive overview of the power consumption, especially in the connected amplifier drivers. The reason for this is that the CE is defined based on the nominal input electrical power. The nominal input electrical power is defined as the real part of the power that is delivered by the electrical amplifier to the actuation unit of an acoustic source. Therefore, power loss in the amplifier unit is not included in the CE definition. With the aid of the OE criterion, the effect of power loss in the connected amplifier units is taken into account. In particular, the application of the OE is crucial for acoustic sources that operate in a low frequency range. This is due to the reactive nature of power in both actuators and connected amplifiers. In the current paper, various combinations of amplifiers and actuators are studied. In particular, voice coil actuators and piezoelectric stack elements including both Lead Zirconate Titanate (PZT) ceramics and single crystal Lead Zirconate Niobate-Lead Titanate (PZN-PT) piezoelectric materials are investigated. In addition, the effect of a connected power driver is investigated. A class AB and a class D amplifier are studied respectively as analogue and switching amplifiers. Unlike a class AB amplifier, a class D amplifier is capable of energy recovery. A perforated flat acoustic source is examined in this paper as a practical example to verify the OE criterion. The numerical simulation on a thin acoustic source shows that for a single actuator, thanks to energy recovery, the OE is higher in a class D amplifier than that in a class AB amplifier. This study reveals that if a class D amplifier is the driver, using piezoelectric actuators results in a higher OE compared to using a voice coil actuator. Measurements on the sample acoustic source verify the numerical results presented in the current study.
- Published
- 2020
80. A 0.013-mm2 0.53-mW/Gb/s 32-Gb/s hybrid analog equalizer under 21-dB channel loss in 65-nm CMOS
- Author
-
Yong Chen, Chirn Chye Boon, Arya Balachandran, School of Electrical and Electronic Engineering, and Integrated Circuit Design Centre of Excellence
- Subjects
Physics ,020208 electrical & electronic engineering ,Equalization (audio) ,02 engineering and technology ,020202 computer hardware & architecture ,CMOS Equalizer ,CMOS ,Hardware and Architecture ,Gigabit ,Unit interval (data transmission) ,0202 electrical engineering, electronic engineering, information engineering ,Electronic engineering ,Electrical and electronic engineering [Engineering] ,Channel Loss ,Electrical and Electronic Engineering ,Electrical efficiency ,Software ,Communication channel ,Voltage ,Jitter - Abstract
Low-power and low-jitter equalization techniques become increasingly crucial for the wire-line receivers operating at data rates more than tens of gigabits per second. This brief reports an inductorless and power-efficient 32-Gb/s hybrid analog equalizer. The hybrid analog equalizer utilizes a triple-gate control to achieve equalization over a range of channel loss resulting in an inductorless and area-efficient design. The triple-gate controls entail that a low-frequency equalization is achieved in addition to the intermediate and high-frequency equalization, at minimum area overhead. The prototype is realized in a 65-nm CMOS, occupying a compact active area of 0.013 mm2. The maximum equalization achieved is 21 dB at Nyquist with a measured peak-to-peak data jitter of 5.25 ps (0.17 unit interval) at 32 Gb/s for a 231 - 1 pseudorandom bit sequence signal. The measurement shows a vertical eye-opening recovery rate of up to 61% at 32 Gb/s, for a channel loss of 21 dB. The prototype exhibits a competitive power efficiency of 0.53 mW/Gb/s under a supply voltage of 1.2 V. MOE (Min. of Education, S’pore)
- Published
- 2017
81. Architectures for RF Frequency synthesizers
- Author
-
Vaucher, Cicero S., Nauta, Bram, and Integrated Circuit Design
- Abstract
Frequency synthesizers are an essential building block of RF communication products. They can be found in traditional consumer products, in personal communication systems, and in optical communication equipment. Since frequency synthesizers are used in many different applications, different performance aspects may need to be considered in each case. The main body of the text describes a conceptual framework for analyzing the performance of PLL frequency synthesizers, and presents optimization procedures for the different performance aspects. The analysis of the PLL properties is performed with the use of the open-loop bandwidth and phase margin concepts, to enable the influence of higher-order poles to be taken into account from the beginning of the design process. The theoretical system analysis is complemented by descriptions of innovative system and building block architectures, by circuit implementations in bipolar and CMOS technologies, and by measurement results. Architectures for RF Frequency Synthesizers contains basic information for the beginner as well as in-depth knowledge for the experienced designer. It is widely illustrated with practical design examples used in industrial products. Written for: Electrical and electronic engineers
- Published
- 2002
82. An Electrically Programmable Split-Electrode Charge-Coupled Transversal Filter (EPSEF)
- Author
-
M.J.M. Pelgrom, H. Wallinga, and Integrated Circuit Design
- Subjects
Engineering ,Voltage-controlled filter ,IR-56124 ,business.industry ,Low-pass filter ,Electronic filter topology ,Adaptive filter ,Filter design ,Filter (video) ,Electronic engineering ,Electrical and Electronic Engineering ,business ,Active filter ,Digital filter - Abstract
A CCD split-electrode transversal filter (EPSEF) with analog controlled tap weights is described. The programmable tap weighting utilizes a novel analog multiplier for sampled data, based on charge profiling underneath a resistive gate structure. The EPSEF device concept and the performance data of a prototype filter with eight programmable taps are presented. Applications of the EPSEF in several programmed filter functions and in an adaptive filter system are demonstrated.
- Published
- 1980
83. Plantenna: towards a network of vegetation-integrated sensors for plant and environmental monitoring
- Author
-
Ten Veldhuis, M. C., Remko Uijlenhoet, Jurriaan Schmitz, Bart Smolders, Bram Nauta, Peter Baltus, Kofi Makinwa, Peter Steeneken, Integrated Devices and Systems, and Integrated Circuit Design
84. Frequency reference generator
- Author
-
Alexander Sebastian Delke, Mark Oude Alink, Anne-Johan Annema, Yanyu Jin, Jos Verlinde, Bram Nauta, MESA+ Institute, and Integrated Circuit Design
- Abstract
A frequency reference generator includes ( i ) an integrated frequency source having drive circuitry that drives a reso nant ( e.g. , non - trimmable LC ) tank to generate an oscillator signal , ( ii ) at least one temperature sensor that generates at least one measured temperature signal , and ( iii ) a frequency adjustment circuit that adjusts the oscillator signal frequency to generate the frequency reference based on the measured temperature signal and a ( e.g. , sample - specific ) mapping from temperature to a corresponding frequency - adjustment parameter ( e.g. , a divisor value for a fractional frequency divider ) . In some embodiments , a Colpitts oscillator gener ates the oscillator signal based on the measured temperature signal , where the Colpitts oscillator has voltage / tempera ture - compensation circuitry that compensates for variations in power supply voltage and operating temperature . Such frequency reference generators achieve substantial PVT insensitivity with as little as a single 1T - trim or even no trim at all .
85. Review of RF Device Behavior Model: Measurement Techniques, Applications, and Challenges.
- Author
-
Li H, Su J, Wang R, Liu Z, and Xu M
- Abstract
This review presents a concise overview of RF (radio frequency) power transistor behavior models, which is crucial for optimizing RF performance in high-frequency applications like wireless communication, radar, and satellites. The paper highlights the significance of accurate modeling in understanding transistor behavior and traces the evolution of behavior modeling techniques. Different behavior modeling strategies, such as LUT (look-up table) based models, polynomial equation-based models, and machine learning based models, are discussed along with their unique characteristics and modeling challenges. The review explores the difference between behavior models and the conventional empirical or physics-based modeling approaches, addressing the challenges of the accurate characterization of transistors at high frequencies and power levels. This paper concludes with an outlook of emerging trends, such as physical models combined with behavior models, shaping the future of RF power transistor modeling for more efficient communication systems.
- Published
- 2023
- Full Text
- View/download PDF
86. Automated design of a 3D passive microfluidic particle sorter.
- Author
-
Lai KM, Liu Z, Zhang Y, Wang J, and Ho TY
- Abstract
Microfluidic chips that can sort mixtures of cells and other particles have important applications in research and healthcare. However, designing a sorter chip for a given application is a slow and difficult process, especially when we extend the design space from 2D into a 3D scenario. Compared to the 2D scenario, we need to explore more geometries to derive the appropriate design due to the extra dimension. To evaluate sorting performance, the simulation of the particle trajectory is needed. The 3D scenario brings particle trajectory simulation more challenges of runtime and collision handling with irregular obstacle shapes. In this paper, we propose a framework to design a 3D microfluidic particle sorter for a given application with an efficient 3D particle trajectory simulator. The efficient simulator enables us to simulate more samples to ensure the robustness of the sorting performance. Our experimental result shows that the sorter designed by our framework successfully separates the particles with the targeted size., Competing Interests: The authors have no conflicts to disclose., (© 2023 Author(s).)
- Published
- 2023
- Full Text
- View/download PDF
87. A virtual reality intervention to improve formal caregivers' understanding of community-dwelling people with dementia: a pilot study.
- Author
-
Tsai CM, Hsu TC, and Hsieh CJ
- Subjects
- Humans, Caregivers psychology, Pilot Projects, Independent Living, Reproducibility of Results, Virtual Reality Exposure Therapy, Dementia psychology
- Abstract
Background: The optimum approach to enhance the understanding toward dementia is to experience how patients feel as they experience the manifestations of the disease. The application of virtual reality (VR) and relevant innovative technologies for developing caregiver training programs allows caregivers to better understand dementia and empathize with patients., Objectives: To develop a VR-based experiential training course on individualized care for the behavioral and psychological symptoms of dementia (BPSD)., Methods: The participants were caregivers of patients with dementia. They assessed the usability of the VR product after the intervention and the VR experience as a preliminary measure of the effectiveness of the intervention using a usability scale and a self-reported appraisal scale, respectively., Results and Conclusion: Ten in-service and in-home caregivers completed the VR training course. The course yielded a usability score of 74.06 points, indicating excellent usability. The content validity index (CVI) of the self-reported VR experience appraisal scale ranged from 0.8-1, scale-level CVI was 0.81, and reliability (Cronbach's α) was 0.929. The mean score of the overall scale was 4.67 ± 0.33. These findings suggest that the VR-based experiential training course enabled the home caregivers to deepen their understanding of the BPSD shown by community-dwelling patients and, therefore, to provide better care services. The course developed in this study is the first VR course directed toward dementia care in Taiwan. Given its excellent usability, as well as the effectiveness of the VR experience appraisal scale for deepening the caregivers' skills in managing patients' BPSD symptoms, the course can be promoted and applied in caregiver training programs for dementia in the future.
- Published
- 2023
- Full Text
- View/download PDF
88. Analytical and experimental study of a valveless piezoelectric micropump with high flowrate and pressure load.
- Author
-
Ni J, Xuan W, Li Y, Chen J, Li W, Cao Z, Dong S, Jin H, Sun L, and Luo J
- Abstract
Miniaturized gas pumps based on electromagnetic effect have been intensively studied and widely applied in industries. However, the electromagnetic effect-based gas pumps normally have large sizes, high levels of noises and high power consumption, thus they are not suitable for wearable/portable applications. Herein, we propose a high-flowrate and high-pressure load valveless piezoelectric micropump with dimensions of 16 mm*16 mm*5 mm. The working frequency, vibration mode and displacement of the piezoelectric actuator, the velocity of gas flow, and the volume flowrate of the micropump are analyzed using the finite element analysis method. The maximum vibration amplitude of the piezoelectric actuator reaches ~29.4 μm. The output gas flowrate of the pump is approximately 135 mL/min, and the maximum output pressure exceeds 40 kPa. Then, a prototype of the piezoelectric micropump is fabricated. Results show that performance of the micropump is highly consistent with the numerical analysis with a high flowrate and pressure load, demonstrated its great potential for wearable/portable applications, especially for blood pressure monitoring., Competing Interests: Conflict of interestThe authors declare no competing interests., (© The Author(s) 2023.)
- Published
- 2023
- Full Text
- View/download PDF
89. A New Analytical Large-Signal Model for Quasi-Ballistic Transport in InGaAs HEMTs Accommodating Dislocation Scattering.
- Author
-
Wang J, Liu J, Wang J, and Zhao Z
- Abstract
A surface-potential-based analytical large-signal model, which is applicable to both ballistic and quasi-ballistic transport in InGaAs high electron mobility transistors, is developed. Based on the one-flux method and a new transmission coefficient, a new two-dimensional electron gas charge density is derived, while the dislocation scattering is novelly taken into account. Then, a unified expression for Ef valid in all the regions of gate voltages is determined, which is utilized to directly calculate the surface potential. The flux is used to derive the drain current model incorporating important physical effects. Moreover, the gate-source capacitance Cgs and gate-drain capacitance Cgd are obtained analytically. The model is extensively validated with the numerical simulations and measured data of the InGaAs HEMT device with the gate length of 100 nm. The model is in excellent agreement with the measurements under I-V, C-V, small-signal conditions, and large-signal conditions.
- Published
- 2023
- Full Text
- View/download PDF
90. Recognition of Abnormal-Laying Hens Based on Fast Continuous Wavelet and Deep Learning Using Hyperspectral Images.
- Author
-
Qin X, Lai C, Pan Z, Pan M, Xiang Y, and Wang Y
- Subjects
- Animals, Female, Neural Networks, Computer, Algorithms, Chickens, Deep Learning
- Abstract
The egg production of laying hens is crucial to breeding enterprises in the laying hen breeding industry. However, there is currently no systematic or accurate method to identify low-egg-production-laying hens in commercial farms, and the majority of these hens are identified by breeders based on their experience. In order to address this issue, we propose a method that is widely applicable and highly precise. First, breeders themselves separate low-egg-production-laying hens and normal-laying hens. Then, under a halogen lamp, hyperspectral images of the two different types of hens are captured via hyperspectral imaging equipment. The vertex component analysis (VCA) algorithm is used to extract the cockscomb end member spectrum to obtain the cockscomb spectral feature curves of low-egg-production-laying hens and normal ones. Next, fast continuous wavelet transform (FCWT) is employed to analyze the data of the feature curves in order to obtain the two-dimensional spectral feature image dataset. Finally, referring to the two-dimensional spectral image dataset of the low-egg-production-laying hens and normal ones, we developed a deep learning model based on a convolutional neural network (CNN). When we tested the model's accuracy by using the prepared dataset, we found that it was 0.975 percent accurate. This outcome demonstrates our identification method, which combines hyperspectral imaging technology, an FCWT data analysis method, and a CNN deep learning model, and is highly effective and precise in laying-hen breeding plants. Furthermore, the attempt to use FCWT for the analysis and processing of hyperspectral data will have a significant impact on the research and application of hyperspectral technology in other fields due to its high efficiency and resolution characteristics for data signal analysis and processing.
- Published
- 2023
- Full Text
- View/download PDF
91. Numerical Study of Particle Separation through Integrated Multi-Stage Surface Acoustic Waves and Modulated Driving Signals.
- Author
-
Jiang Y, Chen J, Xuan W, Liang Y, Huang X, Cao Z, Sun L, Dong S, and Luo J
- Abstract
The manipulation of biomedical particles, such as separating circulating tumor cells from blood, based on standing surface acoustic wave (SSAW) has been widely used due to its advantages of label-free approaches and good biocompatibility. However, most of the existing SSAW-based separation technologies are dedicated to isolate bioparticles in only two different sizes. It is still challenging to fractionate various particles in more than two different sizes with high efficiency and accuracy. In this work, to tackle the problems of low efficiency for multiple cell particle separation, integrated multi-stage SSAW devices with different wavelengths driven by modulated signals were designed and studied. A three-dimensional microfluidic device model was proposed and analyzed using the finite element method (FEM). In addition, the effect of the slanted angle, acoustic pressure, and the resonant frequency of the SAW device on the particle separation were systemically studied. From the theoretical results, the separation efficiency of three different size particles based on the multi-stage SSAW devices reached 99%, which was significantly improved compared with conventional single-stage SSAW devices.
- Published
- 2023
- Full Text
- View/download PDF
92. Modeling the Effects of Threading Dislocations on Current in AlGaN/GaN HEMT.
- Author
-
Liu C, Wang J, Chen Z, Liu J, and Su J
- Abstract
The aim of this paper is to model the effects of threading dislocations on both gate and drain currents of AlGaN/GaN high electron mobility transistors (HEMTs). The fraction of filled traps increases with the threading dislocations, while the trapping effects cause a decrease in drain current and an increase in gate leakage current. To model the drain current drop, the two simplified RC subcircuits with diodes are proposed to capture the charge trapping/detrapping characteristics. The trap voltages V
g_trap and Vd_trap generated by RC networks are fed back into the model to capture the effects of traps on drain current. Considering acceptor-decorated dislocations, we present a novel Poole-Frenkel (PF) model to precisely describe the reverse leakage gate current, which plays a dominant role in the gate leakage current. The proposed model, which uses physical parameters only, is implemented in Verilog-A. It is in excellent agreement with the experimental data.- Published
- 2023
- Full Text
- View/download PDF
93. Editorial for the Special Issue on Advanced Interconnect and Packaging.
- Author
-
Zhao WS
- Abstract
Unlike transistors, the continuous downscaling of feature size in CMOS technology leads to a dramatic rise in interconnect resistivity and concomitant performance degradation [...].
- Published
- 2023
- Full Text
- View/download PDF
94. Electrical Modeling and Characterization of Graphene-Based On-Chip Spiral Inductors.
- Author
-
Wang DW, Yuan MJ, Dai JY, and Zhao WS
- Abstract
This paper investigates the electrical performance of graphene-based on-chip spiral inductors by virtue of a physics-based equivalent circuit model. The skin and proximity effects, as well as the substrate loss effect, are considered and treated appropriately. The graphene resistance and inductance are combined into the circuit model. It is demonstrated that the electrical characteristics of the on-chip square spiral inductor can be improved by replacing copper with graphene. Moreover, graphene exhibits more effectiveness in improving the inductance in tapered inductors than uniform ones.
- Published
- 2022
- Full Text
- View/download PDF
95. Design of plasmonic enhanced all-optical phase-change memory for secondary storage applications.
- Author
-
Lian X, Liu C, Fu J, Liu X, Ren Q, Wan X, Xiao W, Cai Z, and Wang L
- Abstract
Phase-change optical device has recently gained tremendous interest due to its ultra-fast transmitting speed, multiplexing and large bandwidth. However, majority of phase-change optical devices are only devoted to on-chip components such as optical tensor core and optical main memory, while developing a secondary storage memory in an optical manner is rarely reported. To address this issue, we propose a novel phase-change optical memory based on plasmonic resonance effects for secondary storage applications. Such design makes use of the plasmonic dimer nanoantenna to generate plasmonic resonance inside the chalcogenide alloy, and thus enables the performance improvements in terms of energy consumption and switching speed. It is found that choosing height, radius, and separation of the plasmonic nanoantenna as 10 nm, 150 nm, and 10 nm, respectively, allows for a write/erase energies of 100 and 240 pJ and a write/erase speed of 10 ns for crystallization and amorphization processes, respectively. Such performance merits encouragingly prevail conventional secondary storage memories and thus pave a route towards the advent of all-optical computer in near future., (© 2022 IOP Publishing Ltd.)
- Published
- 2022
- Full Text
- View/download PDF
96. Recent Progress in Physics-Based Modeling of Electromigration in Integrated Circuit Interconnects.
- Author
-
Zhao WS, Zhang R, and Wang DW
- Abstract
The advance of semiconductor technology not only enables integrated circuits with higher density and better performance but also increases their vulnerability to various aging mechanisms which occur from front-end to back-end. Analysis on the impact of aging mechanisms on circuits' reliability is crucial for the design of reliable and sustainable electronic systems at advanced technology nodes. As one of the most crucial back-end aging mechanisms, electromigration deserves research efforts. This paper introduces recent studies on physics-based modeling of electromigration aging of on-chip interconnects. At first, the background of electromigration is introduced. The conventional method and physics-based modeling for electromigration are described. Then studies on how electromigration affects powers grids and signal interconnects are discussed in detail. Some of them focus on the comprehensiveness of modeling methodology, while others aim at the strategies for improving computation accuracy and speed and the strategies for accelerating/decelerating aging. Considering the importance of electromigration for circuit reliability, this paper is dedicated to providing a review on physics-based modeling methodologies on electromigration and their applications for integrated circuits interconnects.
- Published
- 2022
- Full Text
- View/download PDF
97. A Bond-Wire Drift Offset Minimized Capacitance-to-Digital Interface for MEMS Accelerometer with Gain-Enhanced VCO-Based Quantization and Nested Digital Chopping Feedback Loops.
- Author
-
Li F, Yin T, and Yang H
- Abstract
This paper presents an output offset minimized capacitance-to-digital interface for a MEMS accelerometer. With a gain-enhanced voltage-controlled oscillator (VCO)-based quantization loop, the interface is able to output a digital signal with improved dynamic range. For optimizing the output offset caused by nonideal factors (e.g., the bond-wire drift), a nested digital chopping feedback loop is embedded in the VCO-based quantization loop. It enables the interface to minimize the output offset without digital filtering and digital-to-analog conversion. The proposed architecture is well suited for dynamic range and offset improvements with low cost. Fabricated with a 0.18 μm Global Foundry (GF) CMOS process, the interface offers a 78 dB dynamic range with 0.4% nonlinearity from a single 2 V supply. With the input referred offset up to 1.3 pF, the offset cancellation loop keeps the DC output offset within 40 mV. The power dissipation is 6.5 mW with a bandwidth of 4 kHz.
- Published
- 2021
- Full Text
- View/download PDF
98. Predicting the fluid behavior of random microfluidic mixers using convolutional neural networks.
- Author
-
Wang J, Zhang N, Chen J, Su G, Yao H, Ho TY, and Sun L
- Abstract
With the various applications of microfluidics, numerical simulation is highly recommended to verify its performance and reveal potential defects before fabrication. Among all the simulation parameters and simulation tools, the velocity field and concentration profile are the key parts and are generally simulated using finite element analysis (FEA). In our previous work [Wang et al., Lab Chip, 2016, 21, 4212-4219], automated design of microfluidic mixers by pre-generating a random library with the FEA was proposed. However, the duration of the simulation process is time-consuming, while the matching consistency between limited pre-generated designs and user desire is not stable. To address these issues, we inventively transformed the fluid mechanics problem into an image recognition problem and presented a convolutional neural network (CNN)-based technique to predict the fluid behavior of random microfluidic mixers. The pre-generated 10 513 candidate designs in the random library were used in the training process of the CNN, and then 30 757 brand new microfluidic mixer designs were randomly generated, whose performance was predicted by the CNN. Experimental results showed that the CNN method could complete all the predictions in just 10 seconds, which was around 51 600× faster than the previous FEA method. The CNN library was extended to contain 41 270 candidate designs, which has filled up those empty spaces in the fluid velocity versus solute concentration map of the random library, and able to provide more choices and possibilities for user desire. Besides, the quantitative analysis has confirmed the increased compatibility of the CNN library with user desire. In summary, our CNN method not only presents a much faster way of generating a more complete library with candidate mixer designs but also provides a solution for predicting fluid behavior using a machine learning technique.
- Published
- 2021
- Full Text
- View/download PDF
99. Finding the optimal design of a passive microfluidic mixer.
- Author
-
Wang J, Zhang N, Chen J, Rodgers VGJ, Brisk P, and Grover WH
- Abstract
The ability to thoroughly mix two fluids is a fundamental need in microfluidics. While a variety of different microfluidic mixers have been designed by researchers, it remains unknown which (if any) of these mixers are optimal (that is, which designs provide the most thorough mixing with the smallest possible fluidic resistance across the mixer). In this work, we automatically designed and rationally optimized a microfluidic mixer. We accomplished this by first generating a library of thousands of different randomly designed mixers, then using the non-dominated sorting genetic algorithm II (NSGA-II) to optimize the random chips in order to achieve Pareto efficiency. Pareto efficiency is a state of allocation of resources (e.g. driving force) from which it is impossible to reallocate so as to make any one individual criterion better off (e.g. pressure drop) without making at least one individual criterion (e.g. mixing performance) worse off. After 200 generations of evolution, Pareto efficiency was achieved and the Pareto-optimal front was found. We examined designs at the Pareto-optimal front and found several design criteria that enhance the mixing performance of a mixer while minimizing its fluidic resistance; these observations provide new criteria on how to design optimal microfluidic mixers. Additionally, we compared the designs from NSGA-II with some popular microfluidic mixer designs from the literature and found that designs from NSGA-II have lower fluidic resistance with similar mixing performance. As a proof of concept, we fabricated three mixer designs from 200 generations of evolution and one conventional popular mixer design and tested the performance of these four mixers. Using this approach, an optimal design of a passive microfluidic mixer is found and the criteria of designing a passive microfluidic mixer are established.
- Published
- 2019
- Full Text
- View/download PDF
100. Integral Equation Prediction of the Structure of Alternating Copolymer Nanocomposites near a Substrate.
- Author
-
Xu Q, Chen L, Yang F, and Cao H
- Abstract
The packing structure and phase behavior of polymer-nanoparticle mixtures under confinement play an important role in developing strategies for rational design of nanomaterials. However, understanding the microscopic dispersion and aggregation mechanism of polymer nanocomposites is a great challenge through experimental techniques. In this work, the microscopic structure of alternating copolymer nanocomposites (ACNs) near a substrate is investigated systematically through extension of the inhomogeneous polymer reference interaction site model (PRISM) theory. In order to characterize the flexibility and internal chain stiffness of copolymers, a semiflexible chain model is introduced to describe the intramolecular correlations between different monomers. Based on the bridge functionals derived from the fluids density functional theory, the modified hypernetted chain closure is integrated with the PRISM equation to form a full theoretical framework to capture the density distributions of ACNs. The influence of the particle volume fraction, nanoparticle diameter, and adsorption strengths between different interaction sites on the packing structure of ACNs under confinement is analyzed and discussed in detail. With the increase of the particle volume fraction, the size asymmetry between nanoparticles and copolymer monomers can greatly influence the density profiles of ACNs near a substrate. Increasing the nanoparticle diameter, the density distribution of nanoparticles experiences a process from absorbing onto the solid surface to segregating from the wall to larger distances. With increasing the adsorption strength between copolymers and nanoparticles, the density distribution of nanoparticles decreases, which is similar to the case of nanoparticles containing attractive interactions. All these characteristics of ACNs show that the current inhomogeneous PRISM theory can give a detailed description of the packing behavior of different segments. Predictive approaches could be desired and developed for design control of alternating copolymer nanocomposites under confinement.
- Published
- 2018
- Full Text
- View/download PDF
Catalog
Discovery Service for Jio Institute Digital Library
For full access to our library's resources, please sign in.