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Moet Europa eigen fabrieken voor de productie van nanochips bouwen? De Europese Commissie vindt van wel en nu lijkt ook hoofdrolspeler ASML overstag.

High selectivity becomes increasingly important with an increasing number of devices that compete in the congested 2.4-GHz industrial, scientific, and medical (ISM)-band. In addition, low power consumption is very important for Internet-of-Things (IoT) receivers. We propose a 2.4-GHz zero-intermediate frequency (IF) receiver front-end architecture that reduces power consumption by 2 $\times $ compared with state-of-the-art and improves selectivity by >20-dB without compromising on other receiver metrics. To achieve this, the entire receive chain is optimized. The low-noise transconductance amplifier (LNTA) is optimized to combine low noise with low power consumption. State-of-the-art sub-30-nm complementary metal–oxide–semiconductor (CMOS) processes have almost equal strength complementary field-effect transistors (FETs) that result in altered design tradeoffs. A Windmill 25%-duty cycle frequency divider architecture is proposed, which uses only a single NOR-gate buffer per phase to minimize power consumption and phase noise. The proposed divider requires half the power consumption and has 2 dB or more reduced phase noise when benchmarked against state-of-the-art designs. An analog finite impulse response (FIR) filter is implemented to provide very high receiver selectivity with ultralow power consumption. The receiver front end is fabricated in a 22-nm fully depleted silicon-on-insulator (FDSOI) technology and has an active area of 0.5 mm2. It consumes 370 $\mu \text{W}$ from a 700-mV supply voltage. This low power consumption is combined with a 5.5-dB noise figure. The receiver front end has −7.5-dBm input-referred third-order-intercept point (IIP3) and 1-dB gain compression for a −22-dBm blocker, both at maximum gain of 61 dB. From three channels offset onward, the adjacent channel rejection (ACR) is ≥63 dB for Bluetooth Low-Energy (BLE), BT5.0, and IEEE802.15.4.

Computers zijn in staat om de chips van hun opvolgers zelf vorm te geven. Decennialang werd het tekenen van de plattegrond van de chips door mensen gedaan, maar ook dit gebied moeten zij prijsgeven aan de automatisering.

Summary form only given, as follows. The complete presentation was not made available for publication as part of the conference proceedings. During the past decades wireless communication has made an enormous growth. Triggered by a large R&D effort, the integration of transceivers in CMOS technology has made low-cost mass production possible. For many applications like Bluetooth, a single-chip CMOS transceiver can now do the job. On the other hand, for complex transceivers like in modern smartphones, still more discrete RF components such as filters, switches and diplexers are being added to protect the transceiver from strong interferers which are often produced by the device itself. To satisfy the future bandwidth hunger, the number of frequency bands will further increase, modulation schemes will become more complex, more antennas will be used and carrier aggregation will be the norm. To limit the number of discrete RF components, linearity of the transceivers is key. Since more computing power will be needed in future transceivers as well, newer CMOS technologies are also wanted. CMOS technology will scale in favor of fast-switching digital circuits, but not for classical analog functions, like amplifiers. For the next fifteen years re-thinking of basic circuits and systems will be needed to make highly integrated linear transceivers, in a technology that is designed for digital circuits.

Chips zitten overal in. In koffieapparaten, tv’s, oortjes, webcams en uiteraard ook in mobieltjes, tablets en laptops. Normaal gesproken doen ze op de vierkante millimeter onverstoorbaar hun noodzakelijke werk. Ze kosten bijna niets en zijn onmisbaar geworden in het dagelijks leven. En nu zitten we in een wereldwijde chipcrisis. Hoe komt dat? Verstoord evenwicht Het korte antwoord: corona. ‘Jarenlang heeft de wereldwijde chipindustrie prima gefunctioneerd’, legt Bram Nauta, hoogleraar elektrotechniek aan de Universiteit Twente, uit. De industrie plaatste zijn bestellingen bij de grote chipfabrikanten en die zorgden ervoor dat hun fabrieken constant op volle toeren draaiden. Dit evenwicht is nu verstoord.

A highly reconfigurable direct-conversion software-defined multiple-input multiple-output (MIMO) receiver with four RF inputs and four I/Q baseband outputs is proposed. It allows for digital MIMO but also analog interference rejection by spatial notch filtering through four flexible and simultaneous orthogonal beams. A segmented constant-Gm vector modulator (VM) with improved interference tolerance and wide RF frequency range targeting the sub-6-GHz bands is proposed. It exploits current-domain beamforming before $I$ – $V$ conversion by transimpedance amplifiers. A 0.7–5.7-GHz 22-nm fully depleted silicon-on-insulator (FD-SOI) prototype chip achieves >29 dB spatial filtering for a single notch and an ultrawideband 20-dB notch suppression bandwidth of 2.3 GHz at broadside excitation at an local oscillator (LO) frequency of 2.5 GHz. In the notches, an IIP3 of +16 dBm and B1dB of −11.5 dBm at a 41-dB gain is achieved, improving IIP3 and B1dB by 35 and 27 dB, respectively, by spatial filtering. A single-element noise figure (NF) of 5.5–7 dB is achieved on the VM constellation corners, degrading about 2 dB on the points nearby the biggest circle fitting into a square constellation. However, sub-3-dB system NF is potentially achievable, taking into account up to 6-dB improvement by the four-element beamforming. Given both gain and phase control provided by the VM, spatial patterns with up to three independent nulls can be synthesized with the four-element antenna array. The chip of 0.52 mm2 active area consumes 77–139 mW at an LO-frequency of 0.7–5.7 GHz from a 0.8-V supply.

The application of stacked-FETs in power amplifiers allows for a supply voltage higher than supported by the breakdown voltage of a single transistor. Potential benefits of the increased supply voltage are reduced supply currents and a lower matching ratio at the output of the amplifier. Furthermore, an increased output power per chip area is obtained due to the reduction in passive structures resulting in more area-efficient power combining. In this paper, the procedure for the design of integrated microwave stacked-FET is discussed. Several options for the correct distribution of RF voltage and current swings are investigated and the relationship between the number of stacked transistors and bandwidth is addressed. The procedure is demonstrated by the design of an S-band GaAs stacked-FET containing three transistors. This stacked-FET is applied in an S-band HPA that has a PAE of more than 40% at an output power of 20 W, which is more than twice the output power of any previously reported GaAs stacked-FET HPA.

A technique is proposed for increasing the data rate transmitted through an inductively coupled chip-to-chip link by resetting the channel state variables. This allows the data rate to be increased well beyond what is implied by the channel bandwidth. In the proposed scheme, the two sides of the link are resonated at the highest possible quality factor, maximizing link gain, and minimizing interference. The transmit signal is a binary matched pulse which maximizes the received signal for a given transmitter voltage limit. High-efficiency switching transmitters can be used for this type of signal. The proposed technique can be applied to communication links in which channel state variables are accessible for reset. For increasing the data rate, it is shown that the proposed state-variable reset technique results in a higher signal-to-noise ratio of the received signal and a higher energy efficiency compared to reducing the quality factor to widen the bandwidth, using equalization, or using multi-level signaling. The technique is demonstrated on a chip-to-chip link with coupled 1.5 mm $\times1.5$ mm planar inductors separated by 0.5 mm in a 0.18 $\mathrm {\mu m}$ CMOS process. 500 Mb/s data rate is achieved over a link which has a band-pass bandwidth of 185 MHz.

This paper presents an energy-/area-efficient digitally controlled oscillator (DCO)-based phase-tracking Receiver for Internet-of-Things (IoT) applications. The RX leverages the constant-envelope nature of frequency shift keying modulation adopted in many IoT protocols, e.g., IEEE802.15.4 and Bluetooth low energy (BLE), to enhance the energy efficiency and to reduce the chip area. The proposed RX, with the DCO acting as a local oscillator (LO) and binary frequency feedback, promotes low-power and low-voltage circuit design, while a data-aided carrier-frequency tracking ensures the received carrier stability without a power-/area-hungry phase-locked loop (PLL). The RX avoids a compromise between a power-hungry I/Q LO generation and the image rejection in traditional RXs. An equivalent mathematical model is further presented, which helps to analyze and optimize the frequency response of the proposed RX. Fabricated in 40-nm CMOS, the RX consumes 1.55 mW from a 0.85-V supply and has a −87-dBm sensitivity at 2 Mb/s, which leads to a 0.77-nJ/b energy efficiency and 178-dB RX sensitivity FoM.

The wireless receiver has a significant impact on the connectivity performance and battery lifetime of Internet-of-Things (IoT) devices. High selectivity becomes increasingly important with an increasing number of devices that compete in the congested 2.4GHz industrial, scientific and medical (ISM) band. In addition, low power consumption is very important for IoT receivers as the burden of changing batteries increases proportionally with the number of the devices. Complementary metal-oxide-semiconductor (CMOS) technology allows for highly integrated IoT devices with small form factor, low digital processing power consumption and low costs. The dissertation presents circuit innovations for a CMOS wireless IoT receiver, that allow to improve the performance of an IoT receiver while reducing its power consumption. An analog FIR filter is proposed that allows for a >20dB increased selectivity. Furthermore, the analog FIR techniques proposed in the dissertation have many other potential applications. The proposed Windmill divider architecture halves the power consumption while reducing the phase noise. The feedforward phase noise cancellation architecture reduces the PLL rms jitter by 7.2dB without significantly increasing its power consumption. These innovations help to pave the way to an all connected world – not just connecting everyone, but connecting everything.

A crystal oscillator circuit (100, 200) is described that includes a crystal resonator (220); and a voltage source (204) configured to apply a voltage step across the crystal oscillator (220) where a polarity of the voltage source (204) applied to the crystal resonator (220) is switched in response to a sign of a current passing through the crystal resonator (220) and in response thereto a self-timed energy injection waveform is provided to the crystal resonator (220).

Systems and methods for analog finite impulse response (FIR) filters are provided. In certain embodiments, a receiver includes a cascade of a mixer, an analog FIR filter, and an analog-to-digital converter (ADC). By including the analog FIR filter along the signal path between the mixer and the ADC, design constraints of the ADC are relaxed. For example, the ADC can operate with relaxed specifications with respect to resolution and/or dynamic range when the analog FIR filter is included. The analog FIR filter can include a controllable transconductance circuit that delivers an integration current to a capacitor over an integration period, with the analog FIR filter's coefficients used to change the transconductance setting of the controllable transconductance circuit to different values over the integration period.

—Digital Multiple-Input Multiple-Output (MIMO) receivers, exposed to strong co-channel interference, require high dynamic range Analog-to-Digital Converters (ADCs) and a highly linear RF front-end. Hybrid analog-digital beamforming can mitigate this co-channel interference by spatial filtering before the ADC and improve interference robustness. This paper demonstrates and characterizes this mitigation effect in detail utilizing Error Vector Magnitude (EVM) as a criterion. A 4-element 22 nm FD-SOI CMOS prototype MIMO Receiver chip is characterized with a linear 4-element dipole antenna array with half-wavelength spacing in the 2.4 GHz ISM-band. EVM measurements demonstrate the effectiveness of spatial filtering for co-channel interference mitigation and dynamic range extension. The receiver is exposed to interference while using different QAM formats (16-QAM to 256-QAM). It is demonstrated how interference reduces the acceptable-EVM input power range, while hybrid beamforming extends this range. This is done by extensive conductive measurements for reliable results, while also demonstrating an Over-the-Air (OTA) result

The modern spectral, and thereby linearity, requirements force 5G phased-array transmitter systems to operate at reduced power efficiency, as they can no longer use voluminous filtering. To reduce the linearity requirements of the transmitter, we consider the case of an array consisting of closely spaced radiating elements operating at different frequencies. The coupled tones from one element to another create reverse intermodulation distortion (RIMD). We explain how RIMD is created within a power amplifier (PA), and derive an estimate for the power of the RIMD components. We provide a set of measurements for an X-Band GaAs PA and draw a direct comparison between RIMD and IMD. We show that RIMD has a third-order behaviour up to very high reverse power levels, opening up the perspective for higher output power operation as well as simpler and lower-power predistortion in multi-tone array systems such as 5G and radar.

Merging developments in RFID and wireless sensor networks have increased the interest in using backscatter radio for tag-to-tag communication. Low power consumption is a major concern, often limiting the choice to incoherent receivers such as diode envelope detectors. Link budget calculations require receiver sensitivity specifications, however accurate characterizations are scarce. In this work, we show that the receiver sensitivity is strongly related to the exciter incident power. Full-range analysis of a zero-bias diode detector shows a decreasing noise factor at higher incident powers, which leads to improved sensitivity. On the other side, at strong incident powers, the phase noise of the exciter interferes with the received signal, setting an lower bound to the sensitivity of the backscatter receiver. This work proposes a semi-passive RFID tag capable of 1kbps to 10kbps data rates in the 434MHz band using off the shelf components. The tag has a low power consumption of 85μW during receive, 45μW during transmit and less than 4μW in sleep. The receiver sensitivity at 1kbps shows a 25dB variation as a function of exciter incident power between -50 to 10dBm, while a peak sensitivity of around -80dBm is measured at an incident power of -25dBm.

China maakt zeer geavanceerde technologie, maar niet de microchips waarop die draait. Dus hoe moet dat nu Chinese techbedrijven in de VS op een zwarte lijst staan? De strijd tussen wereldmachten in de technologie.

Power amplifiers (PAs) need digital predistortion (DPD) linearization to handle high-order complex modulation schemes in next-generation communication systems. While load variation is inevitable, DPD is generally designed considering only the nominal load impedance for PAs. This paper presents a polar class-E PA with an on-chip waveform characterizer enabling adaptive digital predistortion (ADPD) to preserve the linearity of the PA under load mismatch. The presented ADPD corrects both AM/AM and AM/PM distortions, which are prominent in the demonstrated PA, while simultaneously correcting for slow memory effects without the need for complex memory DPD algorithms. Load-pull measurements demonstrate that target error vector magnitude (EVM) and adjacent channel power ratio (ACPR) can be maintained in a significantly larger area on the Smith chart going from 50 Ω optimized static DPD to our ADPD for a 2 GHz 1024 QAM signal with 1 MSym/s symbol rate.

After the occurrence and detection of a short circuit to ground in the LHC main dipole circuit, a fast power abort is triggered and the current in the circuit starts decaying semi-exponentially from a maximum value of 11.85 kA to zero, with a time constant of 103 s. If a short to ground occurs, the current flows through the fuse that is present in the grounding subcircuit. Depending on the value of the thermal load, the fuse first enters a pre-arcing region where it starts intermittently blowing up, until the blow-up threshold is reached, after which it definitively blows up. A simulation scheme utilising a common interface between PSpice and Matlab is proposed in order to simulate the blow-up behaviour of the fuse and hence increase the accuracy of the circuit model for short circuits to ground. A parametric analysis of the short circuit to ground parameters is performed and a better understanding of the behaviour of the circuit under different conditions is obtained. The worst-case values of the voltage to ground in the LHC main dipole circuit are identified for both the case where the intermittent behaviour of the fuse is included in the model as well as for the case where the fuse is not modelled and a comparison between the two is given.

In this letter, we present a design of a linear array of tilted dipoles to achieve radiation patterns with asymmetric angular filtering characteristics. To realize the asymmetric radiation, the dipole elements are spaced by a distance larger than half a wavelength, thus allowing for grating lobes to occur in the visible region. Moreover, the dipoles are loaded with artificial dielectrics to increase the front-to-back ratio and consequently to enable higher gain in certain desired angular regions. Based on the design, a linear array with ten elements is manufactured and tested. The measured results show the ability of such an array to achieve stable gain from broadside up to 90° scanning while implementing a stopband angular filter for negative scanning angles. © 2002-2011 IEEE.

Upcoming Internet-of-Things (IoT) applications require low-power multi-standard RF receiver (RX) front-ends. Interference rejection becomes increasingly important as ever more devices compete in the scarce 10w-GHz spectrum. Typically, low-power RXs do not possess very steep filtering [1]–[6]. On the other hand, very selective RXs - e.g. using analog FIR or Filtering-by-Aliasing [7] - have very high power consumption, not suitable for IoT applications. A recent Analog Finite-Impulse-Response (AFIR) filter [8] shows promising results to improve channel filtering. [8] uses a much lower FIR update rate than [7] to considerably reduce power consumption. This comes at the cost of a filter alias, but the inherent windowed integration sinc filtering mitigates this filter alias. Achieving low RX Noise Figure (NF), while improving selectivity is challenging at ultra-low power, where all blocks tend to contribute significantly to the total power consumption [1]–[6].

An inductor arrangement has a first inductor structure having one or more inductors at least partially on a first layer and a second inductor structure having one or more inductors at least partially on a second layer. The inductors are arranged such that currents induced by an external magnetic field are substantially cancelled in at least one of the first inductor structure and the second inductor structure. The, or each, inductor of the second inductor structure overlaps, at least partially, the, or each, inductor of the first inductor structure. An oscillator circuit having an inductor arrangement is also presented.

In this article, we investigate the radiation and impedance properties of arrays of tilted dipoles. A spectral periodic method of moments (MoM) is developed for the analysis of infinite arrays with arbitrarily tilted dipole elements, in free space or with a backing reflector. With the aid of this analysis method, the radiation characteristics of arrays of stacked dipoles over a ground plane are studied, explaining the variation of the patterns as a function of the interelement distance and the angle of inclination of the elements. Finite linear arrays of tilted dipoles are also investigated, to assess the dependence of the array characteristics on the number of elements. The developed method can be used to design arrays with nonsymmetric radiation patterns for angular filtering or pattern shaping.

A five-layer frequency selective surface (FSS) composed of subwavelength elements with large harmonic rejection bandwidth is presented. The FSS design is based on an equivalent circuit model, where the interlayer interaction is only described with a single transmission line representing the fundamental Floquet wave. A prototype of the designed FSS is fabricated, and the measured response exhibits good stability over a wide conical incidence range up to 45°. The FSS is combined with a wide-scanning connected array of dipoles to implement a phased array with integrated filtering properties. A dispersion analysis is performed to define the distance between the array and the FSS that avoids the propagation of surface waves between the combined structures, allowing to maximize the radiation efficiency. The performance of the array combined with the FSS is experimentally characterized, showing high-order harmonic rejection better than 17 dB over a large bandwidth.

We report on the dependency of the optical power efficiency $\eta $ on the breakdown voltage ${V}_{\text {BR}}$ of avalanche-mode (AM) light-emitting diodes (LEDs) in silicon. Lateral p+-n-n+ LEDs have been designed in a 65-nm bulk CMOS technology, where ${V}_{\text {BR}}$ is varied between 2 and 9 V. This tunes both the magnitude and the spatial distribution of the reverse electric field, which governs AM electroluminescence. Experiments show that a maximum $\eta $ of $\sim 1.7 \times 10^{-6}$ is obtained for ${V}_{\text {BR}} \sim 6$ V. For ${V}_{\text {BR}} V, non-local avalanche results in a lower $\eta $ , while for ${V}_{\text {BR}} > 6$ V, a gradual reduction in $\eta $ with increasing ${V}_{\text {BR}}$ is obtained. This trend is compared with two recently proposed opto-electronic models. A maximum in $\eta $ at relatively low voltages is attractive for monolithic opto-electronic integration in silicon

Power amplifier nonlinearity introduces intermodulation distortion when transmitting dual-tone signals from an antenna array. To reduce distortion levels and increase output power for dual-tone systems we propose to densely interleave two antenna arrays without increasing the antenna aperture. Each array is excited with a different tone, resulting in a single-tone input for the power amplifiers, thereby reducing intermodulation distortion. In order to compare the performance of the densely interleaved array with a regular, planar array, when excited by two-tone signals, a procedure for evaluating the S-parameters matrix of an interleaved dipole array is presented. Simulations with a realistic RF power amplifier model show 13 to 31 dB intermodulation reduction for the same output power and total antenna aperture.

Meer dan veertig jaar geleden voorspelde Gordon Moore dat het aantal componenten op computerchips elke twee jaar zou verdubbelen. Tot nu toe weet de computerindustrie daar aardig aan te voldoen. Maar volgens veel deskundigen is het eind van deze razendsnelle vooruitgang in zicht. Hebben de doemdenkers gelijk?

Subthreshold amplifiers suffer from the limited voltage headroom which leaves little space for conventional analog techniques to enhance performance and efficiency. This paper presents an evolution process of implementing conventional structures with inverters, allowing ultralow-voltage operation with increased flexibility in adopting traditional circuit techniques. Based on the proposed inverter-based elementary structure and CMFB, both the Miller-compensated (MC) operational transconductance amplifier (OTA) and the feedforward-compensated (FFC) OTA achieve significantly improved performance as compared to previous works. The proposed amplifier techniques are verified in $\Delta \Sigma $ modulator (DSM) design, with MC-OTA for a DT-DSM and FFC-OTA for a CT-DSM, both fabricated in a 0.13- $\mu \text{m}$ CMOS. The 0.3-V DT-DSM achieves 74.1-dB SNDR, 83.4-dB SFDR and 20-kHz bandwidth with 79.3- $\mu \text{W}$ power, resulting in a Schreier figure of merit (FoM) of 158 dB. The 0.3-V CT-DSM achieves 68.5-dB SNDR, 82.6-dB SFDR, and 50-kHz bandwidth with 26.3- $\mu \text{W}$ power, leading to a Schreier FoM of 161 dB. Both DSMs exhibit highly competitive performance among sub-0.5-V designs, validating the proposed subthreshold amplifier techniques.

This paper defines a criterion called the overall efficiency (OE) for evaluating the efficiency of acoustic sources. In practice, the conventional efficiency (CE), is not capable of giving a comprehensive overview of the power consumption, especially in the connected amplifier drivers. The reason for this is that the CE is defined based on the nominal input electrical power. The nominal input electrical power is defined as the real part of the power that is delivered by the electrical amplifier to the actuation unit of an acoustic source. Therefore, power loss in the amplifier unit is not included in the CE definition. With the aid of the OE criterion, the effect of power loss in the connected amplifier units is taken into account. In particular, the application of the OE is crucial for acoustic sources that operate in a low frequency range. This is due to the reactive nature of power in both actuators and connected amplifiers. In the current paper, various combinations of amplifiers and actuators are studied. In particular, voice coil actuators and piezoelectric stack elements including both Lead Zirconate Titanate (PZT) ceramics and single crystal Lead Zirconate Niobate-Lead Titanate (PZN-PT) piezoelectric materials are investigated. In addition, the effect of a connected power driver is investigated. A class AB and a class D amplifier are studied respectively as analogue and switching amplifiers. Unlike a class AB amplifier, a class D amplifier is capable of energy recovery. A perforated flat acoustic source is examined in this paper as a practical example to verify the OE criterion. The numerical simulation on a thin acoustic source shows that for a single actuator, thanks to energy recovery, the OE is higher in a class D amplifier than that in a class AB amplifier. This study reveals that if a class D amplifier is the driver, using piezoelectric actuators results in a higher OE compared to using a voice coil actuator. Measurements on the sample acoustic source verify the numerical results presented in the current study.

Low-power and low-jitter equalization techniques become increasingly crucial for the wire-line receivers operating at data rates more than tens of gigabits per second. This brief reports an inductorless and power-efficient 32-Gb/s hybrid analog equalizer. The hybrid analog equalizer utilizes a triple-gate control to achieve equalization over a range of channel loss resulting in an inductorless and area-efficient design. The triple-gate controls entail that a low-frequency equalization is achieved in addition to the intermediate and high-frequency equalization, at minimum area overhead. The prototype is realized in a 65-nm CMOS, occupying a compact active area of 0.013 mm2. The maximum equalization achieved is 21 dB at Nyquist with a measured peak-to-peak data jitter of 5.25 ps (0.17 unit interval) at 32 Gb/s for a 231 - 1 pseudorandom bit sequence signal. The measurement shows a vertical eye-opening recovery rate of up to 61% at 32 Gb/s, for a channel loss of 21 dB. The prototype exhibits a competitive power efficiency of 0.53 mW/Gb/s under a supply voltage of 1.2 V. MOE (Min. of Education, S’pore)

Frequency synthesizers are an essential building block of RF communication products. They can be found in traditional consumer products, in personal communication systems, and in optical communication equipment. Since frequency synthesizers are used in many different applications, different performance aspects may need to be considered in each case. The main body of the text describes a conceptual framework for analyzing the performance of PLL frequency synthesizers, and presents optimization procedures for the different performance aspects. The analysis of the PLL properties is performed with the use of the open-loop bandwidth and phase margin concepts, to enable the influence of higher-order poles to be taken into account from the beginning of the design process. The theoretical system analysis is complemented by descriptions of innovative system and building block architectures, by circuit implementations in bipolar and CMOS technologies, and by measurement results. Architectures for RF Frequency Synthesizers contains basic information for the beginner as well as in-depth knowledge for the experienced designer. It is widely illustrated with practical design examples used in industrial products. Written for: Electrical and electronic engineers

A CCD split-electrode transversal filter (EPSEF) with analog controlled tap weights is described. The programmable tap weighting utilizes a novel analog multiplier for sampled data, based on charge profiling underneath a resistive gate structure. The EPSEF device concept and the performance data of a prototype filter with eight programmable taps are presented. Applications of the EPSEF in several programmed filter functions and in an adaptive filter system are demonstrated.

A frequency reference generator includes ( i ) an integrated frequency source having drive circuitry that drives a reso nant ( e.g. , non - trimmable LC ) tank to generate an oscillator signal , ( ii ) at least one temperature sensor that generates at least one measured temperature signal , and ( iii ) a frequency adjustment circuit that adjusts the oscillator signal frequency to generate the frequency reference based on the measured temperature signal and a ( e.g. , sample - specific ) mapping from temperature to a corresponding frequency - adjustment parameter ( e.g. , a divisor value for a fractional frequency divider ) . In some embodiments , a Colpitts oscillator gener ates the oscillator signal based on the measured temperature signal , where the Colpitts oscillator has voltage / tempera ture - compensation circuitry that compensates for variations in power supply voltage and operating temperature . Such frequency reference generators achieve substantial PVT insensitivity with as little as a single 1T - trim or even no trim at all .