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In this paper, an electrostatic discharge (ESD) protection circuit is designed for use as a 12 V power clamp by using a parasitic-diode-triggered silicon controlled rectifier. The breakdown voltage and trigger voltage (V-t) of the proposed ESD protection circuit are improved by varying the length between the n-well and the p-well, and by adding n+/p+ floating regions. Moreover, the holding voltage (V-h) is improved by using segmented technology. The proposed circuit was fabricated using a 0.18-m bipolar-CMOS-DMOS process with a width of 100m. The electrical characteristics and robustness of the proposed ESD circuit were analyzed using transmission line pulse measurements and an ESD pulse generator. The electrical characteristics of the proposed circuit were also analyzed at high temperature (300 K to 500 K) to verify thermal performance. After optimization, the V-t of the proposed circuit increased from 14 V to 27.8 V, and V-h increased from 5.3 V to 13.6 V. The proposed circuit exhibited good robustness characteristics, enduring human-body-model surges at 7.4 kV and machine-model surges at 450 V.

In this paper, a Silicon Controlled Rectifier (SCR)-based Electrostatic Discharge (ESD) protection circuit with high holding voltage and high robustness characteristics is proposed. Unlike conventional SCR, the proposed circuit has low trigger voltage and high holding voltage and provides effective ESD protection with latch-up immunity. In addition, the TCAD simulation results show that the proposed circuit has better electrical characteristics than the conventional SCR. A stack technology was used for voltage-specific applications. Consequentially, the proposed circuit has a trigger voltage of 17.60 V and a holding voltage of 3.64 V., {"references":["R.G Wagner, J. Soden and C.F. Hawkins \"Extend and Cost of EOS/ESD Damage in an IC Manufacturing Process\", in Porc. of the 15th EOS/ESD Symp., pp.49-55, 1993.","Yong Seo Koo, et. al., \"Design of SCR-based ESD protection device for power clamp using deep-submicron CMOS technology,\" Microelectronics Journal, Vol. 40, pp. 1007-1012, 2009.","Sheng-Lyang Jang, et. al., \"Temperature-dependent dynamic triggering characteristics of SCR-type ESD protection devices,\" Solid-State Electronics, Vol.45, pp. 2005-2009, 2001.","P.-Y Ran, M. Indrajjit, P.-H. Li and S. H. Voldman. \"RC-triggered PNP and NPN Simultaneously Switched Silicon Controlled Rectrifier ESD Networks for Sub-0.18um Technology\" in proc. Of IEEE int. symp. On physical and failure Analysis of Intergrated Circuits, pp. 71-75, 2005.","W.Y Chen, et. al., \"Measurement on Snapback Holding voltage of High-Voltage LDMOS for Latch-up Consideration,\" device and system, APCCAS 2008, pp. 61-64, 2008.","Amerasekera A., Duvvury Charvaka \"ESD in Silicon Integrated Circuits\", New York:John Wiley and Sons, 2002.","Albert Z. H. Wang, \"On-chip ESD Protection for Integrated Circuits\", Kluwer Academic Publisher Group, 2002.","O. Quittard, Z. Mrcarica, F. Blanc, G. Notermans, T. Smedes, and H.van Zwol, \"ESD protection for high-voltage CMOS technologies,\" EOS/ESD Symp, pp. 77-86, 2006.","K. D Kim \"A Study on the Novel SCR Nano ESD Protection Device Design and Fabrication,\" j.inst. Korean. electr. electron. eng, vol. 9, no. 2, pp. 83-91, 2005.\n[10]\tM. D. Ker and H. H. Chang, \"How to safely apply the LVTSCR for CMOS whole-chip ESD protection without being accidentally triggered on,\" J. Electro- statics, vol. 47, pp.215-248, 1999.\n[11]\tY. Koo, K. Lee, K. Kim, and J. Kwon, \"Design of SCR-based ESD protection device for power clamp using deep-submicron CMOS technology,\" Microelectronics Journal, vol. 40, pp. 1007-1012, 2009.\n[12]\tS.-L. Jang, L.-S. Lin, and S.-H. Li, \"Temperature-dependent dynamic trig-gering characteristics of SCR-type ESD protection circuits,\" Solid-State Electronics, vol. 45, pp. 2005-2009, 2001."]}

In this study, an improved Electrostatic Discharge (ESD) protection circuit with low trigger voltage and high holding voltage is proposed. ESD has become a serious problem in the semiconductor process because the semiconductor density has become very high these days. Therefore, much research has been done to prevent ESD. The proposed circuit is a stacked structure of the new unit structure combined by the Zener Triggering (SCR ZTSCR) and the High Holding Voltage SCR (HHVSCR). The simulation results show that the proposed circuit has low trigger voltage and high holding voltage. And the stack technology is applied to adjust the various operating voltage. As the results, the holding voltage is 7.7 V for 2-stack and 10.7 V for 3-stack., {"references":["Albert Z, H. Wang, On-Chip ESD Protection for Integrated devices 2nd ed. Springer, US, 2002.","M.D. Ker and C.C. Yen \"investigation and Design of on-Chip Power-Rail ESD Clamp Circuits without Suffering Latch up-Like Failure during System-Level ESD Test\" IEEE J, Solid-State Circuit, vol. 43, no. 11, pp.2533-2545, 2008.","V. Vashchenko, A. Sinkevitch, V.F., \"Physical Limitaions of Semiconductor Devices, Springer, p.340, 2008","Yong Seo Koo, et. al., \"Design of SCR-based ESD protection device for power clamp using deep-submicron CMOS technology,\" Microelectronics Journal, Vol. 40, pp. 1007-1012, 2009.","Sheng-Lyang Jang, et. al., \"Temperature-dependent dynamic triggering characteristics of SCR-type ESD protection devices,\" Solid-State Electronics, Vol.45, pp. 2005-2009, 2001.","P.-Y Ran, M. Indrajjit, P.-H. Li and S. H. Voldman. \"RC-triggered PNP and NPN Simultaneously Switched Silicon Controlled Rectrifier ESD Networks for Sub-0.18um Technology\" in proc. Of IEEE int. symp. On physical and failure Analysis of Intergrated Circuits, pp. 71-75, 2005","W.Y Chen, et. al., \"Measurement on Snapback Holding voltage of High-Voltage LDMOS for Latch-up Consideration,\" device and system, APCCAS 2008, pp. 61-64, 2008.","J. Y. Lee \"Analysis of SCR, MVSCR, LVTSCR With I-V Characteristic and Turn-On-Time,\" j.inst.Korean.electr.electron.eng, vol. 20, no. 3, pp. 295-398, 2016.","O. Quittard, Z. Mrcarica, F. Blanc, G. Notermans, T. Smedes, and H.van Zwol, \"ESD protection for high-voltage CMOS technologies,\" EOS/ESD Symp, pp. 77-86, 2006.\n[10]\tK. D Kim \"A Study on the Novel SCR Nano ESD Protection Device Design and Fabrication,\" j.inst.Korean.electr.electron.eng, vol. 9, no. 2, pp. 83-91, 2005.\n[11]\tM. D. Ker and H. H. Chang, \"How to safely apply the LVTSCR for CMOS whole-chip ESD protection without being accidentally triggered on,\" J. Electro- statics, vol. 47, pp.215-248, 1999.\n[12]\tY. Koo, K. Lee, K. Kim, and J. Kwon, \"Design of SCR-based ESD protection device for power clamp using deep-submicron CMOS technology,\" Microelectronics Journal, vol. 40, pp. 1007-1012, 2009.\n[13]\tS.-L. Jang, L.-S. Lin, and S.-H. Li, \"Temperature-dependent dynamic trig-gering characteristics of SCR-type ESD protection circuits,\" Solid-State Electronics, vol. 45, pp. 2005-2009, 2001.\n[14]\tV. A. Vashchenko, A. Concannon, M. ter Beek, and P. Hopper \"High Holding Voltage Cascoded LVTSCR Structures for 5.5-V Tolerant ESD Protection Clamps,\" IEEE Transactions on Device and Materials Reliability, vol. 4, no. 2, pp. 273-280, 2004."]}

The excellent area efficiency of dual-directional SCRs (DDSCRs) have made them desirable for low-voltage and high-voltage applications. However, to implement the required symmetrical structure, conventional DDSCRs have to lengthen their ESD discharge path. In addition, the low holding voltage of existing DDSCRs is not suitable for high-voltage applications. In this study, a novel DDSCR with a high holding voltage and low dynamic resistance is proposed and its electrical characteristics are verified. The proposed DDSCR has two additional internal parasitic bipolar transistors compared to a conventional low- triggering voltage DDSCR (LTDDSCR). Self-gate biasing reduces latch-mode feedback between the parasitic bipolar transistors in the SCR. The device is fabricated using 0.13 $\mu {\mathrm{ m}}$ BCD processes and implements a segment layout resulting in a very low dynamic resistance of $2.2~{\Omega }$ and excellent holding voltages of up to 17.2 V. The proposed DDSCR demonstrates improved reliability and area efficiency for 12 V applications.

International audience; A MOS-IGBT-SCR component that was proposed in a previous paper to increase the device robustness and the cost of ESD protection circuit is optimized in this paper. In order to improve its latch up immunity, several variations of geometrical parameters that have been simulated using TCAD Sentaurus Device in another previous paper have been implemented and compared in this paper. The drift area, the form factor, and the proportion of P + sections inserted into the drain are the main parameters, which have a significant impact on the latch up immunity. TLP characterization, and curve tracer measurements have been carried out to evaluate the proposed solution. Holding current increases up to 70 mA and holding voltage up to 10 V. 1 Introduction The electrostatic discharge (ESD) has always been one of the highest reliability concerns in the integrated (IC) manufacturing industry. With the continuous miniaturization process, the integrated circuits become more and more vulnerable to ESD. The miniaturization of the ESD protection blocks is one of the greatest challenges of smart power technologies. Silicon On Insulator (SOI) technologies allow extending the operational temperature range while providing the necessary isolation between components with a reduced silicon area. SOI technology is becoming more and more attractive to manage very high voltage blocks, to reduce parasitic NPN effect and to increase Integrated Circuit (IC) speed as well as for applications operating at high temperature [1], [2]. Electro Static Discharge (ESD) protections occupy a significant silicon IC area. Using a LDMOS as main ESD protection component is not optimal due to its high on-resistance, but it could be the only solution for some technologies. In a previous work, we proposed a new ESD component (MOS-IGBT-SCR) and improved it in order to increase ESD performance and improve the latch up immunity [3] [4]. ESD performance was excellent but margin to prevent latch up was not satisfying. In this paper, an optimized version of this structure is discussed and experimentally validated. As the technological parameters of the used technology (TFSMART1: SOI smart power technology) cannot be changed, we explored various layout-design solutions such as the device topology or the architecture. 2 Structure description and preview solution

In this paper, we proposed a novel SCR (Silicon Controlled Rectifier) - based ESD (Electrostatic Discharge) protection device for I/O and power clamp. The proposed device has a higher holding voltage characteristic than conventional SCR. These characteristics enable to have latch-up immunity under normal operating conditions as well as superior full chip ESD protection. The proposed device was analyzed to figure out electrical characteristics and tolerance robustness in term of individual design parameters (D1, D2, D3). They are investigated by using the Synopsys TCAD simulator. As a result of simulation, holding voltage increased with different design parameters. The holding voltage of the proposed device changes from 3.3V to 7.9V. Also, N-Stack structure ESD device with the high holding voltage is proposed. In the simulation results, 2-stack has holding voltage of 6.8V and 3-stack has holding voltage of 10.5V. The simulation results show that holding voltage of stacking structure can be larger than the operation voltage of high-voltage application., {"references":["Albert Z, H. Wang, On-Chip ESD Protection for Integrated devices 2nd ed.\nSpringer, US, 2002","R.G Wagner, J. Soden and C.F. Hawkins 'Extend and Cost of EOS/ESD\nDamage in an IC Manufacturing Process', in Porc. of the 15th EOS/ESD\nSymp., pp49-55, 1993.","V. Vashchenko, A. Sinkevitch, V.F., \"Physical Limitaions of\nSemiconductor Devices, Springer, p.340, 2008","C. Russ, M. P. J. Mergens, J. Armer, P. Jozwiak, G.Kolluri, L. Avery, and\nK. Vergaegem, \"GGSCR: GGNMOS triggered silicon controlled\nrectifiers for ESD protection in deep submicron CMOS processes,\" in\nProc. EOS/ESD Symp., 2001, pp.22-31.","J. A. Salcedo, J. J. Liou, and J. C. Bernier, \"Novel and robust silicon\ncontrolled rectifier (SCR) based devices fo on-chip ESD protection,\"\nIEEE Electron device Lett., vol. 25, no. 9, pp. 658-660, September 2004.","Markus P. J. Mergens, Christian C. Russ, et al, \" High holding current\nSCRs for ESD protection and latch-up immune IC operation,\"\nMicroelectronics Reliability, vol. 43, pp.993-1000, 2003.","M.D Ker, et al., \"How to safely apply the LVTSCR for CMOS whole-chip\nESD protection without being accidentally triggered on,\" Journal of\nElectro- statics, Vol. 47, pp. 215-248, 1999.","Yong Seo Koo, et al., \"Design of SCR-based ESD protection device for\npower clamp using deep-submicron CMOS technology,\"\nMicroelectronics Journal, Vol. 40, pp. 1007-1012, 2009.","Sheng-Lyang Jang, et al., \"Temperature-dependent dynamic triggering\ncharacteristics of SCR-type ESD protection devices,\" Solid-State\nElectronics, Vol.45, pp. 2005-2009, 2001.\n[10] W.Y Chen, et al., \"Measurement on Snapback Holding voltage of\nHigh-Voltage LDMOS for Latch-up Consideration,\" device and system,\nAPCCAS 2008, pp. 61-64, 2008.\n[11] Yong Seo Koo, \"Electrical characteristics of novel SCR-based ESD\nprotection for power clamp,\" IEICE Electronics Express, vol.9, no.18,"]}

This paper proposed a silicon controller rectifier (SCR) based ESD protection device to protect low voltage ESD for integrated circuit. The proposed ESD protection device has low trigger voltage and high holding voltage compared with conventional SCR-based ESD protection devices. The proposed ESD protection circuit is verified and compared by TCAD simulation. This paper verified effective low voltage ESD characteristics with low trigger voltage of 5.79V and high holding voltage of 3.5V through optimization depending on design variables (D1, D2, D3 and D4)., {"references":["Ming-Dou Ker, Cheng-Cheng Yen: \"Investigation and Design of\nOn-Chip Power-Rail ESD Clamp Circuits Without Suffering\nLatchup-Like Failure During System-Level ESD Test,\" IEEE Journal of\nSolid-State Circuit, vol.43, no.11, pp. 2533-2545, November 2008.","Mergens, Markus P.J: \"ESD Protection Considerations in Advanced\nHigh-Voltage Technologies for Automotive\"Proc. 28thEOS/ESD Symp.,\nWestin La Paloma Tucson, Arizona, USA, pp. 54-63, September 2006.","Yong-Seo Koo, Kwang-Yeob Lee, Kui-Dong Kim, and Jong-ki Kwon:\n\"Design of SCR-based ESD Protection Device for Power Clamp using\nDeep-Submicron CMOS Technology,\"Microelectronics Journal, vol. 40,\nno. 6, pp. 1007-1012, June 2009.","V. Vashchenko, A. Concannon, M. terBeek, and P. Hopper:\"High\nholding voltage cascoded LVTSCR structures for 5.5-V tolerant ESD\nprotection clamps\", IEEE Trans. on Device and Materials Reliability, vol.\n4, no. 2, pp. 273-280, 2004.","Yong-Seo Koo, Kwang-Yeob Lee, Kui-Dong Kim, and Jong-Ki Kwon:\n\"The design of high holding voltage SCR for whole-chip ESD protection\"\nIEICE Electronics Express, vol. 5, no. 17, pp. 624-630, September 2008.","Oleg Semenov, HosseinSarbishaei and ManojSachdev:ESD Protection\nDevice and Circuit Design for Advanced CMOS Technologies, Springer,\n2008."]}

This paper presents a silicon controller rectifier (SCR) based ESD protection circuit for IC. The proposed ESD protection circuit has low trigger voltage and high holding voltage compared with conventional SCR ESD protection circuit. Electrical characteristics of the proposed ESD protection circuit are simulated and analyzed using TCAD simulator. The proposed ESD protection circuit verified effective low voltage ESD characteristics with low trigger voltage and high holding voltage., {"references":["Huang, et al.., \"ESD protection design for advanced CMOS,\" in Proc.\nSPIE, 2001, pp. 123-131.","S. P. Bingulac, \"On the compatibility of adaptive controllers (Published\nConference Proceedings style),\" in Proc. 4th Annu. Allerton Conf.\nCircuits and Systems Theory, New York, 1994, pp. 8–16.","M. -D. Ker; C. -Y. Wu, T. Cheng, M. J. -N. Wu, T. -L. Yu, and A.C.\nWang, \"WholechipESD protection for CMOS VLSI/ULSI with multiple\npower pins,\" Proc. of theInt.Integrated Reliability Workshop, pp.\n124–128, 1994..","C. Russ, M. Mergens, J. Armer, p. jozwiak, G. Kolluri, L. Avery, and K.\nVerhaege, \"GGSCRs: GGNMOS triggered silicon controlled rectifiers\nfor ESD protection in deep submicron CMOS processes,\" in Proc.\nEOS/ESD Symp., 2001, pp.22-31.","M.-D. Ker and K.-C. Hsu, \"overview of on-chip electrostatic discharge\nprotection design with SCR-vased devices in CMOS intergrated circuits,\"\nIEEE Tran. Device Mater. Reliab. Vol. 5, no. 2, Jun 2005, pp.235-249.","P.-Y.Tan, M. Indrajit, p.-H. Li, and S.H.Voldman, \"Rc-triggered PNP and\nNPN simultaneously switched silicon controlled rectifier ESD networks\nfor sub-0.18um technology,\" in Proc. Of IEEE Int. Symp. On Physical\nand Failure Analysis of Integrated Circuits, 2005, pp. 71-75.","M. D. Ker and K. C. Hsu, \"Latchup-free ESD protection design with\ncomplementary substrate-triggered SCR devices,\" IEEE J. Solid State\nCir., vol. 38, No. 8, pp. 1380-1392,2003","M. –D. Ker and W. –Y. Lo, \"Design on the low-leakage diode string for\nusing in the power-rail ESD clmp circuits in a 0.35-μm silicide CMOS\nprocess,\" IEEE J. of Solid-State Cir., vol. 35, No. 4, pp. 601-11,2000"]}