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Tunnel FETs (TFETs) have been identified as the most promising steep slope devices for ultralow power logic circuits. In this paper, we demonstrate in-plane InAs/Si TFETs monolithically integrated on Si, using our recently developed template-assisted selective epitaxy approach. These devices represent some of the most scaled TFETs with dimensions of less than 30 nm, combined with excellent aggregate performance with average subthreshold swing (SS), of around 70 mV/decade combined with $I_{\mathrm{\scriptscriptstyle ON}}$ of a few $\mu \text{A}$ / $\mu \text{m}$ for $|V_{\mathrm {\mathbf {DS}}}| = |V_{\mathrm {\mathbf {GS}}}| = 0.5$ V. Here, we will discuss the device fabrication as well as the experimental electrical data. Extensive low temperature characterization and activation energy analysis is used to gain insights into the factors limiting device performance. Combined with the simulation study presented in part 2 of this paper, this will elucidate how traps are ultimately limiting the SS.

This part of the paper presents TCAD simulations of the InAs/Si lateral nanowire (NW) tunnel FET (TFET) with the same geometry as the fabricated device discussed in the first part. In addition to band-to-band tunneling, trap-assisted tunneling (TAT) at the InAs/Si and InAs/oxide interfaces was considered. A very good agreement is found between the simulation results and experimental transfer characteristics of different devices. The simulations confirm that the transfer characteristics in the subthreshold regime of the TFETs are entirely dominated by TAT. Due to the high concentration of generation centers at the InAs/Si interface, the current conduction in the subthreshold regime takes place in two steps: carrier generation by TAT at the InAs/Si interface followed by thermionic emission over the hole barrier. The latter is the limiting process, and hence dominant for the subthreshold swing (SS), preventing a value smaller than 60mV/decade. In addition, traps at the Si/oxide interface reduce the electrostatic coupling between the gate and the channel, which further degrades the SS. Predictive simulations with varying interface trap densities indicate that a subthermal SS would only be achievable for $D_{\mathrm{ it}} cm $^{-2}$ eV $^{-1}$ at both InAs/Si and InAs/oxide interfaces. This confirms a recently found minimum requirement of $D_{\mathrm{ it}} cm $^{-2}$ eV $^{-1}$ for vertical InAs/Si NW TFETs with larger diameters.

Metastable wurtzite crystal phases of semiconductors comprise enormous potential for high-performance electro-optical devices, owed to their extended tunable direct band gap range. However, synthesizing these materials in good quality and beyond nanowire size constraints has remained elusive. In this work, the epitaxy of wurtzite InP microdisks and related geometries on insulator for optical applications is explored. This is achieved by an elaborate combination of selective area growth of fins and a zipper-induced epitaxial lateral overgrowth, which enables co-integration of diversely shaped crystals at precise position. The grown material possesses high phase purity and excellent optical quality characterized by STEM and $\mu$-PL. Optically pumped lasing at room temperature is achieved in microdisks with a lasing threshold of 365 $\mu J/cm^2$, thus demonstrating promise for a wide range of photonic applications., Comment: 8 pages, 4 figures

We present a low-temperature electrical transport study on four-terminal ballistic InAs nanowire cross-junctions in magnetic fields aligned perpendicular to the cross-plane. Two-terminal longitudinal conductance measurements between opposing contact terminals reveal typical 1D conductance quantization at zero magnetic field. As the magnetic field is applied, the 1D bands evolve into hybrid magneto-electric sub-levels that eventually transform into Landau levels for the widest nanowire devices investigated (width = 100 nm). Hall measurements in a four-terminal configuration on these devices show plateaus in the transverse Hall resistance at high magnetic fields that scale with (ve 2/h)−1. e is the elementary charge, h denotes Planck's constant and v is an integer that coincides with the Landau level index determined from the longitudinal conductance measurements. While the 1D conductance quantization in zero magnetic field is fragile against disorder at the NW surface, the plateaus in the Hall resistance at high fields remain robust as expected for a topologically protected Quantum Hall phase. (Less)

We demonstrate a growth approach that enables connecting III-V nanowires ―with precise control of shape, position and size by standard Si nanofabrication techniques― to a bottom silicon solar cell for the next generation of photovoltaics.

InGaAs is a potential candidate for Si replacement in upcoming advanced technological nodes because of its excellent electron transport properties and relatively low interface defect density in dielectric gate stacks. Therefore, integrating InGaAs devices with the established Si platforms is highly important. Using template-assisted selective epitaxy (TASE), InGaAs nanowires can be monolithically integrated with high crystal quality, although the mechanisms of group III incorporation in this ternary material have not been thoroughly investigated. Here we present a detailed study of the compositional variations of InGaAs nanostructures epitaxially grown on Si(111) and Silicon-on-insulator substrates by TASE. We present a combination of XRD data and detailed EELS maps and find that the final Ga/In chemical composition depends strongly on both growth parameters and the growth facet type, leading to complex compositional sub-structures throughout the crystals. We can further conclude that the composition is governed by the facet-dependent chemical reaction rates at low temperature and low V/III ratio, while at higher temperature and V/III ratio, the incorporation is transport limited. In this case we see indications that the transport is a competition between Knudsen flow and surface diffusion.

We report InGaAs gate-all-around nanosheet NFETs on Si substrate using template-assisted-selective-epitaxy (TASE) and a gate-last process with thermal budget advantages. Compared to our early report of the TASE process, in this paper we demonstrate that TASE can be scaled to a channel thickness of ∼10 nm, which enables short gate devices without significant leakage. The defects and composition of the fabricated nanosheet FETs are also investigated. Enabled by this VLSI compatible process and a novel high-pressure deuterium annealing process, our 39 nm- $L_{g}$ device shows a peak $g_{m}$ of $1.37 \ \text{mS}/\mu \mathrm{m}$ , a subthreshold slope in saturation of 72 mV/decade, and an $I_{on}$ of $355 \ \mu \mathrm{A}/\mu \mathrm{m}$ at 0.5 V $V_{gs}$ , the highest among reported sub-50 nm- $L_{g}$ III-V FETs on Si.

Recent research on nanowires (NWs) demonstrated the ability of III–V semiconductors to adopt a different crystallographic phase when they are grown as nanostructures, giving rise to a novel class of materials with unique properties. Controlling the crystal structure however remains difficult and the geometrical constraints of NWs cause integration challenges for advanced devices. Here, we report for the first time on the phase-controlled growth of micron-sized planar InP films by selecting confined growth planes during template-assisted selective epitaxy. We demonstrate this by varying the orientation of predefined templates, which results in concurrent formation of zinc-blende (ZB) and wurtzite (WZ) material exhibiting phase purities of 100% and 97%, respectively. Optical characterization revealed a 70 meV higher band gap and a 2.5× lower lifetime for WZ InP in comparison to its natural ZB phase. Further, a model for the transition of the crystal structure is presented based on the observed growth facets and the bonding configuration of InP surfaces.

Today, silicon is the most used material in photovoltaics, with the maximum conversion efficiency getting very close to the Shockley-Queisser limit for single-junction devices. Integrating silicon with higher band-gap ternary III-V absorbers is the path to increase the conversion efficiency. Here, we report on the first monolithic integration of Ga

As we increasingly move beyond conventional silicon CMOS towards more hybrid technology platforms there is a rising interest in integrating other materials on the Si substrate. Co-integrated III-V materials could strongly enhance electronic properties by providing increased electron mobility or tunable heterostructures or add additional functionality for silicon photonics via integrated direct bandgap materials [1], [2]. We have developed a method for monolithic III-V integration on Si, where we grow III-V material within lithographically defined oxide cavities [3]–[7]. This provides us with a high degree of control and versatility, while eliminating some of the constraints associated with either buffer layers or traditional selective area growth of nanowires. As shown in Fig. 1 this method has been employed to demonstrate various electronic devices ranging from high performance InGaAs nFET [7], ballistic transport in nanowires [8] to complementary III-V heterostructure Tunnel FETs (TFETs) where we have demonstrated a scalable platform for complementary TFETs [9], [10]. Recently we have also expanded this technology to optically active devices, enabling monolithically integrated micro-cavity GaAs [11], [12] and InGaAs lasers [13].

The tunnel field-effect transistor (TFET) is regarded as one of the most promising solid-state switches to overcome the power dissipation challenge in ultra-low power integrated circuits. TFETs take advantage of quantum mechanical tunneling hence exploit a different current control mechanism compared to standard MOSFETs. In this review, we describe state-of-the-art development of TFET both in terms of performances and of materials integration and we identify the main remaining technological challenges such as heterojunction defects and oxide/channel interface traps causing trap-assisted-tunneling (TAT). Mesa-structures, planar as well as vertical geometries are examined. Conductance slope analysis on InAs/GaSb nanowire tunnel diodes are reported, these two-terminal measurements can be relevant to investigate the tunneling behavior. A special focus is dedicated to III-V heterostructure TFET, as different groups have recently shown encouraging results achieving the predicted sub-thermionic low-voltage operation.

The development of photovoltaics as a serious means of producing renewable energy has accelerated greatly in the last ten years, with prices for silicon-based solar cell systems dropping dramatically in the last few years. The next great opportunity for photovoltaics following this competitiveness in prices will be to enhance the cell and panel efficiencies. It is quite generally seen that the most viable platform on which this should be realized will be as augmented silicon solar cells, in which a top cell will be combined with the silicon bottom cell in a tandem configuration, by which the efficiency can be enhanced by a factor from 20% to 50%, depending on details of the approach. In this paper, we report on the status of one such approach, namely, with a top cell comprising III-V nanowires, connected to the bottom silicon cell in a two-terminal or four-terminal configuration. Among the most important opportunities, we show that a substrate-free growth, called Aerotaxy, offers a radical reduction in the total price picture. Besides the description of the key technical approaches, we also discuss the environmental issues.

In this paper, we introduce ${p}$ -channel InAs-Si tunnel field-effect transistors (TFETs) fabricated using selective epitaxy in nanotube templates. We demonstrate the versatility of this approach, which enables III–V nanowire integration on Si substrates of any crystalline orientation. Electrical characterization of diodes and of TFETs fabricated using this method is presented; the TFETs exhibit a good overall performance with on-currents, ${I} _{\rm on}$ of 6 $\mu $ A/ $\mu $ m ( $|V_{GS}| = |V_{DS}| = 1$ V) and a room-temperature subthreshold swing ( SS ) of $\sim 160$ mV/dec over at least three orders of magnitude in current. Temperature-dependent measurements indicate that SS is limited by traps. We demonstrate improved TFET ${I} _{\rm on}$ performance by 1–2 orders of magnitude by scaling the equivalent oxide thickness from 2.7 to 1.5 nm. Furthermore, a novel benchmarking scheme is proposed to allow the comparison of different TFET data found in literature despite the different measurement conditions used.

Due to their high mobility and direct band gap, III-V materials promise good prospects of obtaining novel, high-performance devices for electronic and photonic applications. In this paper, two variants of the established Template Assisted Selective Epitaxy (TASE) technique [2]–[4] are explored to study the structural quality of GaAs and InGaAs microcavities monolithically integrated on Si (001). The first variant involves a one-step direct cavity growth (DCG), while the second relies on a two-step virtual substrate (VS) growth approach. The cavities obtained were investigated by Scanning Transmission Electron Microscopy (STEM) and Energy Dispersive X-Ray Spectroscopy (EDX); the findings have been correlated with the photoluminescence properties of the cavities. Both approaches enable monolithic integration of GaAs crystalline material in predefined oxide microcavities. In some cases, they allow the III-V materials to be grown as a single gain and do not lead to noticeable structural defects. InGaAs disks and ring cavities grown using the VS approach have also been investigated. Despite the presence of planar defects and rough surfaces, lasing could be achieved at low temperature.

Additional functionalities on semiconductor microchips are progressively important in order to keep up with the ever-increasing demand for more powerful computational systems. Monolithic III-V integration on Si promises to merge mature Si CMOS processing technology with III-V semiconductors possessing superior material properties, e. g., in terms of carrier mobility or band structure (direct band gap). In particular, Si photonics would strongly benefit from an integration scheme for active III-V optoelectronic devices in order to enable low-cost and power-efficient electronic-photonic integrated circuits. We report on room-temperature lasing from AlGaAs/GaAs microdisk cavities monolithically integrated on Si(001) using a selective epitaxial growth technique called template-assisted selective epitaxy. The grown gain material possesses high optical quality without indication of threading dislocations, antiphase boundaries, or twin defects. The devices exhibit single-mode lasing at T250 K and lasing thresholds between 2 and 18 pJ/pulse depending on the cavity size (1-3 μm in diameter).

We have recently developed a novel III-V integration scheme, where III-V material is grown directly on top of Si within oxide nanotubes or microcavities which control the geometry of nanostructures. This allows us to grow III-V material non-lattice matched on any crystalline orientation of Si, to grow arbitrary shapes as well as abrupt heterojunctions, and to gain more flexibility in tuning of composition. In this talk, applications for electronic devices such as heterojunction tunnel FETs and microcavity III-V lasers monolithically integrated on Si will be discussed along with an outlook for the future.

Tunnel diodes are of interest to gain insights into the limitations of tunnel field effect transistors (TFETs) as they enable us to distinguish effects of the heterojunction from device parasitics found in a three terminal device. In the present work, we report on InAs/GaSb nanowire heterojunction tunnel diodes monolithically integrated on silicon-on-insulator substrate (SOI). The nanowires were grown using template-assisted selective epitaxy (TASE). Temperature dependent I–V measurements show a change in the conductance slope due to the presence of defects at the heterojunction. Comparison with TFETs results shows a similar temperature dependence of the slope, but with smaller absolute values. We further performed room temperature pulsed I–V measurements on the same diodes to analyze trap contributions and we observed no significant dependence on pulse time down to 10µs.

The transition of the conventional energy supply scheme, typically characterized by integration of more small-scale renewable sources and reduction of greenhouse gas emissions, is an inevitable trend. At the same time, efficient operation of the existing distribution system, which hosts these decentralized generators, is equally important toward achieving a sustainable energy system. In order to keep track of the upcoming changes regarding system efficiency, an accurate determination of grid losses in the distribution system is the fundamental step. However, to evaluate the energy losses of power distribution grids at large scales is a difficult task. Currently, distribution system operators only have limited options for determining grid losses, especially in the low voltage sector. The growing installation rate and the fluctuating nature of distributed generations pose further difficulties and uncertainties for the loss evaluations. For this reason, a comprehensive and accurate evaluation on grid losses, which takes the grid information, the available metering data and the installed distributed generations into account, is highly relevant. In this work, a novel evaluation framework for energy losses for low voltage distribution grids is presented. Our evaluation framework consists of three building blocks: a fully automatic and parallelized generation of grid models, the determination of grid losses based on annual power flow simulations as well as a data-driven reference grid modeling method. We demonstrate and validate this framework based on a data-set of 5000 real distribution grids (including about 31,000 low voltage feeders), located in the service area of one of the largest German distribution system operators. The key contribution of the proposed framework is the automatic approach for grid modeling and feature evaluation at large scales and the implementation of the advanced, comprehensive reference grid modeling method for evaluating relevant grid features and estimating grid losses. This novel reference grid modeling approach and the complete framework are further validated by comparison with both exhaustive simulation results of grid losses and three state-of-the-art regression schemes. Among the case studies, this proposed evaluation framework shows a very good performance in the evaluation of grid losses. Moreover, this evaluation framework provides useful insights concerning the allocation of energy losses as well as the impact of distributed generations on grid losses. Accordingly, this novel evaluation framework gives distribution system operators a powerful tool considering the evaluation and improvement of system efficiency.

International audience; We report the analysis of the electrical properties of In x-1 Ga x P nanowires (NWs) grown by template-assisted selective epitaxy (TASE). The individual NW properties are investigated by means of electron beam induced current microscopy (EBIC) and current-voltage curves acquired on single nano-objects. First, a set of samples containing n-doped InGaP NWs grown on a p-doped Si substrate are investigated. The electrical activity of the hetero-junction between the NWs and the substrate is demonstrated and the material parameters are analyzed, namely the n-doping level is determined in relation with the dopant flow used during the growth. These results were used to design and elaborate InGaP NWs containing a p-n homo-junction. The electrical activity of the homo-junction is evidenced using EBIC mapping on single NWs and material parameters (namely, the doping and the minority carrier diffusion lengths) for the p-and n-doped InGaP segments are estimated. Finally, the first proof of a photovoltaic effect from the NW homo-junctions is obtained by photocurrent measurements of a contacted NW array under white light irradiation.

Coherent interconnection of quantum bits remains an ongoing challenge in quantum information technology. Envisioned hardware to achieve this goal is based on semiconductor nanowire (NW) circuits, comprising individual NW devices that are linked through ballistic interconnects. However, maintaining the sensitive ballistic conduction and confinement conditions across NW intersections is a nontrivial problem. Here, we go beyond the characterization of a single NW device and demonstrate ballistic one-dimensional (1D) quantum transport in InAs NW cross-junctions, monolithically integrated on Si. Characteristic 1D conductance plateaus are resolved in field-effect measurements across up to four NW-junctions in series. The 1D ballistic transport and sub-band splitting is preserved for both crossing-directions. We show that the 1D modes of a single injection terminal can be distributed into multiple NW branches. We believe that NW cross-junctions are well-suited as cross-directional communication links for the reliable transfer of quantum information as required for quantum computational systems.

We have measured the thermopower and the thermal conductivity of individual silicon and indium arsenide nanowires (NWs). In this study, we evaluate a self-heating method to determine the thermal conductivity λ. Experimental validation of this method was performed on highly n-doped Si NWs with diameters ranging from 20 nm to 80 nm. The Si NWs exhibited electrical resistivity of \(\rho = (8\pm4)\, \hbox{m}\Upomega\,\hbox{cm}\) at room temperature and Seebeck coefficient of −(250 ± 100) μV/K. The thermal conductivity of Si NWs measured using the proposed method is very similar to previously reported values; e.g., for Si NWs with 50 nm diameter, λ = 23 W/(m K) was obtained. Using the same method, we investigated InAs NWs with diameter of 100 nm and resistivities of \(\rho = (25\pm5)\, \hbox{m}\Upomega\,\hbox{cm}\) at room temperature. Thermal conductivity of λ = 1.8 W/(m K) was obtained, which is about 20 to 30 times smaller than in bulk InAs. We analyzed the accuracy of the self-heating method by means of analytical and numerical solution of the one-dimensional (1-D) heat diffusion equation taking various loss channels into account. For our NWs suspended from the substrate with low-impedance contacts the relative error can be estimated to be ≤25%.

In this paper we report on our work on the monolithic integration of various III-V compounds on Si using template-assisted selective epitaxy (TASE) and its application for electronic devices. Nanowires, crossbar nanostructures, and micron-sized sheets are epitaxially grown on Si via metal-organic chemical vapor deposition and form the basis for III-V MOSFETs and Tunnel FETs. Epitaxy conditions specific to TASE are discussed and material quality assessed. Here, we focus on InAs and GaSb as a potential all-III-V alternative to complementary group IV technology. Scaled n-FETs as well as both n- and p-channel TFETs are fabricated on Si and illustrate the potential of TASE.

In this presentation we will discuss our recent progress on the integration of InAs/Si p-tunnel FETs (TFETs) and InAs/GaSb n-TFETs on SOI wafers. Local III-V growth is enabled by the development of Template-Assisted Selective Epitaxy (TASE) [1-4]. Both polarity devices have scaled geometries with cross-sections on the order of 30nm. The p-channel InAs/Si TFETs are developed based on our previously demonstrated vertical devices, which are now implemented horizontally in-plane on the Si wafer. The InAs/Si TFETs show excellent performance with Ion of about 4μA/μm at Vgs = Vds = −0.5V, combined with average subthreshold swings (SS) of 70–80mV/dec. The SS is limited by trap mechanisms at the heterojunction, which will also be discussed. The InAs/GaSb n-TFETs represent our first devices in this material system, with doping levels and gate stack not yet optimized; the all III-V TFETs show about an order of magnitude greater current levels, but at a worse SS.

Electrical transport and thermoelectric properties of thin indium arsenide nanowires have been investigated in the temperature range between 100 K and 365 K. Charge carrier concentration was varied by a back-gate electrode. In nanowires with a diameter of 20 nm, discrete conductance plateaus are observed at low temperature indicating one-dimensional quantization of the density of states. A mean free path of 135 nm is extracted. At room temperature, the one-dimensional nature leads to drastically enhanced thermoelectric properties. A 100 % increase of the thermoelectric power factor σS2 (calculated from the electrical conductivity σ and the Seebeck coefficient S) is obtained in the nanowires compared to bulk InAs bulk material.

In the present work we will show our complementary TFET technology, which allows for the co-planar integration of InAs/Si p-TFETs and InAs/GaSb n-TFETs. We demonstrate both types of devices, show the results of the electrical characterization at room temperature and down to 125K. The p-TFETs exhibit excellent performance with I on of a couple of µA/µm (|V GS | = |V DS | = 0.5V) combined with average subthreshold swing, SS, of 70–80mV/dec. The all III–V n-TFETs show about an order of magnitude higher I on , but their SS is limited by the non-optimized gate stack and doping profiles. Thorough simulation studies of our devices show trap-assisted tunneling at the heterojunction to be the main limitation on SS. We will discuss the impact of different trap mechanisms and compare our results with other experimental data.

We demonstrate for the first time a technology which allows the monolithic integration of both p-type (InAs-Si) and n-type (InAs-GaSb) heterojunction Tunnel FETs (TFET) laterally on a Si substrate. The lateral heterojunction nanowire (NW) structures are implemented using top-down CMOS-compatible processes combined with Template-Assisted Selective Epitaxy (TASE) [1] of the III–V materials. Sub-40nm InAs-Si p-TFETs and InAs-GaSb n-TFETs have been fabricated and represent to the best of our knowledge the first lateral III–V heterostructure NW TFETs. The InAs-Si p-TFETs show excellent performance with average subthreshold swing, SS ave , of ∼70mV/dec. combined with an on-current, I on , of 4µA/µm at V DS = V GS = −0.5V. The InAs-GaSb n-TFETs have about an order of magnitude higher I on , but SS is deteriorated due to high interface traps density (D it ).

In this talk we will discuss fabrication and device aspects of IBMs work on III–V Tunnel FETs. Since our focus is on the monolithic integration of III–V on Si, we will show our recently developed Template Assisted Selective Epitaxy (TASE) technology and its application to both TFETs as well as other electronic devices. In TASE, III–V materials can be grown within templates, which allows for versatility in materials choice and freedom in growth parameters and is ideally suited for the heterojunction devices required for tunnel FETs. Generally, reducing traps at the heterojunction and at the interface is a great challenge for tunnel FETs, thus we will also discuss the impact of the different trap mechanisms in our devices.

We report on the influence of doping on the band-edge abruptness of InAs/GaSb p-n and p-i-n tunnel diodes. Understanding and fabrication of a well-defined and sharp band edge is mandatory for tunnel FET operation. InAs/GaSb nanowire junctions were selectively grown by metal organic chemical vapor deposition (MOCVD) on silicon-on-insulator (SOI) substrates using template assisted selective epitaxy (TASE) [1]. The junctions were analyzed by scanning transmission electron microscope (STEM) showing an abrupt interface. Current-voltage measurements and conductance slope (S) analysis [2] were conducted at various temperatures. We find that (S) of tunnel diodes exhibits a temperature dependence due to trapping and de-trapping of carriers at the junction and, importantly, that high doping of p-n junctions results in steeper slopes compared to p-i-n diodes. This finding suggests that electronic states from doping impurities play a minor role in S degradation. The presence of doping independent traps at the hetero-interface still results in > 60mV/dec steepness which needs continuous investigations for subthermal device operation of tunnel FETs.

Here we investigate the growth of InAs nanowires on 〈111〉 Si substrates masked by SiO x using metal–organic chemical vapor deposition. We study 〈111〉 (axial) and 〈1−10〉 (radial) growth of InAs NWs by varying growth duration, temperature, group-III molar flows, V/III ratio, mask material, mask opening size, and inter-wire distance. We find that growth takes place without an In droplet and the process evolves through three successive phases: nucleation of an InAs cluster, followed by two distinct nanowire growth phases. These two growth phases have different axial and radial growth rates, which originate in a transition from having In supply dominated by the open Si area in the first phase towards an In supply from the vapor/oxide mask in the second growth phase. The linear relation found between nanowire length and diameter vs. time in the last growth phase indicates that 〈111〉 growth is not surface diffusion limited as is usually the case for catalyzed growth. A high yield of vertical nanowires is obtained if group-III flow is above and V/III ratio below threshold values, in addition to having an arsenic-terminated Si surface. Furthermore, we observe that 〈111〉 and 〈1−10〉 growth is surface kinetically limited below 520 °C and 540 °C, respectively, with activation energies of 20 and 6.5 kcal/mol. This difference in activation energies limits the selectivity of the 〈111〉 to 〈1−10〉 growth to 25:1 under optimized conditions, which must be considered when fabricating axially modulated structures. However, we find that by placing wires in large arrays it is possible to completely stop the 〈1−10〉 growth rate in favor of the 〈111〉 growth rate.

We report on the fabrication and characterization of silicon nanowire tunnel diodes. The silicon nanowires were grown on p-type Si substrates using Au-catalyzed vapor-liquid-solid growth and in situ n-type doping. Electrical measurements reveal Esaki diode characteristics with peak current densities of 3.6 kA/cm(2), peak-to-valley current ratios of up to 4.3, and reverse current densities of up to 300 kA/cm(2) at 0.5 V reverse bias. Strain-dependent current-voltage (I-V) measurements exhibit a decrease of the peak tunnel current with uniaxial tensile stress and an increase of 48% for 1.3 GPa compressive stress along the111growth direction, revealing the strain dependence of the Si band structure and thus the tunnel barrier. The contributions of phonons to the indirect tunneling process were probed by conductance measurements at 4.2 K. These measurements show phonon peaks at energies corresponding to the transverse acoustical and transverse optical phonons. In addition, the low-temperature conductance measurements were extended to higher biases to identify potential impurity states in the band gap. The results demonstrate that the most likely impurity, namely, Au from the catalyst particle, is not detectable, a finding that is also supported by the excellent device properties of the Esaki diodes reported here.

In this paper, we demonstrate p-channel tunnel FETs based on silicon nanowires grown with an in situ p-i-n doping profile. The tunnel FETs were fabricated with three different gate dielectrics, SiO2, Al2O3, and HfO2, and show a performance enhancement when using high-k dielectric materials. The best performance is achieved for the devices using HfO2 as the gate dielectric, which reach an Ion of 0.1 μA/μm (VDS = -0.5 V, VGS = -2 V), combined with an average inverse subthreshold slope (SS) of ~ 120 mV/dec and an Ion/Ioff ratio of around 106. For the tunnel FETs with Al2O3 as the gate dielectric, different annealing steps were evaluated, and an activation anneal at only 700°C was found to yield the best results. Furthermore, we also investigated the temperature behavior of the tunnel FETs. Ideal tunnel FET behavior was observed for devices having ohmic Ni/Au contacts, and we demonstrate the invariance of both the SS and on-current with temperature, as expected for true tunnel FETs.

Conventional scaling is hampered by the inability to further reduce operating voltages. The main reason for this is the limitation on the subthreshold swing of a MOSFET which determines the abruptness of the on-off transition. This is an inherent limitation of the MOSFET device physics and cannot be remedied by the introduction of novel materials or architectures, but remains an underlying physical limitation. A number of devices have been proposed to overcome this limitation, of those, the most promising in a CMOS setting remains the tunnel FET (TFET). Within the past decade, initial euphoria regarding TFET properties were replaced by more realistic hopes as more thorough simulations brought a deeper understanding of device limitations and opportunities. In this respect it became clear that careful device design and a stringent control of defects is required to realize the promise of TFETs experimentally. Very recently experimental tunnel FETs showing sub-thermionic swing over a significant current range were demonstrated, showing that it is possible to beat CMOS performance. However, technologically heterojunction TFETs are much more complex than a silicon MOSFET. Our focus has been on dense monolithic integration of complementary III-V heterojunction TFETs on silicon, which may eventually evolve into a hybrid technology platform. In this talk we will give a general overview of the development of TFETs, discuss the challenges and opportunities both at the individual device level as well as in terms of technology development.

This paper discusses the electronic transport properties of nanowire field-effect transistors (NW-FETs). Four different device concepts are studied in detail: Schottky-barrier NW-FETs with metallic source and drain contacts, conventional-type NW-FETs with doped NW segments as source and drain electrodes, and, finally, two new concepts that enable steep turn-on characteristics, namely, NW impact ionization FETs and tunnel NW-FETs. As it turns out, NW-FETs are, to a large extent, determined by the device geometry, the dimensionality of the electronic transport, and the way of making contacts to the NW. Analytical as well as simulation results are compared with experimental data to explain the various factors impacting the electronic transport in NW-FETs.

Imaging temperature fields at the nanoscale is a central challenge in various areas of science and technology. Nanoscopic hotspots, such as those observed in integrated circuits or plasmonic nanostructures, can be used to modify the local properties of matter, govern physical processes, activate chemical reactions and trigger biological mechanisms in living organisms. The development of high-resolution thermometry techniques is essential for understanding local thermal non-equilibrium processes during the operation of numerous nanoscale devices. Here we present a technique to map temperature fields using a scanning thermal microscope. Our method permits the elimination of tip–sample contact-related artefacts, a major hurdle that so far has limited the use of scanning probe microscopy for nanoscale thermometry. We map local Peltier effects at the metal–semiconductor contacts to an indium arsenide nanowire and self-heating of a metal interconnect with 7 mK and sub-10 nm spatial temperature resolution., Nature Communications, 7, ISSN:2041-1723

A wide variety of methods are now available for the synthesis of colloidal particle having controlled shapes, structures, and dimensions. One of the main challenges in the development of devices that utilize micro- and nanoparticles is still particle placement and integration on surfaces. Required are engineering approaches to control the assembly of these building blocks at accurate positions and at high yield. Here, we investigate two complementary methods to create particle assemblies ranging from full layers to sparse arrays of single particles starting from colloidal suspensions of gold and polystyrene particles. Convective assembly was performed on hydrophilic substrates to create crystalline mono- or multilayers using the convective flow of nanoparticles induced by the evaporation of solvent at the three-phase contact line of a solution. On hydrophobic surfaces, capillary assembly was investigated to create sparse arrays and complex three-dimensional structures using capillary forces to trap and organize particles in the recessed regions of a template. In both methods, the hydrodynamic drag exerted on the particle in the suspension plays a key role in the assembly process. We demonstrate for the first time that the velocity and direction of particles in the suspension can be controlled to perform assembly or disassembly of particles. This is achieved by setting the temperature of the colloidal suspension above or below the dew point. The influence of other parameters, such as substrate velocity, wetting properties, and pattern geometry, is also investigated. For the particular case of capillary assembly, we propose a mechanism that takes into account the relative influences of these parameters on the motion of particles and that describes the influence of temperature on the assembly efficiency.

Bulk syntheses of colloids efficiently produce nanoparticles with unique and useful properties. Their integration onto surfaces is a prerequisite for exploiting these properties in practice. Ideally, the integration would be compatible with a variety of surfaces and particles, while also enabling the fabrication of large areas and arbitrarily high-accuracy patterns. Whereas printing routinely meets these demands at larger length scales, we have developed a novel printing process that enables positioning of sub-100-nm particles individually with high placement accuracy. A colloidal suspension is inked directly onto printing plates, whose wetting properties and geometry ensure that the nanoparticles only fill predefined topographical features. The dry particle assembly is subsequently printed from the plate onto plain substrates through tailored adhesion. We demonstrate that the process can create a variety of particle arrangements including lines, arrays and bitmaps, while preserving the catalytic and optical activity of the individual nanoparticles.

High mobility (III–V) materials have long been anticipated to replace Si MOSFETs. But only recently [1] were scaled InAs MOSFETs reported to outperform Si devices. However, high-performing III–V devices are typically fabricated on InP substrates which are not compatible with large-scale chip manufacturing. While various III–V on Si fabrication approaches have been reported to overcome this issue, they either suffer from limited material quality or are economically not competitive compared to Si substrates. Here we demonstrate a versatile approach for heterogeneous integration of III–Vs on Si and validate this by the fabrication of multiple-gate (MuG)-FET devices. The study is complemented by performing TEM analysis, TLM and Hall measurements.

This review is an account of our efforts to develop a versatile and flexible microfluidic technology for surface-processing applications and miniaturizing biological assays. The review is presented in the context of current trends in microfluidic technology and addresses some of the major challenges for confining chemical and biochemical processes on surfaces: the sealing of a microchannel with a surface, the world-to-chip interface, the displacement of liquids in small conduits, the sequential delivery of multiple solutions, the accurate patterning of surfaces, the coincident detection of various analytes, and the detection of analytes in a small and dilute sample. Our solutions to these problems include the use of reversible sealing, capillary phenomena for powering and controlling liquid transport, and non-contact microfluidics for spotting and drawing (on surfaces) with flow conditions. These solutions offer many advantages over conventional techniques for handling minute amounts of liquids and may find applications in lithography, biopatterning (e.g., the patterning of biomolecules), diagnostics, drug discovery, and also cellular assays.