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Impact ionization and velocity overshoot in the base-collector junction of bipolar transistors are studied using Monte Carlo simulation and the hydrodynamic energy-balance equation. For advanced bipolar transistors, the carrier energy lags the electric field; therefore, the maximum impact ionization rate occurs deep into the junction. A simplified solution of the energy-balance equation can accurately model this nonlocal behavior. Excellent agreement with measurements of the multiplication factor for a variety of base-collector profiles is obtained. As a consequence of this nonequilibrium effect, velocity overshoot is expected and its trade-off with breakdown is analyzed in detail. >

This paper presents an analytical model for depletion-mode m.o.s. transistors which is particularly suitable for c.a.d. applications, and improves the current state of the art by including the effect of the surface-mobility degradation induced by the transverse field. The model is used to fit experimental data obtained on long-channel devices, and turns out to give good results; the mean square error over the whole ID/VDS plane, for several values of the gate- and bulk-source voltages, is of the order of 1%

The Schroedinger equation, or the coupled Schroedinger and Poisson equations, are transformed into an integral equation. Back-substituting from the original equations allows one to approximate the numerical corrections to any order without the need of calculating derivatives of the unknown function of order larger than one. Typical applications are in the numerical analysis of quantum transport in nanowires and nanotubes in the ballistic regime.

We study a possible circuit solution to overcome the problem of low voltage gain of short-channel graphene FETs. The circuit consists of a fully differential amplifier with a load made of a cross-coupled transistor pair. Starting from the device characteristics obtained from self-consistent ballistic quantum transport simulations, we explore the circuit parameter space and evaluate the amplifier performance in terms of dc voltage gain and voltage gain bandwidth. We show that the dc gain can be effectively improved by the negative differential resistance provided by the cross-coupled pair. Contact resistance is the main obstacle to achieving gain bandwidth products in the terahertz range. Limitations of the proposed amplifier are identified with its poor linearity and relatively large Miller capacitance., Comment: 19 pages, 10 figures

A scalable Dual n/p-LDMOS device with interesting Rsp versus Vbd performance for voltage applications in the range of 20–120 V is identified through proper optimization. Three designs have been proposed, based on different process implementations. The physical behavior of the device is reviewed and analyzed. The current expansion induced by the bipolar conductance in the drift region at high gate and drain biases is fully explained. The thermal behavior in a worst case condition is investigated, and the reduction in performance in terms of current and safe-operating area are reported. The switching performance is addressed, showing very good transient times in any analyzed load condition.

Degradation induced by hot-carrier stress (HCS) in a Multi-STI-Finger (MF) LDMOS is analyzed through both electrical measurements and TCAD simulations. The critical HCS issues have been first addressed on a conventional STI-based LDMOS. Then, the detrimental effect of extended Si/SiO2 interfaces along the silicon fingers in the MF-LDMOS has been widely investigated with particular focus on its dependence on biases, ambient temperature, and layout variations. Experimental results are analyzed and discussed on the basis of numerical simulations. The application of a time-dependent HCS degradation model is successfully proved for the first time on the conventional and MF-LDMOS devices at different stress biases and ambient temperatures.

A physics-based analytical model for the on-resistance in the linear transport regime and its application as an alternative tool for the investigation of the hot-carrier stress degradation in shallow-trench-isolation-based laterally diffused MOS devices are presented. The extraction of the model and its validation by comparison with experimental and TCAD data are reported. A thorough investigation of the degradation under low- and high-gate stress biases, corresponding to saturation and impact-ionization regimes, is carried out to gain an insight on the overall bias and temperature dependences of the parameter drifts.

In this paper we perform a simulation study on the limits of graphene-nanoribbon field-effect transistors (GNR-FETs) for post-CMOS digital applications. Both conventional and tunneling FET architectures are considered. Simulations of conventional narrow GNR-FETs confirm the high potential of these devices, but highlight at the same time OFF-state leakage problems due to various tunneling mechanisms, which become more severe as the width is made larger and require a careful device optimization. Such OFF-state problems are partially solved by the tunneling FETs, which allow subthreshold slopes better than 60 mV/dec, at the price of a reduced ON-current. The importance of a very good control on edge roughness is highlighted by means of a direct simulation of devices with non-ideal edges.

In this paper, we investigate quasi-ballistic transport in nanowire field-effect transistors (NW-FETs). In order to do so, we address the 1-D Boltzmann transport equation (BTE) and find its exact analytical solution for any potential profile with the constraint of dominant elastic scattering. A simulation code implementing a self-consistent Schrodinger-Poisson solver in the transverse direction and the present BTE solution in the longitudinal direction is worked out, providing the I-V characteristics of the NW-FET. Such characteristics are compared with those computed using a numerical BTE solver accounting for both inelastic and elastic collisions, and the two of them turn out to agree very nicely. From this comparison, it may be concluded that inelastic scattering plays a minor role for small-diameter FETs with device lengths in the decananometer range. Next, a methodology for the calculation of the transmission and backscattering coefficients is worked out for the first time starting from the scattering probabilities. The aforementioned coefficients turn out to be functions of the ratio between the carrier transit time and a suitably averaged momentum-relaxation time. Therefore, one of the main conclusions of this paper is that, so long as inelastic collisions are negligible, the so-called kT layer plays no role in 1-D quasi-ballistic carrier transport.

The impact of acoustic and optical-phonon scateringon on the performance of CNT-FETs is investigated using a full-quantum transport model within the NEGF formalism. Different gate lengths, dielectric materials and chiralities are considered. It is shown that the use of a high-k dielectric lowers the off-current dominated by phonon-assisted band-to-band tunneling. The device scalability is demonstrated: with the oxide thickness fixed to 1.5 nm, good performance is obtained with 15 nm and 10 nm gate lengths with SiO_2 and HfO_2 gate dielectrics, respectively. The role of phonon scattering in CNT-FETs of different chiralities is investigated for the HfO_2 devices. A similar analysis has also been carried out for source/drain underlp geometries. The results confirm that the calculation of the off-currents and delay times is strongly influenced by phonon scattering.

We investigate the transport properties of silicon- nanowire FETs by using two different approaches to the solution of the Boltzmann equation for the quasi-1-D electron gas, namely, the Monte Carlo method and a deterministic numerical solver. In both cases, we first solve the coupled Schrodinger-Poisson equations to extract the profiles of the 1-D subbands along the channel; next, the coupled multisubband Boltzmann equations are tackled with the two different procedures. A very good agreement is achieved between the two approaches to the transport problem in terms of mobility, drain-current, and internal physical quantities, such as carrier-distribution functions and average velocities. Some peculiar features of the low-field mobility as a function of the wire diameter and gate bias are discussed and justified based on the subband energy and wave-function behavior within the cylindrical geometry of the nanowire, as well as the heavy degeneracy of the electron gas at large gate biases.

In 2004, we reported the short-term results of a multicentric, phase 2 study of imatinib 400 mg daily and pegylated interferon-alpha in the treatment of 76 early chronic phase Philadelphia-positive chronic myeloid leukemia patients. In this report, we update the results with an observation time of five years. After two years of treatment, all but 10 patients (13%) had discontinued pegylated interferon-alpha. The complete cytogenetic response rate at five years was 87%, and 94% of complete cytogenetic responders maintained the complete cytogenetic response after five years. All but one complete cytogenetic response also achieved a major molecular response. These data confirm the excellent response to imatinib front-line and the stability of the complete cytogenetic response. Any possible additional benefit of the combination with interferon-alpha remains uncertain, due to low patient compliance.

In this paper we investigate the effect of surface roughness scattering on transport in silicon nanowire FETs using a deterministic Boltzmann equation solver previously developed by the authors. We first solve the coupled Schroedinger-Poisson equations to extract the subband profiles along the channel, and then address the transport problem. Some features of the low-fied mobility as a function of the wire diameter and gate bias are discussed and the effect of surface roughness on the I-V characteristics is presented.

In this paper, we examine the theoretical foundations of the quantum drift-diffusion and density-gradient transport models for the simulation of fully-depleted silicon-on-insulator and silicon nanowire FETs. In doing so, we highlight the strengths and limitations of both approaches. In the former case, the harmonization of the classical and quantum-mechanical perspectives is pursued by means of Bohm’s theory of quantum potential and by solving, in addition to the coupled Schrodinger–Poisson equations, as many drift-diffusion equations as the number of populated subbands. The latter approach is affected instead by more serious conceptual problems, as it basically replaces the Schrodinger equation with a simplified non-linear equation in the electron-charge concentration, by which energy quantization, multiple subbands, and multiple effective-masses are neglected. Despite these limitations, the density-gradient model turns out to be remarkably successful in predicting the device I–V characteristics. Simulation examples are discussed and the model predictions are compared. In our implementation, the simulation efficiency of the QDD is superior to that of the DG model.

The impact-ionization coefficient at high fields is derived in terms of the electric field E and lattice temperature TL, without introducing a priori relations among the parameters. An asymptotic analysis leads to simplifications that validate closed-form expressions of the impact-ionization coefficient. The role of the relaxation times in determining the slope is discussed, along with the meaning of the critical field.

The ultimate scaling limits of p-i-n carbon-nanotube field-effect transistors (CNT-FETs) are investigated through numerical simulations based on a quantum–mechanical transport within the nonequilibrium Green’s function formalism, based on an energy-dependent effective mass, including inelastic phonon scattering. Starting from the projected specifications of the International Technology Roadmap for Semiconductors for the low operating-power double-gate MOSFETs, the effect of variations of oxide thickness, power supply, and gate length has been systematically studied. The main conclusion is that there is no speed advantage in scaling the gate length of the p-i-n CNT-FETs below 16 nm due to the rapid increase of the tunneling current in the subthreshold region. A near optimum is found by keeping the gate length fixed at 16 nm and by scaling the oxide thickness and the power supply.

Measurements of the I(V ) characteristic in Ovonic semiconductors are notoriously unstable. Experimental setups must therefore rely on pulsed schemes in which only the positive slope branches of the characteristic are detected. This paper considers the time-dependent, trap-limited conduction model proposed by the authors for investigating this type of devices, and shows that the model is suitable for stability analysis. The conditions that make the measurement stable are assessed; also, examples of simulations in the oscillatory regime are given, in the field-driven case.

In this work we investigate the electrostatics of the top-gate carbon-nanotube FET (CNT-FET) and the silicon-based Π-gate FET at the ITRS 22 nm node. In order to do so, we solve the coupled Schrodinger and Poisson equations within the cross-section of each device, and compare the channel-charge and capacitance curves as functions of the gate voltage. This study shows that, for a fixed cross-sectional area, the quantitative differences between the two devices are small both in terms of charge and capacitance. The use of a classical model for the Π-gate FET shows instead that the resulting discrepancies with respect to the quantum-mechanical (QM) model are very relevant using both the Boltzmann and Fermi statistics. Thus, accounting for quantum-mechanical effects is essential for a realistic prediction of the device on-current and transconductance at the feature sizes considered here. The effect of high-κ dielectrics is also addressed. As opposed to planar-gate devices, the electrostatic performance of Si-based Π-gate FETs and CNT-FETs is not adversely affected by the use of different insulating materials with the same equivalent oxide thickness. As a consequence, not only do high-κ dielectrics relieve the gate-leakage problem; they also improve the device performance in terms of the gate-control effectiveness over the channel.

In this work we investigate and compare the electrostatics of fully depleted cylindrical silicon-nanowire (SiCNW) FETs, four-gate rectangular nanowire (4G RNW) FETs, tri-gate rectangular nanowire (3G RNW) FETs and gate-all-around carbon-nanotube (GAA-CNT) FETs at advanced miniaturization limits. In doing so, we rigorously solve the coupled Schrodinger–Poisson equations within the device cross-sections and fully account for quantum-mechanical effects. The investigation, carried out for the 65 and 45 nm technology nodes, leads to the unexpected conclusion that, for an assigned threshold voltage, the gate-all-around CNT-FET offers only a slightly better performance with respect to the SiCNW and the 4G RNW-FETs. This is due to the compensation of two different mechanisms, namely a higher gate effectiveness and a lower density of states. The 3G RNW yields instead an electron density within the channel which is about 25% lower than the SiCNW and 4G RNW-FETs at a given gate voltage. Such a reduced performance is due to its inherent asymmetry, which negatively affects the gate control on the channel charge.

This paper deals with the problem of dimensions shrinking of some basic sensors in order to see whether or not this process may bring to us advantages in designing future sensor systems. In this context, after some considerations related to the sensor strategy adopted on behalf of living beings, the attention is payed on cantilevers and microphones similar behaviour, while more emphasis is given to the sensor-oriented MOSFET family, which includes ISFET and GasFET. Here the most relevant sensor parameter, i.e. the sensitivity, is considered and discussed as a key aspect encountered when the choice of the sensor dimension becomes of primary importance in view of both the sensor system design and the technology option.

The linear drain current degradation due to hot-carrier stress (HCS) of an n-type LDMOS with shallow-trench isolation (STI) has been investigated through experiments and TCAD predictions under AC pulsed stress conditions. The systematic increase of degradation with frequency and the dependence on rise/fall times and duty cycle has been explained by using a new TCAD approach based on physical models. The degradation increase can be correlated to the peak of the HCS reaction rate at the rising edge. The analysis carried out on two different devices confirms the TCAD predictions.

In this work we investigate the ballistic ratio and the backscattering coefficient in nanowire FETs operating under quasi-ballistic conditions. Starting from general expressions of the current–voltage characteristics worked out in a previous paper, we extract the above parameters and their functional dependence on inversion-layer charge and device length. The computation is based on a rigorous analytic solution of the BTE and on a numerical solution of the coupled Schroedinger–Poisson equations, by which multiple subbands are taken into account. We propose three different definitions of the ballistic ratio, clarify their meaning and compute their values against the gate voltage and the device length. As opposed to most phenomenological treatments addressing this subject for 2D nanoscale MOSFETs, the strength of our approach is that the aforementioned parameters can be computed from the knowledge of the scattering probabilities, without introducing any major simplifying assumptions.

In this work we propose a physics-based analytical model of nanowire tunnel FETs, which is meant to provide a fast tool for an optimized device design. The starting point of the model is the Landauer expression of the current for 1D physical systems, augmented with suitable expressions of the tunneling probability across the tunnel junctions and the whole channel. So doing, we account for the ambipolar effect, as well as for the tunnel-related leakage current, which becomes appreciable when small band-gap materials are used. The model is validated by comparison with numerical simulation results provided by the k · p technique. With this model we examine the problem of the non-linear output characteristics of tunnel FETs, and the related small drain conductance at low drain voltage, which prevents rail-to-rail logic switching, and design a nanowire TFET by an appropriate selection of the material, nanowire size and degeneracy levels in the source and drain regions.

Tunnel FETs (TFETs) are promising alternatives to the conventional CMOS technology for steeper-than-60mV/dec subthreshold slopes (SS) required to limit power consumption of integrated circuits [1]. Current challenges for TFET integration into practical circuit applications include reaching acceptable ION levels, suppressing ambipolar effects, improving output characteristics [2], and simultaneously co-integrating optimized n-and p-type devices. All of these issues are carefully taken into account in this work. Device- and circuit-level design of TFET inverters is proposed, based on co-optimized n-and p-type TFETs integrated on the same InAs/ Al0.05Ga0.95Sb platform. A full-band quantum simulation approach is adopted to properly account for quantum effects which strongly influence TFET device, and hence circuit, performance. This advances the state of the art of TFET-based circuit literature, which is mostly based on simplified TCAD models [3], with rare calibrations against atomistic calculations [4].

In this paper, we present a mode space method for atomistic non-equilibrium Green's function simulations of armchair graphene nanoribbon FETs that includes electron-phonon scattering. With reference to both conventional and tunnel FET structures, we show that, in the ideal case of a smooth electrostatic potential, the modes can be decoupled in different groups without any loss of accuracy. Thus, inter-subband scattering due to electron-phonon interactions is properly accounted for, while the overall simulation time considerably improves with respect to real-space, with a speed-up factor of 40 for a 1.5-nm-wide device. Such factor increases with the square of the device width. We also discuss the accuracy of two commonly used approximations of the scattering self-energies: the neglect of the off-diagonal entries in the mode-space expressions and the neglect of the Hermitian part of the retarded self-energy. While the latter is an acceptable approximation in most bias conditions, the former is somewhat inaccurate when the device is in the off-state and optical phonon scattering is essential in determining the current via band-to-band tunneling. Finally, we show that, in the presence of a disordered potential, a coupled mode space approach is necessary, but the results are still accurate compared to the real-space solution., Comment: 10 pages, 12 figures. Copyright (2013) American Institute of Physics. This article may be downloaded for personal use only. Any other use requires prior permission of the author and the American Institute of Physics

A new TCAD-based approach is used to investigate hot-carrier stress (HCS) effects, especially suited for power devices. Physically-based degradation models are used to determine the interface trap generation at different stress biases and ambient temperatures. Special attention has been given to the high current-voltage regimes, when significant self-heating effects and impact ionization play a relevant role. By monitoring the linear and saturation regimes of a rugged LDMOS at different stress biases and times, the spatial and energetic distribution of acceptor- and donor-type traps has been investigated for the first time confirming the experimental results.

Design of complementary n- and p-type heterojunction tunnel field-effect transistors (TFETs) realized with the same InAs/Al0.05Ga0.95Sb material pair is carried out in this work using 3D, full-quantum simulations. Several design parameters are optimized, leading to a TFET pair with similar dimensions and feasible aspect ratios, which exhibit average subthreshold slopes around 30 mV/dec and relatively high on-currents of 280 (n-TFET) and 165 μA/ μm (p-TFET) at 0.4 V supply voltage. This is combined with low operating power (LOP) compatible off-currents, which makes the proposed technology platform well suited for LOP applications and even usable in HP scenarios. Devices with reduced cross section (7 nm instead of 10 nm) are also proposed as good candidates for low standby power (LSTP) scenarios.

We discuss the phenomenon of negative output differential resistance of short-channel graphene FETs at room temperature, whose physical origin arises from a transport-mode bottleneck induced by the contact-doped graphene. We outline a simple semianalytical model, based on semiclassical ballistic transport, which captures this effect and qualitatively reproduces results from the non-equilibrium Green's function approach (NEGF). We find that this effect is robust against phonon scattering.

An analytical model of the threshold voltage variance induced by random dopant fluctuations (RDF) in junctionless (JL) FETs is derived for both cylindrical nanowire (NW) and planar double-gate (DG) structures considering only the device electrostatics in subthreshold. The model results are shown to be in reasonable agreement with TCAD simulations for different gate lengths and device parameters. The results confirm previous indications that the threshold voltage fluctuations are a serious concern for nanometer-scale JL FETs.

In this work we investigate by numerical simulation the electrical properties of the junctionless nanowire field-effect transistor, which has recently been proposed as a possible alternative to the junction-based FET. The numerical model assumes a cylindrical geometry and is meant to provide a physical understanding of the device behaviour by highlighting the features of the I–V and C–V characteristics, as well as the electrostatic potential and carrier concentration within the channel. Numerical results are compared with the experimental turn-on characteristics and are found to provide a generally-good agreement. Finally, we discuss the strengths and the limitations of this device as a possible candidate for future technology nodes.

In this paper, we model the electrical properties of a junctionless (JL) ultrathin-body silicon-on-insulator field-effect transistor (SOI-FET), which has been proposed as a possible alternative to the junction-based SOI-FET. The model is based on improved depletion approximation, which provides a very accurate solution of Poisson's equation and allows for the computation of the substrate, as well as the Si-body lower- and upper-surface potentials by an iterative procedure, which accounts for the back-oxide (BOX) charge and thickness and the potential drop within the substrate. The drain current is then computed versus gate, drain, and substrate voltages via integral expression and validated by comparison with technology computer-aided design simulation results. Analytical models of the field-effect-transistor threshold voltage and subthreshold slope are worked out against the substrate voltage, highlighting the effect of the substrate doping and BOX thickness on the aforementioned parameters. In essence, this work provides the physical background for better understanding of the JL SOI-FET and its assessment for logic applications.

In this work we examine the problem of the nonlinear output characteristics of tunnel FETs, and the related small drain conductance at low drain voltage, which prevents rail-to-rail logic operation and severely degrades the device dynamic properties compared with standard CMOS FETs. The problem is investigated with the help of an analytical model which highlights the constraints of the device design by splitting the effects of the tunneling probability from the density of states in the source, channel and drain, and makes it possible to design a nanowire TFET by an appropriate selection of the material, nanowire size and degeneracy levels in the source and drain regions. So doing, we remove the above characteristics' feature and recover a large drain conductance without degrading the subthreshold slope. The optimized device is numerically simulated using the k·p model, whose results are in fair agreement with the analytical one.

This study presents vertical Si-nanowire (SiNW) gate all-around (GAA) non-volatile memory with channel diameter down to 20nm. The junction-less devices with SiN trap layer is found to have comparable memory characteristics (3.2V in 1ms P/E at +15V/-16V) to the junction-based cell. Despite of that, the absence of junctions reduces the process complexity and makes vertical SiNW a suitable platform for multi-level stacked ultra high density memory application.