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The key features and performance data of a 2560/spl times/1960-pixel split-frame-transfer imager developed for space surveillance is described. The eight-port, backside illuminated charge coupled device (CCD) features 24 /spl mu/m pixels with buried blooming drains to provide 100% optical fill-factor and >1000/spl times/ overload protection from blooming. The imaging and storage registers are strapped with metal to achieve vertical transfer clock rates >400 KHz for the 61 mm long imaging register gates. The 5 million pixel array operates at 2.7 frames/s. The monolithic focal plane includes a 32/spl times/32-pixel frame-transfer imager, with a single output, which operates at 1000 frames/s. The output ports employ a floating diffusion output circuit with responsivity of 10.5 /spl mu/V/e and noise of 7e RMS at a 1.25 MHz clock rate. The imager is photocomposed employing a combination of 5/spl times/ and 1/spl times/ lithography. The photocomposition approach is described.

In this letter, the 28 nm CMOS divide-by-three injection-locked frequency divider (ILFD) operating at the V band is presented for the first time. Based on a differential direct injection scheme, the proposed circuit can perform a division ratio of three while an enhanced locking range is achieved due to superior injection efficiency. From the measured results, the core circuit consumes a dc power of 8.8 mW from a 1 V supply voltage. At an incident power level of 0 dBm, the divider exhibits a locking range from 52.61 to 55.12 GHz. Within this frequency range, the output power and phase noise are kept around -5 dBm and -125 dBc/Hz at a 1 MHz offset, respectively.

By the electrostatic discharge (ESD)/matching co-design methodology, a wideband low-noise amplifier (LNA) using a grounded spiral inductor in conjunction with a MOM capacitor for ESD protection and wideband matching is demonstrated in a 65 nm CMOS. The shunt inductor provides an effective bidirectional ESD protection to the ground and the series capacitor greatly enhances the breakdown level in the current discharge path. The measurement results demonstrate an over 8 kV human-body-model ESD protection level with almost no RF characteristic degradation after ESD zapping. Under a power consumption of 5.6 mW, the ESD-protected LNA presents a flat NF and power gain of 3.3-3.9 dB and 16.6-17.9 dB, respectively, in the frequency range of 18.5-24.5 GHz, and a 3 dB bandwidth of 17.5-26 GHz is achieved.

A 1.1 um pitch pixel array fabricated by 45 nm 3D stacked technology, can be switched to peripheral circuits on same wafer or to other stacked wafer for process and signal integrity verification. It supports through silicon connection or direct connection to increase the flexibility by separating pixel array and sensing circuit. The novel wide operation range VCO and low power serializer are implemented to reduce the total power and noise.

We propose a new architecture of an all-digital PLL (ADPLL) for advanced cellular radios that is optimized for 28 nm CMOS. It is based on a wide tuning range, fine-resolution class-F DCO with only switchable metal capacitors and a phase-predictive TDC. The 8mW DCO emits -157 dBc/Hz at 20MHz offset at ~2 GHz, while fully satisfying metal density rules. The 0.4mW TDC clocked at 40MHz achieves PVT-stabilized 6 ps resolution for -108 dBc/Hz in-band phase noise. FREF spur is ultra-low at

Next-generation high-performance computing systems require high-bandwidth serial links to transport high-speed data streams among computational blocks. Optical links have recently attracted attention due to their low channel loss at high frequencies, requiring simpler equalization circuits than electrical links. The energy-efficiency of optical links can thus be significantly improved [1-5]. Broadband techniques such as inductive peaking are commonly used in highspeed optical transceivers for bandwidth enhancement at the expense of the chip area. Inductor-less receivers have been proposed [4,6] to reduce chip area but they usually consume more power or have lower data rates at given technology nodes. In this paper, we present two optical receivers that each consists of a pseudodifferential CMOS push-pull transimpedance amplifier (TIA), a DC offset-cancellation circuit, a limiting amplifier (LA) with interleaving active-feedback [6], and a T-Coil fT-doubler output buffer. The block diagram and experimental setup are shown in Fig. 8.4.1. The capacitance of the off-chip GaAs PIN photodetector (PD), which is wire-bonded to the CMOS receiver, is 100fF with 0.4A/W responsivity. The two optical receivers have identical designs except for the LA, in which two different inductive peaking techniques, conventional and shared-inductor, are designed and fabricated on the same die in 28nm CMOS technology.

New materials and technologies are enabling next generation systems and applications. The first four papers in this session combine different semiconductor materials (organic and/or oxide) on flexible foils to realize a variety of applications such as a microprocessor, a display, a sensor and an RFID tag. Papers 5, 8 and 9 combine in a hybrid manner crystalline high-bandgap semiconductors on top of the back-end-of-line (BEOL) of silicon. In papers 6 and 7 dedicated communication systems are implemented in automobiles and over the human body. Finally, paper 10 implements a learning machine mimicking the activity in the human brain.

This study presents a wideband low noise amplifier (LNA) including electrostatic discharge (ESD) protection circuits using 65 nm CMOS with a gate oxide thickness of only ~ 2 nm. By co-designing the ESD blocks with the core circuit, the LNA shows almost no performance degradation compared to the reference design without ESD. Under a power consumption of only 6.8 mW, the silicon results show that the LNA can achieve a peak power gain of 13.8 dB. Within the 3 dB bandwidth from 2.6 GHz to 6.6 GHz, the noise figure (NF) is in a range of 4.0 dB to 6.5 dB and the input reflection coefficient S 11 is below -13.0 dB. Using the miniaturized Shallow-Trench-Isolation (STI) diode of ~ 40 fF capacitance and a robust gate-driven power clamp configuration, the proposed LNA demonstrates an excellent 4 kV human body mode (HBM) ESD performance, which has the highest voltage/capacitance ratio ( ~ 100 V/fF) among the published results for RF LNA applications.

This study presents a 53.6 GHz wideband direct injection-locked frequency divider (DILFD) using 65 nm CMOS technology. By operating a RF input transistor in subthreshold region and changing its forward body bias, the proposed DILFD achieves a 28.6 GHz (72%) locking range with 6.7 mW power consumption and 1 V supply voltage. When varying the supply voltage from 0.9 V to 1.1 V or its physical temperature from 253 K to 373 K, the measured locking range remains more than 22 GHz.

A low-phase-noise phase-locked loop (PLL) is widely used in clock generation, frequency synthesis, and data conversion. In a PLL using a sub-sampling phase detector (SSPD) achieves not only low phase noise, but also low power. In a low-phase-noise sub-harmonically injection-locked PLL (SIPLL) is presented. The injection timing of a SIPLL is sensitive to the process, voltage, and temperature (PVT) variations. In addition, the divider of a SIPLL [3-5] cannot be powered down to save the power as in [1, 2]. In this paper, a divider-less SIPLL with self-adjusted injection timing is presented.

This paper presents a V-band low-noise amplifier with high RF performance and ESD robustness. An inductor-triggered silicon-controlled rectifier (SCR) assisted with both a PMOS and an inductor is proposed to enhance the ESD robustness and minimize the impact of the ESD protection block on the millimeter-wave LNA. The initial-on PMOS improves the turn-on speed and the inductor resonates with the parasitic capacitance, respectively. Also, a 3-stage wideband V-band LNA is designed by using the gate inductor in the common-gate stage of the cascode topology as gain peaking to compensate the roll-off at high frequencies for bandwidth extension. The measured results demonstrate a 2.5-kV HBM ESD protection level with a minimum noise figure (NF) of 5.1 dB and a peak gain of 22 dB, also a 3-dB bandwidth of 56–67 GHz can be achieved under a power consumption of only 23 mW.

Standards with narrow channel spacing have stringent requirements for in-band phase noise of oscillator, which is dominated by up-converted flicker noise. In this paper, we propose a LC-tank voltage-controlled oscillator (VCO) that utilizes novel Mesh-BJT structure to suppress in-band phase-noise while maintaining low power consumption. The proposed 2.7GHz LC-VCO consumes 3.9mW from a 1.5V supply and the figures of merit (FOM) at 10KHz and 100KHz offsets are −222dBc/Hz and −204dBc/Hz in 65nm CMOS. The Mesh-BJT is compatible with standard CMOS and no extra masks are required. To our best knowledge, this is the best FOM ever reported at low offsets (

This paper studies the trade-off between different cell-based layout styles and V t options using a set of 5-GHz differential cascode LNAs. The test chip is fabricated in 65-nm CMOS process. The impact of merged diffusion area at the cascode node, the effect of gate contact style as well as the usage of normal V t versus low V t are presented. Our measurement results show that using individual device layout with separated diffusion area, low V t and double-sided gate contact provides better gain and noise performance. Specifically, the power gain and noise figure (NF) are improved by 1.5 dB and 0.3 dB, respectively, under the same bias current and power consumption. On the other hand, using normal V t devices with merged diffusion area achieves significantly better linearity with about 4-dBm increase in IIP3. Based on these findings, recommended layout and V t usage guidelines for RF amplifier design in 65-nm technology are proposed.

We present a new varactorless voltage-controlled oscillator (VCO) technique at 100GHz in 65nm CMOS technology. Using source degeneration and capacitors between the source and drain nodes of cross-coupled MOS transistors, the new technique is able to change the output frequency of a VCO in a 100GHz fundamental mode with an at least 4GHz wide tuning range. The phase noise of the VCO is −85.1dBc/Hz at 1MHz offset from the 98.6GHz carrier frequency. The power consumption is 7.4mW when the supply voltage is 1.2V and the maximum output frequency is 102.7GHz.

This paper presents an ESD-protected V-band (f 0 at 58 GHz) low-noise amplifier (LNA) in 65-nm CMOS. Instead of using the conventional diode-based RF ESD design, a high current capability spiral inductor and a high breakdown MOM capacitor are employed as effective bi-directional ESD protection network, and also as part of the input matching by the co-design approach. The measured results demonstrate an over 8-kV HBM ESD protection level with a NF of 5.3 dB and a power gain of 17.5 dB at 58 GHz, under a power consumption of 18 mW. To our best knowledge, this LNA presents a highest ESD protection level and a lowest NF, compared with prior arts in a similar frequency range.

This 55nm CMOS 12-bit current-steering DAC directly powered by the single-inductor dual-output (SIDO) switching DC-DC converter with the dynamic voltage scaling (DVS) technique improves the DAC's power efficiency by 25% and achieves 65.34dB SFDR. The proposed 3S method, including separating, splitting, and shifting, effectively reduces the current mismatching within 0.2% and suppresses the switching noise interference from the SIDO converter. The 12-bit DAC and SIDO module achieve compatible performance compare to the tradition method and has the benefit of area and energy efficiency.

Epiretinal prostheses deliver electrical pulses through a great number of stimulation electrodes to generate visual perception. Since a large amount of stimulation parameters have to be sent into the eye wirelessly, the transmission efficiency and data loss are critical design factors. While the error rate of wireless transmission might not be perfect due to the limited power dissipation allowed in the eyeball, data loss can be reduced by altering the size of data packets. In this paper, the correlation between packet length and data loss are analyzed, and we find that more than 10 times of reduction in data loss can be achieved by shortening the data packets. The costs and benefits of using error-correcting codes (ECC) are also evaluated. A data packet protocol for 1024-channel retinal prosthesis as well as the corresponding receiver circuitry are then designed based on the results of the analyses. The circuit occupies 330 μm × 262 μm using 0.18 μm CMOS technology. With the flexibility provided by the protocol and receiver circuitry, data packet configuration (size and ECC on/off) can be adaptively adjusted to optimize for real-time wireless channel error conditions.

This paper presents a fully integrated low-power neuron recording front-end system in TSMC 65 nm 1p6m CMOS technology. The proposed system is comprised of two recording modules, each containing 32 recording channels with tunable bandwidth and gain, a 32-to-1 multiplexer, one differential successive approximation register (SAR) analog-to-digital converter (ADC) with programmable sampling rate on each channel, and a digital control module to govern the signal digitization as well as to encode and serialize the digitized neuron signal from two ADCs. The recording amplifier presents a low power and low noise merits of 6 μW and input-referred noise of 3.8 μV(rms). The ADC digitizes the neural signal at a sampling rate of 40 kS/s with 9-bit resolution. The overall power consumption of the entire system is 2.56 mW and occupies an area of 3 × 4mm(2).

By means of co-designed methodology, a 24-GHz low-noise amplifier, utilizing junction varactors as ESD protection, is first demonstrated by a 65-nm CMOS technology. The ESD protection capability of the junction varactors with multi-finger topology is characterized in details by transmission line pulse (TLP) measurements. Under a 1.2-V supply voltage and a 5.8-mA drain current, the proposed LNA achieves a 1.4-A TLP failure level, corresponding to an over 2-kV human body model (HBM) ESD protection. The LNA presents a lowest noise figure of 2.8 dB at 23.5 GHz and a peak power gain of 14.3 dB at 24 GHz, respectively. The input third-order intercept point (IIP3) is −5 dBm and the input and output return losses are both greater than 10 dB. To the best of our knowledge, this is the first attempt using junction varactors as the ESD device in 65-nm CMOS.

This paper presents a K-band low noise amplifier (LNA) co-designed with ESD protection circuit in 40-nm CMOS technology. By treating ESD devices as a part of the input matching network, an ESD protected 24-GHz LNA is demonstrated with a NF of 3.2 dB under a power consumption of only 4.1 mW. The ESD protection network is composed of dual-diode and a gate-driven power clamp achieving an ESD level of 2.8 kV human body model (HBM). Owing to the co-design approach, the NF only degrades by 0.2 dB compared with the reference LNA without the ESD network. The ESD-LNA presents a power gain of 13.0 dB with the input and output return losses both greater than 10 dB. To the best of our knowledge, this is the first report on a 24-GHz ESD-protected LNA in 40-nm CMOS.

In this study, we demonstrate an analog front-end (AFE) circuit with ESD protection for a passive RFID tag at UHF-band (860∼960 MHz) in a 0.18-μm CMOS technology. A dual-directional silicon-controlled-rectifier (dual-SCR) structure is proposed for the ESD protection under the large-signal operation at the RFID input. With the well-designed dual-SCR, a large trigger voltage (V T ) of ∼ 16.9 V is obtained. The parasitic capacitance of the ESD block is only ∼ 34 fF, which has virtually no impact on the core circuits at the frequency of interest. The measured ESD levels achieve 3.0-kV human-body-mode (HBM) and 200-V machine-mode (MM), respectively. The RF-DC rectifier in the RFID circuit can generate a stable power supply output about 1.2 V when the RF input power exceeds −7.5 dBm.

This paper studies the electrostatic discharge (ESD)-protected RF low-noise amplifiers (LNAs) in 65-nm CMOS technology. Three different ESD designs, including double-diode, modified silicon-controlled rectifier (SCR), and modified-SCR with double-diode configurations, are employed to realize ESD-protected LNAs at 5.8 GHz. By using the modified-SCR in conjunction with double-diode, a 5.8-GHz LNA with multiple ESD current paths demonstrates a 4.3-A transmission line pulse (TLP) failure level, corresponding to a ~ 6.5-kV Human-Body-Mode (HBM) ESD protection level. Under a supply voltage of 1.2 V and a drain current of 6.5 mA, the proposed ESD-protected LNA demonstrates a noise figure of 2.57 dB with an associated power gain of 16.7 dB. The input third-order intercept point (IIP3) is - 11 dBm, the input and output return losses are greater than 15.9 and 20 dB, respectively.

This paper presents a 2.5–8Gb/s transceiver for PCI Express Gen3.0/2.0/1.0 applications. To overcome channel loss of high bit rate application, a linear equalizer (LEQ) and decision feedback equalizer (DFE) are used to eliminate ISI effect, compensate channel loss, and improve BER performance for 28-inch FR4 channel. The 3-tap feed-forward equalizer (FFE) is used to improve signal quality in transmitter. The resolution of de-emphasis and pre-shoot is up to 1/63 and 1/15. It also performs 0.8UIpp eye opening for 8Gb/s operation. A 2nd order clock and data recovery (CDR) employs digital finite state machine to track phase difference and frequency between clock and data. The CDR can cover 0 to −5000ppm frequency offset of SSC modulation and achieve jitter tolerance of up to 0.2UIpp at 8Gb/s with a BER=10−10 when all specified jitter sources is included. The integrated transceiver operates from 2.5Gb/s to 8Gb/s and consumes 235mA at 8Gb/s current with 0.95V supply voltage. The test-chip is implemented by flip chip layout and fabricated in TSMC 40nm 0.9V/1.8V CMOS technology. The area of transceiver is 725um × 615um.

In this paper, a novel circuit topology of CMOS divide-by-three injection-locked frequency divider is demonstrated. By using a differential direct injection pair with a LC-tank oscillator, the proposed circuit can perform the division ratio of three while the wide locking range is obtained. Based on the presented circuit architecture, a V-band frequency divider is implemented in 65-nm CMOS for demonstration. Operated at a supply voltage of 1.0 V, the divider core consumes a dc power of 5.2 mW. At an incident power of 0 dBm, the fabricated circuit exhibits an input locking range from 58.6 to 67.2 GHz. The measured output power and locked phase noise at a 1-MHz offset are −10 dBm and −127 dBc/Hz, respectively. To the authors' best knowledge, this work is the first CMOS V-band divide-by-three injection-locked frequency divider owning a locking range over 10% without any tuning mechanism reported to date.

A new ESD topology is proposed for RF low-noise amplifier (LNA). By using the modified silicon-controlled rectifier (MSCR) in conjunction with a P+/N-well diode clamp, a 5.8-GHz LNA with 6.5-kV ESD protection circuit is demonstrated by a 65-nm CMOS technology. Compared with the reference design, the new topology enhances the ESD level from 3.5 kV to 6.5 kV for human body model (HBM) while the noise figure (NF) is only 0.13 dB higher. Under a supply voltage of 1.2 V and drain current of 6.5 mA, the proposed ESD-protected LNA has a NF of 2.57 dB with an associated power gain of 16.7 dB. The input third-order intercept point (IIP3) is −11 dBm and the input and output return losses are below −15.9 dB and −20 dB, respectively.

Three different digitally-assisted analog designs are presented to demonstrate the powerful way to solve the analog design deficiencies in the submicron CMOS technology. A 200 MS/s 12-bit pipeline ADC is using the split-capacitor correlation method to solve the linear and nonlinear problems. A 1 GS/s 14-bit current-steering DAC is using the programmable sub-DAC to continuously trimming the current mismatches. A 25 MS/s 16-bit ΣΔ ADC is using the adaptive way to correct the leakage noise and DAC nonlinearity.

A 15 μm2 cell 4 Kb electrical fuse memory is designed in 90 nm CMOS using core devices only. The N+ 8-sq asymmetric fuses are used to enhance fuse uniformity, reliability, and aggregate electro-migration. High-gain cascade amplifiers sense small resistance differences to achieve a 2.25 V program voltage in 1 mus. A sufficient design window is derived and verified by using on-chip resistance monitor without area overheads.

Many applications, such as industrial inspection and overhead reconnaissance benefit from line scanning architectures where time delay integration (TDI) significantly improves sensitivity. CCDs are particularly well suited to the TDI architecture since charge is transferred virtually noiselessly down the column. Sarnoff's TDI CCDs have demonstrated extremely high speeds where a 7200 x 64, 8 um pixel device with 120 output ports demonstrated a vertical line transfer rate greater than 800 kHz. The most recent addition to Sarnoff's TDI technology is the implementation of extended dynamic range (XDR) in high speed, back illuminated TDI CCDs. The optical, intrascene dynamic range can be adjusted in the design of the imager with measured dynamic ranges exceeding 2,000,000:1 with no degradation in low light performance. The device provides a piecewise linear response to light where multiple slopes and break points can be set during the CCD design. A description of the device architecture and measured results from fabricated XDR TDI CCDs are presented.

A novel, high-density, active-matrix, electroluminescent display has been fabricated using single-crystal silicon-on-insulator technology. This new approach offers many advantages including high brightness, superior speed, low power dissipation, high pixel density, high resolution, good gray-scale performance, and improved reliability. >

SOI technology is presently being used for the fabrication of both liquid crystal displays (LCDs) and electroluminescent (EL) displays. It has unique advantages for the fabrication of flat panel displays such as the production of devices with high performance and high breakdown voltage. It is the object of this paper to review the process technologies used in the fabrication of these displays and also to show the latest developments in these technologies.

A family of backside illuminated CCD imagers with 6.6 micrometers pixels has been developed. The imagers feature full 12 bit (> 4,000:1) dynamic range with measured noise floor of 50,000 e. The modulation transfer function performance is excellent, with measured MTF at Nyquist of 46% for 500 nm illumination. Three device types have been developed. The first device is a 1 K X 1 K full frame device with a single output port, which can be run as a 1 K X 512 frame transfer device. The second device is a 512 X 512 frame transfer device with a single output port. The third device is a 512 X 512 split frame transfer device with four output ports. All feature the high quantum efficiency afforded by backside illumination.

A backside illuminated time delay integration (TDI) charge coupled device (CCD) technology has been developed. Imagers have been demonstrated at 13 pm pixel size and 8 pm pixel size. Photocomposition (stitching) has been employed to realize TDI iinagers of length < 60 mm. Performance has been enhanced in the areas of quantum efficiency, dynamic range, modulation transfer function (MTF), and line scan rates. The focus of this work has been to develop this new generation of line scan imagers for advanced reconnaissance applications. The enhancements permit the deployment of new camera systems with higher sensitivity, and higher resolution. To support the deployment of this technology into rugged environments, a custom packaging technology has been 'developed. The packages provide a hermetic enclosure for the CCD and establish precise alignment of the CCD pixels to the package mounting fixture. This paper will summarize the design features of the 13 pm pixel and 8 jim pixel TDI arrays. Measured performance will be presented. Future plans for this backside illuminated TDI technology will be discussed.

Using a 12 by 12 micrometers pixel cell and 1.0 micrometers deign rules, a 0.7-inch diagonal 1280 by 1024 active matrix electroluminescent (AMEL) display has been designed and demonstrated using a silicon-on-insulator based CMOS technology. The display accepts data at 100 MHz via eight data inputs and provides five bits of gray scale. A total of 24 connections are used for all display functions. Architecture, theory of operation, and detailed specification for this new 2000 line-per-inch display will be discussed. The display is the same size as Planar's previously developed AMEL 640 by 480 arrays, thus providing over tour times the number of pixels in the same footprints as the prior design. The display provides workstation resolution in an extremely compact format and offers the same environmental robustness and optical performance as previously demonstrated in 1000 line-per-inch AMEL displays.

Active matrix electroluminescent (AMEL) devices are fabricated using circuitry built on the thin-film single crystal silicon on insulator wafers. A 128 X 128 matrix with 24micrometers pixel pitch (1000 lines/inch) is fabricated with higher than 80% fill factor showing initial brightness of above 500fL and high contrast ratios (>100:1). These devices demonstrated the successful combination of active circuitry fabricated using conventional IC processing with standard electroluminescent processing. This AMEL approach provides the potential for head-mounted displays with a very small profile and high efficiency.© (1994) COPYRIGHT SPIE--The International Society for Optical Engineering. Downloading of the abstract is permitted for personal use only.

AMEL displays with 12μm×12μm pixels in a 1280×1024 array have been built and operated at 100MHz input data rates. The display accepts data at 100MHz on each of the 8 parallel inputs to support a total pixel data rate of over 800 megabits per second. These high data rates were achieved using a 1.2μm effective channel length body-tied crystalline silicon TFTs fabricated on SOI. This is the highest data rate reported for any flat panel display.

The five-transistor (5T) CMOS/SOS memory cell has been widely used in RCA's radiation hardness products. The p-channel devices in the memory cell are protected from the cosmic ray hit by the buried contact diodes. However, there is no protection for the n-channel devices. A configuration referred to as seven-transistor (7T) CMOS/SOS memory cell which is modified from the 5T memory cell layout by inserting a depletion mode NMOS transistor in the feedback path of enhancement NMOS drain node has been proposed. Simulations show that this configuration increases the single event upset critical charge by a factor of 25 at Vdd=5V. The increase in silicon area is only 10%.