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We report GaN vertical trench MOS barrier Schottky (TMBS) diodes with embedded p-GaN shielding rings (SRs) and systematically investigate the impact of different structural parameters of the p-GaN SRs on the breakdown performance of the GaN-based vertical TMBS diodes by numerical simulation. The charge coupling effect by the embedded p-n junction at the bottom of the trench homogenize the electric field at the trench corner and alleviate the electric field crowding effect at the Schottky contact region, which can effectively avoid the premature breakdown and improve the reverse blocking capability of the TMBS diodes. The p-GaN SRs can also broaden the overlapped depletion region and shift the pinch-off point into the n−-GaN drift region, thus facilitating the 2-D depletion in the n−-GaN drift layer and boosting the breakdown performance of the conventional TMBS diodes. We found that the doping concentration, thickness, and the width of the p-GaN SRs are closely associated with the electric field distribution and the reverse breakdown characteristics of the GaN-based vertical TMBS diodes. The vertical TMBS diodes with optimal p-GaN SR parameters featured a dramatic improvement in the breakdown voltage from 907 to 1281 V, without an obvious degradation in the ON performance. The proposed TMBS diodes with a p-GaN SR structure can pave the way toward a high-performance GaN vertical power device for high-power and high-efficiency power switch applications.

A 2-D compact analytical model for the device potential of double metal double gate hetero-oxide Tunnel FET (DM DG Hetero-oxide TFET) has been developed in this work. The hetero-oxide (HfO2 + SiO2) and the double metal double gate allows improvement in current in the ON state of TFET as well as suppresses the ambipolar current in TFET curtailing both the limitations of TFET. Parabolic approximation method with required boundary conditions has been utilized to solve Poisson’s equation. Depletion region plays vital role in altering the potential of device in its proximity. Therefore, the depletion regions at drain and source are also considered for the modeling of the device. For this the effect of fringing field has been considered using the technique of conformal mapping in the depletion regions. The incorporation of the depletion region in potential modeling allows a precise modeling of the potential near channel-drain and source-channel junctions. The model results considering source and drain depletion region shows better match with simulation results. Validation of proposed model has done against simulation data using ATLAS TCAD SILVACO software. The compact analytical model developed here is found to have good agreement with the simulation framework.

Growth of 2D materials under ultrahigh-vacuum (UHV) conditions allows for an in situ characterization of samples with direct spectroscopic insight. Heteroepitaxy of transition-metal dichalcogenides (TMDs) in UHV remains a challenge for integration of several different monolayers into new functional systems. In this work, we epitaxially grow lateral WS2–MoS2 and vertical WS2/MoS2 heterostructures on graphene. By means of scanning tunneling spectroscopy (STS), we first examined the electronic structure of monolayer MoS2, WS2, and WS2/MoS2 vertical heterostructure. Moreover, we investigate a band bending in the vicinity of the narrow one-dimensional (1D) interface of the WS2–MoS2 lateral heterostructure and mirror twin boundary (MTB) in the WS2/MoS2 vertical heterostructure. Density functional theory (DFT) is used for the calculation of the band structures, as well as for the density of states (DOS) maps at the interfaces. For the WS2–MoS2 lateral heterostructure, we confirm type-II band alignment and determine the corresponding depletion regions, charge densities, and the electric field at the interface. For the MTB, we observe a symmetric upward bend bending and relate it to the dielectric screening of graphene affecting dominantly the MoS2 layer. Quasi-freestanding heterostructures with sharp interfaces, large built-in electric field, and narrow depletion region widths are proper candidates for future designing of electronic and optoelectronic devices.

Indium selenide (γ-In2Se3) films were prepared using RF magnetron sputtering. Influence of deposition time on structural, optical, morphological, and photoelectrochemical (PEC) performance was studied. Formation of γ-In2Se3 is confirmed by low angle XRD, Raman spectroscopy, and XPS analysis. Surface morphology investigated using FE-SEM shows that γ-In2Se3 films are uniform and have a dense grain structure, without cracks and holes. Optical properties show that γ-In2Se3films absorb mainly in the UV region, and the bandgap energy decreases from 2.81 to 2.27 eV as deposition duration increases. Conduction and valance band-edge potential values show that γ-In2Se3 films are suitable for photoelectrochemical hydrogen evolution. PEC activity of γ-In2Se3 photoanodes was evaluated using linear sweep voltammetry (LSV), and there was an increase in photocurrent density with deposition time. Electron impedance spectroscopy (EIS) analysis revealed that γ-In2Se3 photoanodes had high charge transfer resistance, and it decreases with deposition time, which leads to improved PEC performance. Investigation of Mott Schottky's (MS) results shows a shifting of flat band potential towards negative potential, suggesting movement of fermi level towards conduction band edge. Carrier density increases from 3.7 × 1019 cm−3 to 8.9 × 1020 cm−3 and depletion layer width of γ-In2Se3 photoanodes are found in the range of ~ 2.67–9.10 nm. The gradual increase in electron lifetime indicates a decrease in the recombination rate of photo-generated charge carriers. An increase in time-dependent photocurrent density reveals that γ-In2Se3 films have effective electron–hole separation. Our work demonstrates that γ-In2Se3 can be a probable candidate for PEC water splitting and opto-electronic applications.

For the first time, we report achieving a considerable output power density in metal-semiconductor field-effect transistors according to silicon-on-insulator technology (SOI MESFETs). Our main idea is to improve the breakdown voltage and the saturation current simultaneously and, therefore, the output power density of SOI MESFET devices by silicon dioxide engineering. Our silicon dioxide engineering consists of a step-shaped buried oxide (BOX) and an extra layer of silicon dioxide under the gate (SB-LO-SOI) in this work. A step-shaped in the channel area results in a more significant drain current due to increasing total carrier concentrations. Also, by omitting a part of the BOX and substituting it with n-doped silicon, the depletion layer changes, and the channel charges increase. Besides, the distribution of the electric field improves by the additional rectangular silicon dioxide layer under the gate as a result of extending the depletion layer. By having a premier electric field distribution, the breakdown voltage will enhance. According to the results, the breakdown voltage and the saturation current of the considered device improve by 130 % and 33 %, respectively, compared to the traditional one. As well as, the output power density of the considered device rises by 212 %. Thereupon, the SB-LO-SOI MESFET device outperforms the conventional SOI MESFET device in terms of electrical properties.

This paper reports the catalyst-free coaxial TiO2/Ge-nanowire (NW) heterostructure synthesis using the glancing angle deposition (GLAD) technique integrated into an electron beam evaporator. The frequency and voltage dependence of the capacitance–voltage (C–V) and conductance–voltage (G/ω–V) characteristics of an Ag/TiO2-NW/Ge-NW/Si device over a wide range of frequency (10 kHz–5 MHz) and voltage (− 5 V to + 5 V) at room temperature were investigated. The study established strong dependence on the applied frequency and voltage bias. Both C–V and G/ω–V values showed wide dispersion in depletion region due to interface defect states (Dit) and series resistance (Rs). The C and G/ω value decreases with an increase in applied frequency. The voltage and frequency-dependent Dit and Rs were calculated from the Hill-Coleman and Nicollian–Brews methods, respectively. It is observed that the overall Dit and Rs for the device decrease with an increase in the frequency at different voltages. The dielectric properties such as dielectric constant ($$\upepsilon$$ ϵ ′), loss ($$\upepsilon$$ ϵ ″) and loss tangent (tan δ) were determined from the C–V and G/ω–V measurements. It is observed that $$\upepsilon$$ ϵ ′, $$\upepsilon$$ ϵ ″ decreases with the increase in frequency. Therefore, the proposed MOS structure provides a promising alternative approach to enhance the device capability in the opto-electronics industry.

Nanoscale oxide layer protected semiconductor photoelectrodes show enhanced stability and performance for solar fuels generation, although the mechanism for the performance enhancement remains unclear due to a lack of understanding of the microscopic interfacial field and its effects. Here, we directly probe the interfacial fields at p-GaP electrodes protected by n-TiO2 and its effect on charge carriers by transient reflectance spectroscopy. Increasing the TiO2 layer thickness from 0 to 35 nm increases the field in the GaP depletion region, enhancing the rate and efficiency of interfacial electron transfer from the GaP to TiO2 on the ps time scale as well as retarding interfacial recombination on the microsecond time scale. This study demonstrates a general method for providing a microscopic view of the photogenerated charge carrier's pathway and loss mechanisms from the bulk of the electrode to the long-lived separated charge at the interface that ultimately drives the photoelectrochemical reactions.

In this study, the frequency/voltage dependence of the dielectric constant (epsilon '), dielectric loss (epsilon ''), real/imaginary components of the complex electric modulus (M ', M ''), tangent loss (tan delta), ac electrical conductivity (sigma(ac)), real and the imaginary parts of the complex impedance (Z*), phase angle (theta) between resistance current, and capacitive current of the Al/(Coumarin: PVA)/p-Si structures were investigated using C/G-V-f measurements in wide range of frequency (10 kHz-1 MHz) and voltage (+/- 5 V) by 0.05 V steps. These parameters showed strong dependence on frequency and voltage due to the existence of surface states (N-ss), their life/relaxation time (tau), series resistance (R-s), and polarization processes. epsilon ' and epsilon '' values were found to be high at lower frequencies and this was explained by the fact that the interfacial dipoles have enough time to orient themselves in the direction of the signal and thus N-ss can easily follow it. M '-V and M ''-V plots both have a distinctive peak at depletion region and peak position shifts toward accumulation region with increasing frequency due to restructuring and reordering of N-ss under electric field and polarization. ln(sigma)-ln(f) plots for accumulation region show two linear parts with different slopes, and this provides an evidence to the existence of two different conduction mechanisms which correspond to intermediate and high frequency regions. The strong dispersion in epsilon ' and epsilon '' at lower frequencies was attributed to the N-ss, Maxwell-Wagner-type polarizations.

LiMn0.8Fe0.2PO4 by coating with carbon and reducing the particle size to nanometric scale can be used as a superb cathode material for lithium-ion batteries. In this study, LiMn0.8Fe0.2PO4/C composite is synthesized by high-energy milling method, and the charge and discharge test results show that it has high capacity and good cycle stability. The electrochemical impedance spectra (EIS) of LiMn0.8Fe0.2PO4/C cathodes are obtained in the initial lithiation and delithiation process. It is found that the Nyquist plots of LiMn0.8Fe0.2PO4/C cathodes mainly consist of three parts in the lithiation and delithiation process, namely, high-frequency semicircle, middle-frequency semicircle, and low-frequency line. The above three parts are assigned to Schotty contact problem, charge transfer step, and lithium-ion solid-state diffusion process, respectively. A quantitative analysis of the variations of the resistance and barrier capacitance of Schotty contact with the polarization potential of the electrode and a reasonable explanation is given, as well as the resistance and space charge layer capacitance of charge transfer. Moreover, the change of n (a parameter in constant phase angle element (CPE) with a value between − 1 and 1) value is briefly discussed.

ZnO-based catalysts have been intensively studied because of their extraordinary performance in lower olefin synthesis, methanol synthesis and water–gas shift reactions. However, how ZnO catalyzes these reactions are still not well understood. Herein, we investigate the activations of CO2, O2 and CO on single crystalline ZnO polar surfaces at room temperature, through in-situ near-ambient-pressure X-ray photoelectron spectroscopy (NAP-XPS). It is revealed that O2 and CO2 can undergo chemisorption on ZnO polar surfaces at elevated pressures. On the ZnO ( 0001 ) surface, molecular CO2 (O2) can chemically interact with the top layer Zn atoms, leading to the formation of C O 2 δ - ( O 2 δ - ) or partially dissociative atomic oxygen ( O - ) and hence the electron depletion layer in ZnO. Therefore, an apparent upward band-bending in ZnO ( 0001 ) is observed under the CO2 and O2 exposure. On the ZnO ( 000 1 ¯ ) surface, the molecular chemisorbed CO2 (O2) mainly bond to the surface oxygen vacancies, which also results in an upward band-bending in ZnO ( 000 1 ¯ ). In contrast, no band-bending is observed for both ZnO polar surfaces upon CO exposure. The electron-acceptor nature of the surface bounded molecules/atoms is responsible for the reversible binding energy shift of Zn 2p3/2 and O 1s in ZnO. Our findings can shed light on the fundamental understandings of CO2 and O2 activation on ZnO surfaces, especially the role of ZnO in heterogeneous catalytic reactions.

The 4H-SiC trench metal–oxide semiconductor field-effect transistor (MOSFET) with the grounded p+ shielding region is one of the commercial devices with superior gate oxide reliability. However, the introduced JFET region seriously increases the influence of quasisaturation (QS) on device electrical performances, resulting in the poor output and transfer characteristics. In order to investigate the mechanism of QS effect, the output characteristic is physically analyzed by monitoring the variations of the electric field, the electron concentration, the electron velocity, and the depletion layer inside the cell structure. It is demonstrated that the channel electrons are injected into the JFET current path from the channel region by a forward bias to the channel and JFET junction at QS state. Moreover, based on the Lombardi CVT model, the influence of QS effect on devices with different channel electron mobilities is first studied. An improved SiC trench MOSFET with two-level doped current spreading layers is proposed to decrease the JFET resistance and suppress the QS effect. The QS current and the peak transconductance are improved by 42% and 23%, respectively. The specific ON-state resistance is decreased by 10% and the figure of merit is improved by 7%.

The reliability of the integrated circuits (ICs) has become one of the greatest challenges with the increasing complexity of the electromagnetic environment. On this basis, an explicit difference in the damage location is observed in the high-power microwave (HPM) radiated CMOS inverters. The detailed damage mechanism analysis is performed. The analysis shows that the overcurrent-dominant failure and the latch-up-dominant failure are induced in positive and negative half radiation cycle respectively, resulting in the damage location discrepancy. The depletion region current $I_{\textrm {SS}}$ and the body current $I_{\textrm {body}}$ are derived from the established theoretical charge transport model. TCAD simulations demonstrate the junctional-overcurrent and latch-up process, empirical formula is obtained to explain the damage mechanism and predict the thermal damage location. The damage dependency on interference characteristics is discussed for further understanding. Corresponding experiments are performed using the six-integrated-inverters chip. The results support the theoretical charge transport model well.

In the present article, we conceptually develop some understanding of the Peltier heat resulting at the rectifying junction between a metal and an n-type semiconductor with a depleted space charge layer (“the Schottky barrier”) as well as two Ohmic contacts between a metal and an n-type semiconductor with an enriched space charge layer, and two dissimilar metals chosen as three instructive examples via “the thought experiment,” based upon the energy band diagram of metal and semiconductor. Additionally, we briefly discussed on the difference between the contact potential and diffusion potential, both of which proved to be a thermodynamic reversible potential as well that influences greatly the Peltier coefficient. We concluded that the reduction in the kinetic energy of more energetic electrons passing through the rectifying junction as well as the two Ohmic contacts is accompanied by the Peltier heat evolution. By contrast, the enhancement in the kinetic energy of less energetic electrons passing through the rectifying junction as well as the two Ohmic contacts is associated with the Peltier heat absorption. The Peltier heat evolution and absorption resulting at the rectifying junction as well as the two Ohmic contacts can be well understood in terms of reduction/enhancement in the kinetic energy of electrons crossing the junction, respectively, under the isothermal constraint of a couple of junctions. The rectifying junctions provide Peltier effects more markedly than the two Ohmic contacts. This idea provides in particular a basis for the thermoelectric generator (batteries) and it can be extended to other rectifying junctions such as a p-n junction and another Ohmic contact between metal and p-type semiconductor with an enriched space charge layer.

Boron-doped diamond (B-diamond) metal–oxide–semiconductor (MOS) capacitor and MOS field-effect transistor (MOSFET) are fabricated on a flat diamond epitaxial layer. Their electrical properties and thermal stabilities after annealing at 500 °C are investigated. Annealing makes the leakage current density of the B-diamond MOS capacitor increase slightly. There is a larger stretch-out for the capacitance-voltage curve in the depletion region after annealing than that before annealing. The drain-current maxima for the as-fabricated and 500 °C-annealed MOSFETs are obtained as −0.49 and −0.60 mA/mm, respectively. Extrinsic transconductance maxima are 18.7 and $21.4~\mu \text{S}$ /mm, respectively. These obtained values are considerably larger than those obtained by the previously reported B-diamond MOSFETs.

All-solid-state lithium batteries (ASSLBs) have advantages of safety and high energy density, and they are expected to become the next generation of energy storage devices. Sulfide-based solid-state electrolytes (SSEs) with high ionic conductivity and low grain boundary resistance exhibit remarkable practical application. However, the space charge layer (SCL) effect and high interfacial resistance caused by a mismatch with the current commercial oxide cathodes restrict the development of sulfide SSEs and ASSLBs. This review summarizes the research progress on the SCL effect of sulfide SSEs and oxide cathodes, including the mechanism and direct evidence from high performance in-situ characterizations, as well as recent progress on the interfacial modification strategies to alleviate the SCL effect. This study provides future direction to stabilize the high performance sulfide-based solid electrolyte/oxide cathode interface for state-of-the-art ASSLBs and future all-SSE storage devices.

In this paper, a 2D analytical potential model for n + SiGe Gate stacked linearly graded work function Vertical TFET (n + SiGe GS-LGW-VTFET) is developed with incorporating the effect of source and drain depletion region towards the channel. The proposed novel structure is developed from linearly graded for equalizing disruption of the work function having symmetric potential distribution effect on the device channel, which noticeably improve the device performance by reducing the short channel effect. The Poisson equation is solved in terms of channel surface potential and electric field using the parabolic approximation approach. This model also used some accurate analysis by employing the SiO2 and HfO2 with gate stacking method in order to increase the better gate control over the channel length. This model can initially forecast with the effect of gate-source voltage (Vgs) and drain-source voltage (Vds) thereafter gate oxide thickness, linearly graded work function, and SiGe mole fraction. The electric field is derived using the surface potential model, and thereafter, in order to extract the drain current characteristics, our suggested model accounts for the variables of the Kane model by integrating the band-to-band tunneling generation rate over the tunneling region. The proposed model efficiency has been confirmed by the drive characteristics of our model are in coincides nicely with that of simulation results.

Herein we introduce and investigate a new architectural design strategy for planar single gate field effect transistors (SG-FETs) that delivers advantages from all fronts of design, fabrication and performance perspectives. The amalgamation of schottky buried metal layer (BML) and charge plasma (CP) mechanism of doping in planar single gate architecture yields a novel type of FET called as CP-BML FET. Owing to the schottky BML induced depletion region created on the bottom side of device layer reduces effective device layer thickness (TSi) suppressing short channel effects (SCEs) including drain induced barrier lowering (DIBL) and threshold voltage roll-off. The proposed FET has been analyzed for DC and RF performance figure of merits (FOMs) and compared to counter part state of the art technologies with reference to ITRS performance projections. The proposed FET is also investigated the performance FOMs on for criticality of physical parameters including gate length (Lg), device layer thickness (TSi), BML workfunction (ϕBML). The ION and IOFF for proposed device at Lg = 20nm read at 730μ A/μ m and 7 × 10− 2 pA/μ m respectively. RF performance analysis reveal transition frequency (ft) of 390 GHz with SS $\simeq \ \text {75mV/dec}$ coherent with ITRS performance projections. It is found that ultra scaled (7 nm) proposed device exhibits intrinsic delay τ of 0.6 ps which is superior to ITRS projections of 1.71 ps at 28 nm technology node. The proposed device yields Pdyn of 0.248 fJ/μ m at Lg= 7nm implicating it to be potential candidate for low power with high performance application requirements.

The Fourier-series-based insulated-gate bipolar transistor (IGBT) model has been very effective in simulating its switching behaviors and meanwhile, reflecting carrier dynamics. However, in turn-on process, such a model has difficulty in distinguishing the boundary between undepleted area and depletion layer of the drift region due to Gibbs phenomenon and therefore, cannot accurately describe the carrier behavior of carrier storage region (CSR). In this study, the Fourier-series-based model is modified to determine the more precise depletion layer edge for turn on. This is achieved by utilizing the actual characteristics of the carrier concentration gradient at the edge of CSR in turn-on process. Such a modified model is implemented in MATLAB/Simulink and it can better reflect the depletion layer and simulate the distribution of both the carrier concentration and electric field during turn-on process. It corrects the unreasonable voltage tail caused by the error of drift region voltage calculation in previous models. The results of the proposed model under both the resistive load and inductive load are in good agreement with TCAD. Such a modified model can more accurately simulate both carrier dynamics and switching behaviors in the turn-on process.

Flexible Cu2ZnSnSe4 (CZTSe) solar cells gradually attract much attention due to their low-cost, lightweight, and environmentally friendly features. However, the efficiency of flexible CZTSe solar cells obtained through the nonvacuum green electrodeposition process remains sluggish (3.82%), far away from that obtained from other methods (∼10% by magnetron sputtering). Herein, a championed 6.33% efficiency of flexible CZTSe solar cells prepared by the electrodeposition process is achieved through an in situ electrochemical treatment (ET) process. It is found that the ET process drives the formation of a thin MoOx layer, evoking a series of beneficial results, thus accounting for an enhancement in photovoltaic performance. With the ET process, the MoSe2 thickness is compressed and Cu- and Sn-related undesirable defects/secondary phases are inhibited, leading to improved film quality. Additionally, it prolongs the depletion region width and minority lifetime, accelerates the charge separation and collection, relieves the band tails, and favorably reverses the band bending from downward to upward at/near grain boundaries. With these effects, the efficiency increases from 4.21% to 6.33%, far beyond the highest reports on electrodeposited flexible CZTSe solar cells. Our findings offer a promising way to improving Mo foil-based flexible devices and mark a significant breakthrough for the development of electrodeposition-processed flexible CZTSSe-based solar cells.

This article describes an analysis of the electric-field-dependence mechanism for cosmic ray failure in power semiconductor devices. Two major modes for the failure have been reported. One is bipolar transistor activation caused by carrier generation from impact ionization at the n−/n+ boundary. The other is Joule heating generated by an avalanche current in high electric fields. We clarified that a bipolar transistor activation mode had not occurred even under high electric field conditions for the drift layer width used in lower-voltage-class insulated-gate bipolar transistors (IGBTs) by evaluating the drift layer thickness dependence of the failure in time (FIT) in 1700 V devices from punchthrough to non-punchthrough with and without a p+ collector layer. We also clarified that the electric field averaged over the depletion layer width (applied voltage divided by the depletion layer width) is the critical factor for failure, rather than the maximum electric field, for the first time by observing a universal curve of the average electric field dependence of FIT in 750–6500 V IGBTs and diodes. To improve the cosmic ray durability of power semiconductor devices, lowering the electric field averaged over the depletion layer width is effective for device design.

Black silicon (b-Si) surfaces typically have a high density of extreme nanofeatures and a significantly large surface area. This makes high-quality surface passivation even more critical for devices such as solar cells with b-Si surfaces. It has been hypothesized that conformal dielectrics with a high fixed charge density ( ${{\boldsymbol{Q}}_{\boldsymbol{f}}}$ ) are preferred as the nanoscale features of b-Si result in a significant enhancement of field-effect passivation. This article uses 1-D, 2-D, and 3-D numerical simulations to study surface passivation of b-Si, where we particularly focus on the charge carrier control by | ${{\boldsymbol{Q}}_{\boldsymbol{f}}}$ | up to 1 × 1013 cm−2 under accumulation conditions. We will show that there is a significant space charge region compression in b-Si nanofeatures, which affects the charge carrier population control for moderate | ${{\boldsymbol{Q}}_{\boldsymbol{f}}}$ | up to a1 × 1012 cm−2. The average surface minority charge carrier density can be reduced by 70% in some cases, resulting in an equivalent reduction in area-normalized surface recombination losses if the effective surface recombination velocity ( ${{\boldsymbol{S}}_{{\rm{eff}}}}$ ) is limited by minority carriers. This provides a possible solution for the empirical ${{\boldsymbol{S}}_{{\rm{eff}}}} \propto 1/{\boldsymbol{Q}}_{\boldsymbol{f}}^4$ reported previously. We will also show that the situation is more complicated for surface passivation films where the ratio between the electron and hole capture cross section ( ${{\boldsymbol{\sigma }}_{\boldsymbol{n}}}$ / ${{\boldsymbol{\sigma }}_{\boldsymbol{p}}}$ ) is higher than 10 for p -type surfaces. For commonly used surface passivation films with a | ${{\boldsymbol{Q}}_{\boldsymbol{f}}}$ | larger than a1 × 1012 cm−2, there is little space charge compression for b-Si. Consequently, ${{\boldsymbol{S}}_{{\rm{eff}}}}$ simply scales with the surface area, i.e., there is no enhanced reduction of surface recombination by field-effect passivation on b-Si.

The electrical characteristics and photoresponse of the “carbon nanofilm on silicon” heterostructure obtained by laser-pulsed deposition have been investigated. The thickness of the carbon nanofilm is selected from the condition of the maximum antireflection effect of the substrate. It was found that the obtained junction is rectifying with a rectifying coefficient of 35 at 1 V. The direct current-voltage characteristic from 0.1 V to 0.35 V is in satisfactory agreement with the expression J = J0exp(eU/ηkT). An increase in voltage in the forward direction leads to the appearance of currents limited by the space charge (J = AU2). Linearization of the C–2–U dependence indicates the sharpness of the impurity distribution in the space charge region. The mechanism of the photoresponse of the heterostructure is similar to the photoresponse of anisotype heterostructures with the ‘window’ effect. The long-wavelength edge (1.1 μm) of the photosensitivity is determined by the silicon substrate, and absorption in the carbon nanofilm leads to an additional expansion of the photosensitivity region. The heterostructure has uniform photosensitivity at the level 0.8 in the wavelength range of 0.55–1.1 µm. The short-wavelength tail reaches up to 0.4 µm.