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51. Emerging Nanotechnology for Integration of Nanostructures in Nanoelectronic Devices

Author

Baron, Thierry, Agraffeil, Claire, Dhalluin, Florian, Kogelschtaz, Martin, Cunge, Gilles, Chevolleau, Thierry, Salem, Bassem, Salhi, Billel, Abed, Hicehm, Potié, Alexis, Latu-Romain, Laurence, Ternon, Céline, Aissou, Karim, Montès, Laurent, Mur, Pierre, Molas, Gabriel, de Salvo, Barbara, Jalaguier, Eric, Ernst, Thomas, Ferret, Pierre, Gentile, Pascal, Pauc, Nicolas, Laboratoire des technologies de la microélectronique (LTM), Université Joseph Fourier - Grenoble 1 (UJF)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Centre National de la Recherche Scientifique (CNRS), Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information (CEA-LETI), Direction de Recherche Technologique (CEA) (DRT (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA), Silicon Nanoelectronics Photonics and Structures (SiNaps), PHotonique, ELectronique et Ingénierie QuantiqueS (PHELIQS), Université Grenoble Alpes [2016-2019] (UGA [2016-2019])-Institut de Recherche Interdisciplinaire de Grenoble (IRIG), Direction de Recherche Fondamentale (CEA) (DRF (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Direction de Recherche Fondamentale (CEA) (DRF (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Université Grenoble Alpes [2016-2019] (UGA [2016-2019])-Institut de Recherche Interdisciplinaire de Grenoble (IRIG), and ANR-06-NANO-0070,PREAANS,PRopriétés Electroniques d'Assemblages Autoorganisés à base de Nanofils(2006)

Subjects
[PHYS]Physics [physics], Fabrication, Materials science, Nanostructure, Nanowire, Copolymer, Nanotechnology, Nanodot, Chemical vapor deposition
Abstract

This chapter focuses on two emerging nanotechnologies developed to fabricate, organize and integrate nanomaterials (nanodots, nanowires) in nanoelectronics devices. The first one uses the natural properties of diblock copolymers to create (i) a hexagonal lattice array of vertical PMMA cylinders in a polystyrene (PS) matrix, or (ii) an ordered array of horizontal PMMA cylinders in a PS matrix. These films are then used as deposition and/or etching masks to produce dense lattices of 20 nm diameter nanoparticles and nanowires with a density of around 1011 cm-2. The chapter presents examples of integration with an 8-inch wafer memory technology. The second technology is based on chemical vapor deposition (CVD) of basic nanomaterial building blocks for future microelectronics. The chapter focuses on CVD growth of silicon nanostructures using a fully compatible CMOS process. The resulting nano-objects are integrated in test devices and measured electrically.

Published
2010

53. A New Method to Induce Tensile Stress in Silicon on Insulator Substrate: From Material Analysis to Device Demonstration

Author

Maitrejean, Sylvain, primary, Loubet, Nicolas, additional, Augendre, Emmanuel, additional, Morin, Pierre Francois, additional, Reboh, Shay, additional, Bernier, Nicolas, additional, Wacquez, Romain, additional, Lherron, Benoit, additional, Bonnevialle, Aurore, additional, Liu, Qing, additional, Hartmann, Jean-Michel, additional, He, Hong, additional, Halimaoui, Aomar, additional, Li, Juntao, additional, Pilorget, Sonia, additional, Kanyandekwe, Joel, additional, Grenouillet, Laurent, additional, Chafik, Fadoua, additional, Morand, Yves, additional, Le Royer, Cyrille, additional, Faynot, Oliver, additional, Celik, Muhsin, additional, Doris, Bruce, additional, and de Salvo, Barbara, additional

Published
2015
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57. A Novel Programming Technique to Boost Low-Resistance State Performance in Ge-Rich GST Phase Change Memory

Author

Kiouseloglou, Athanasios, primary, Navarro, Gabriele, additional, Sousa, Veronique, additional, Persico, Alain, additional, Roule, Anne, additional, Cabrini, Alessandro, additional, Torelli, Guido, additional, Maitrejean, Sylvain, additional, Reimbold, Gilles, additional, De Salvo, Barbara, additional, Clermidy, Fabien, additional, and Perniola, Luca, additional

Published
2014
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59. Interface Engineering of Ag-${\rm GeS}_{2}$-Based Conductive Bridge RAM for Reconfigurable Logic Applications

Author

Palma, Giorgio, primary, Vianello, Elisa, additional, Thomas, Olivier, additional, Suri, Manan, additional, Onkaraiah, Santhosh, additional, Toffoli, Alain, additional, Carabasse, Catherine, additional, Bernard, Mathieu, additional, Roule, Anne, additional, Pirrotta, Onofrio, additional, Molas, Gabriel, additional, and De Salvo, Barbara, additional

Published
2014
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62. Study of resistive random access memory based on TiN/TaOx/TiN integrated into a 65nm advanced complementary metal oxide semiconductor technology

Author

Diokh, Therese, primary, Le-Roux, Elise, additional, Jeannot, Simon, additional, Cagli, Carlo, additional, Jousseaume, Vincent, additional, Nodin, Jean-François, additional, Gros-Jean, Mickaël, additional, Gaumer, Clement, additional, Mellier, Maxime, additional, Cluzel, Jacques, additional, Carabasse, Catherine, additional, Candelier, Philippe, additional, and De Salvo, Barbara, additional

Published
2013
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68. Electrical Behavior of Phase-Change Memory Cells Based on GeTe

Author

Perniola, Luca, primary, Sousa, Veronique, additional, Fantini, Andrea, additional, Arbaoui, Edrisse, additional, Bastard, Audrey, additional, Armand, Marilyn, additional, Fargeix, Alain, additional, Jahan, Carine, additional, Nodin, Jean-Francois, additional, Persico, Alain, additional, Blachier, Denis, additional, Toffoli, Alain, additional, Loubriat, Sebastien, additional, Gourvest, Emanuel, additional, Betti Beneventi, Giovanni, additional, Feldis, Helene, additional, Maitrejean, Sylvain, additional, Lhostis, Sandrine, additional, Roule, Anne, additional, Cueto, Olga, additional, Reimbold, Gilles, additional, Poupinet, Ludovic, additional, Billon, Thierry, additional, De Salvo, Barbara, additional, Bensahel, Daniel, additional, Mazoyer, Pascale, additional, Annunziata, Roberto, additional, Zuliani, Paola, additional, and Boulanger, Fabien, additional

Published
2010
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69. CVD Growth and Passivation of W and TiN Nanocrystals for Non-volatile Memory Applications

Author

Gay, Guillaume, primary, Belhachemi, Djamel, additional, Colonna, Jean-Philippe, additional, Minoret, Stéphane, additional, Beaurain, Arnaud, additional, Pelissier, Bernard, additional, Roure, Marie-Christine, additional, Lafond, Dominique, additional, Jalaguier, Eric, additional, Molas, Gabriel, additional, Baron, Thierry, additional, and De Salvo, Barbara, additional

Published
2010
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80. Interface Engineering of Ag-GeS2-Based Conductive Bridge RAM for Reconfigurable Logic Applications.

Author

Palma, Giorgio, Vianello, Elisa, Thomas, Olivier, Suri, Manan, Onkaraiah, Santhosh, Toffoli, Alain, Carabasse, Catherine, Bernard, Mathieu, Roule, Anne, Pirrotta, Onofrio, Molas, Gabriel, and De Salvo, Barbara

Subjects
ADAPTIVE computing systems, RANDOM access memory, ELECTRIC switchgear, FIELD programmable analog arrays, GATE array circuits
Abstract

In this paper, we show performance and reliability improvement of Ag-GeS2-based conductive bridge RAM (CBRAM) devices by addition of a 2-nm-thick HfO2 layer between the electrolyte and the W bottom electrode. Our optimized dual-layer electrolyte stack (2-nm HfO2\--30\-nm~GeS2) leads to a resistance ratio (ROFF/RON) higher than 10^6 and projected 10 years read disturb immunity at 0.04 V. The improved memory resistance ratio is explained by means of physical modeling. Using compact modeling and circuit level simulations, we show that our optimized CBRAM device, integrated in a 1T-2R architecture, fits well with the aggressive requirements of field programmable gate array-type reconfigurable applications. Nonvolatility, back-end-of-line compatibility, and 1.3-nA leakage current during continuous reverse read operation at 1 V are strong benefits demonstrated on our device for such applications. [ABSTRACT FROM AUTHOR]

Published
2014
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81. Detailed Analysis of the Role of Thin-HfO2 Interfacial Layer in Ge2Sb2Te5-Based PCM.

Author

Hubert, Quentin, Jahan, Carine, Toffoli, Alain, Delaye, Vincent, Lafond, Dominique, Grampeix, Helen, and de Salvo, Barbara

Subjects
PULSE-code modulation, THIN films, GERMANIUM compounds, PHASE change materials, RECORDS management, ELECTRIC currents
Abstract

In this paper, we show that performances of Ge2Sb2Te5-based phase-change memory (PCM) cells can be improved by the insertion of a thin HfO2 interfacial layer between the phase-change material and the tungsten plug. Significant reduction of the RESET and SET currents and of the energy required to switch the PCM cells are demonstrated. In addition, compared with pure GST reference cells, the presence of the HfO2 layer leads to an enhanced endurance (>10^8~cycles) and an improved data-retention (ten years at 172^\circC). Using cross-sectional TEM-Energy Dispersive X-Ray (EDX) analyses and technology computer-aided design simulations, the decreases of the programming currents and energy are explained through the reduction of the PCM cell active area, due to the creation of conductive paths in the HfO2 layer during the initial forming procedure. Electrical measurements and modeling of the forming procedure indicate that the size of the conductive paths is controlled by the maximum current flowing through the PCM cells during the current overshoot of the forming procedure. [ABSTRACT FROM AUTHOR]

Published
2013
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82. Assessment of Self-Induced Joule-Heating Effect in the I–V Readout Region of Polycrystalline \Ge2\Sb2\Te5 Phase-Change Memory.

Author

Betti Beneventi, Giovanni, Perniola, Luca, Hubert, Quentin, Gliere, Alain, Larcher, Luca, Pavan, Paolo, and De Salvo, Barbara

Subjects
RESISTANCE heating, POLYCRYSTALS, CHALCOGENIDES, PHASE change materials, RANDOM access memory, ELECTRON transport, ELECTRIC conductivity, MATHEMATICAL models
Abstract

The physical mechanisms that regulate carrier transport in polycrystalline chalcogenides, such as \Ge2\Sb2\Te5 (GST), are still debated. Recently, self-induced Joule-heating (SJH) effect has been claimed to be the key factor in explaining the nonlinearity of the I–V characteristics of polycrystalline GST-based phase-change memory (PCM). In this paper, we carefully investigate the SJH occurring in the GST material by analyzing the I–V characteristics of PCM cells at low voltages, i.e., in the memory-cell readout region. To accomplish the study, we use ad hoc fabricated PCM devices allowing an easier evaluation of SJH occurring in the chalcogenide layer. A novel procedure to test the SJH effect is also proposed. A comparison between numerical simulations and compact modeling is discussed as well. Our paper shows that the SJH effect is not sufficient to reproduce the experimental I–V nonlinearity, claiming for new experiments and theoretical investigations. Therefore, this paper can be considered a step forward toward the comprehension of the transport properties of polycrystalline GST, which is a key aspect for robust modeling of PCM devices. [ABSTRACT FROM PUBLISHER]

Published
2012
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83. From Atomistic to Device Level Investigation of Hybrid Redox Molecular/Silicon Field-Effect Memory Devices.

Author

Pro, Tiziana, Buckley, Julien, Barattin, Régis, Calborean, Adrian, Aiello, Venera, Nicotra, Giuseppe, Huang, Kai, Gély, Marc, Delapierre, Guillaume, Jalaguier, Eric, Duclairoir, Florence, Chevalier, Nicolas, Lombardo, Salvatore, Maldivi, Pascale, Ghibaudo, Gérard, De Salvo, Barbara, and Deleonibus, Simon

Abstract

In this paper, an extensive investigation of hybrid molecular/Si field-effect memories is presented, where redox ferrocene (Fc) molecules play the role of the memory charge storage nodes. Engineering of the organic linkers between Fc and Si is achieved by grafting Fc with different linker lengths. The study shows a clear correlation between results from atomistic computational density functional theory, electrochemical measurements (cyclic voltammetry) and electrical data obtained by a detailed study on capacitors and pseudo-MOS devices. Physical–chemical analyses (atomic force microscopy, high-resolution transmission electron microscopy, and X-ray photoelectron spectroscopy), corroborate the quality of molecular layers on devices. [ABSTRACT FROM PUBLISHER]

Published
2011
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85. Experimental and Theoretical Investigation of Nano-Crystal and Nitride-Trap Memory Devices.

Author

De Salvo, Barbara, Ghibaudo, Gerard, Pananakakis, G., Masson, Pascal, Baron, Thierry, Buffet, Nicholas, Fernandes, Antoine, and Guillaumot, Bernard

Subjects
*FERROELECTRIC RAM, *SEMICONDUCTORS, *NITRIDES
Abstract

Proposes an experimental and theoretical investigation of memory-cell structures employing discrete-trap type storage nodes, using either natural nitride traps or semiconductor nano-crystals. Background on the use of discrete-trap storage nodes in memory devices; Methodology; Results and discussion.

Published
2001
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86. Charge Localization during Program and Retention in Nitrided Read Only Memory-Like Nonvolatile Memory Devices

Author

Nowak, Etienne, Vianello, Elisa, Perniola, Luca, Bocquet, Marc, Molas, Gabriel, Kies, Rabah, Gely, Marc, Ghibaudo, Gerard, De Salvo, Barbara, Reimbold, Gilles, and Boulanger, Fabien

Abstract

An alternative solution to standard Flash memories is represented by nitride-trap memories as silicon--oxide--nitride--oxide--silicon (SONOS) or nitrided read only memory (NROM) memories. However these structures are facing retention issues at high temperature and a quantitative analysis of the location of the charge during program and retention is required. This work investigates the location of charge of NROM Nonvolatile memory devices in order to evaluate the trapped charge distribution in program and retention conditions for Si3N4, Al2O3, and HfO2trapping layers. During programming, the charge is initially injected on a 40--60-nm-length region in the trapping layer, then after reaching a trapped charge saturation level, it broadens. The charge saturation level is explained through electrostatic considerations and not by a limit of available number of traps. During retention, the lateral migration (inside the trapping layer) and vertical migration (charge loss) of the trapped charge are quantitatively evaluated. Thanks to a one-dimensional (1D) drift model, the characterization of lateral migration at room temperature is put in relation to the trap properties of Si3N4, Al2O3, and HfO2layers.

Published
2010
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87. (Invited) Germanium Enrichment for Planar-, Fin- and Nanowire-Channel MOSFETs Made on SOI

Author

Augendre, Emmanuel, Loubet, Nicolas, Morin, Pierre Francois, Liu, Qing, Schmitt, Joël, L'Herron, Benoît, Nguyen, Phuong, Barraud, Sylvain, Hutin, Louis, Maitrejean, Sylvain, De Salvo, Barbara, Coquand, Rémi, Reboh, Shay, Venigalla, Rajasekhar, Doris, Bruce, Yamashita, Tenko, Faynot, Olivier, and Vinet, Maud

Abstract

This paper discusses the fabrication of SiGe channel for Ultra-Thin Body and Buried oxide Fully Depleted Silicon-On-Insulator (UTBB FDSOI) MOSFETs, FinFETs and Nano Wire FETs (NWFETs). Enrichment conditions need to be tuned to avoid excessive Ge pile-up on tensile-strained planar Si films due to lower Ge diffusion. Patterning SiGe Fins in thick blanket SiGe layers faces the crystal quality limits set by plastic relaxation beyond critical thickness. As an alternative, Ge enrichment of pre-existing Si Fins requires conformal SiGe growth and can produce strained SiGe Fins up to 50% without significant relaxation, independently from Fin height. Enrichment requirements for NWFETs are identical to those of planar devices. As a result, NWFETs benefit from both SiGe mechanical stability and uniaxial compressive strain performance enhancement.

Published
2016
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88. (Invited) Non-Volatile Resistive Memory: Technology Capable of Revolutionary Compromises

Author

Navarro, Gabriele, Vianello, Elisa, Sousa, Véronique, Molas, Gabriel, Nowak, Etienne, De Salvo, Barbara, and Perniola, Luca

Abstract

Non-Volatile Resistive Memory (NVRM) such as Phase-Change Memory, Oxide-based Memory and Conductive Bridging Memory has rapidly increased in maturity in the last decade. In a memory market context dominated by DRAM and Flash technologies, the evolving memory hierarchy and the strong differentiation of the applications portfolio represent a real opportunity for NVRM to emerge. The real revolution of this technology resides in its versatility made possible by general trade-offs existing between the different NVRM performances, highlighted in the last years by the research and the development in several fields (e.g. materials science, engineering, etc.). We present here some of these trade-offs, and how they can be used to target specific applications.

Published
2016
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89. (Keynote) Oxide based Resistive Memories for Low Power Embedded Applications and Neuromorphic Systems

Author

Vianello, Elisa, Garbin, Daniele, Jovanovic, Natalija, Bichler, Olivier, Thomas, Olivier, de Salvo, Barbara, and Perniola, Luca

Abstract

Oxide based resistive memories (OxRAMs) is one of the potential candidates for non-volatile logic circuits and neuromorphic circuits in the applications of wearable devices, internet of things (IoT), cloud computing, and big-data processing. One of the main OxRAMs issue is the noise behavior of the high resistance state (HRS). In this work, we will demonstrate a hybrid (CMOS logic plus ReRAM devices) Non Volatile Flip Flop designed to face OxRAM variability. Concerning neuromorphic circuits, we will focus on the impact of resistance variability on the performance of Convolutional Neural Network (CNN) systems for visual pattern recognition applications.

Published
2015
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90. A New Method to Induce Tensile Stress in Silicon on Insulator Substrate: From Material Analysis to Device Demonstration

Author

Maitrejean, Sylvain, Loubet, Nicolas, Augendre, Emmanuel, Morin, Pierre Francois, Reboh, Shay, Bernier, Nicolas, Wacquez, Romain, Lherron, Benoit, Bonnevialle, Aurore, Liu, Qing, Hartmann, Jean-Michel, He, Hong, Halimaoui, Aomar, Li, Juntao, Pilorget, Sonia, Kanyandekwe, Joel, Grenouillet, Laurent, Chafik, Fadoua, Morand, Yves, Le Royer, Cyrille, Faynot, Oliver, Celik, Muhsin, Doris, Bruce, and de Salvo, Barbara

Abstract

Here, we demonstrate a new process to fabricate tensily strained Si On Insulator substrates (sSOI). The process is based on the epitaxial growth of Si1-xGexon SOI substrate, the partial amorphization and crystallization of the Si / Si1-xGexbilayers and the selective removal of the top Si1-xGexfilm. Si tensile stress higher than 1.4 GPa is obtained. Complementary Metal Oxide Semiconductor Fully Depleted- SOI (CMOS FD-SOI) devices at 14 nm node design rules were fabricated on top of such substrate. For nFET devices, improvement in mobility is demonstrated with respect to devices built on standard SOI substrates.

Published
2015
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91. Mechanical Analyses of Extended and Localized UTBB Stressors Formed with Ge Enrichment Techniques

Author

Morin, Pierre Francois, Grenouillet, Laurent, Loubet, Nicolas, Pofelski, Alexandre, Lu, Darsen, Liu, Qing, Augendre, Emmanuel, Maitrejean, Sylvain, Fiori, Vincent, de Salvo, Barbara, Doris, Bruce, and Kleemeier, Walter

Abstract

Germanium enrichment process also known as condensation can be used for the integration of stressors in the fully depleted silicon on insulator technology. Using multi-physics modeling combined with advanced TEM characterization we studied the formation of stressors with condensation. We first observed in blanket 1D structures that the diffusion rate is substantially reduced during Ge condensation compared to the typical diffusion in neutral atmosphere. We postulate this is due to the injection of interstitial at the oxide/SiGe interface and to a reduced stress effect on the kinetics. We then studied self-aligned in plane stressors (SAIPS) formed in the source/drain region using localized Ge condensation. It is shown that the SAIPS methodology almost doubles the channel stress generated by the source drain stressor. Combining Si0.65Ge0.35and SAIPS source/drain stressors with in-situ Si0.79Ge0.21strained channel allows achieving a stress of -2 GPa in the p-type channel with gate first architecture.

Published
2015
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93. (Invited) Investigation of Frenkel-Pair Formation in HfO2and Its Influence on OxRAM Memory Reliability

Author

Vianello, Elisa, Blaise, Philippe, Traoré, Boubacar, Xue, Kanhao, Fonseca, Leonardo, Molas, Gabriel, de Salvo, Barbara, Perniola, Luca, and Nishi, Yoshio

Abstract

In this work we combine experimental data and first principles calculations to investigate the conductive filament (CF) creation in HfO2based resistive switching memories. First, we propose that the CF in HfO2-based resistive OxRAMs is due to HfOxsub-oxides, possibly assuming a tetragonal symmetry with x≤1.5. Second, we demonstrate that Frenkel-Pair formation is favored by electron injection and by the adoption of oxygen reactive electrodes with low work function, such as Ti. Finally, endurance tests on a memory cell with Ti as the top electrode were performed to assess its cycling stability. Endurance up to 108cycles with optimized set conditions has been demonstrated.

Published
2014
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94. Study of resistive random access memory based on TiN/TaOx/TiN integrated into a 65nm advanced complementary metal oxide semiconductor technology

Author

Diokh, Therese, Le-Roux, Elise, Jeannot, Simon, Cagli, Carlo, Jousseaume, Vincent, Nodin, Jean-François, Gros-Jean, Mickaël, Gaumer, Clement, Mellier, Maxime, Cluzel, Jacques, Carabasse, Catherine, Candelier, Philippe, and De Salvo, Barbara

Subjects
*NONVOLATILE random-access memory, *TITANIUM nitride, *TANTALUM oxide, *COMPLEMENTARY metal oxide semiconductors, *METAL-insulator-metal structures, *STOICHIOMETRY
Abstract

Abstract: In this work, cells based on TiN/TaOx/TiN metal–insulator–metal structure, fabricated in a 65nm complementary metal oxide semiconductor technology, are investigated in order to propose a good stack candidate for multiple time programmable (MTP) applications. Firstly, the oxide material thickness and stoichiometry are optimized to minimize the forming voltage and the RESET current. Programming energies of the devices under different current compliance during the SET operation and with different cell size are studied putting in evidence the filamentary mechanism. Very high speed and low voltage for the ON (SET) operation are demonstrated. High thermal stability up to 125°C is demonstrated in the SET/RESET states of the device (with an ROFF/RON ~100). Promising data retention exceeding 24h at 250°C is also shown. Finally, due to the stability of this device, the high potential of TaOx-based resistive random access memory for MTP applications is demonstrated. [Copyright &y& Elsevier]

Published
2013
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