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Due to the fast-growing number of connected tiny devices to the Internet of Things (IoT), providing end-to-end security is vital. Therefore, it is essential to design the cryptosystem based on the requirement of resource-constrained IoT devices. This article presents a lightweight advanced encryption standard (AES), a high-secure symmetric cryptography algorithm, implementation on field-programmable gate array (FPGA) and 65-nm technology for resource-constrained IoT devices. The proposed architecture includes 8-bit datapath and five main blocks. We design two specified register banks, Key-Register and State-Register, for storing the plain text, keys, and intermediate data. To reduce the area, Shift-Rows is embedded inside the State-Register. To adapt the Mix-Column to 8-bit datapath, we design an optimized 8-bit block for Mix-Columns with four internal registers, which accept 8-bit and send back 8-bit. Also, a shared optimized Sub-Bytes is employed for the key expansion phase and encryption phase. To optimize Sub-Bytes, we merge and simplify some parts of the Sub-Bytes. To reduce power consumption, we apply the clock gating technique to the design. Application-specific integrated circuit (ASIC) implementation results show a respective improvement in the area over the previous similar works from 35% to 2.4%. Based on the results, the proposed design is a suitable cryptosystem for tiny IoT devices.

Personalized recommendation systems are gaining significant traction due to their industrial importance. An important building block of recommendation systems consists of what is known as the embedding layers, which exhibit a highly memory-intensive characteristics. Fundamental primitives of embedding layers are the embedding vector gathers followed by vector reductions, which exhibit low arithmetic intensity and becomes bottlenecked by the memory throughput. To address this issue, recent proposals in this research space employ a near-data processing (NDP) solution at the DRAM rank-level, achieving a significant performance speedup. We observe that prior NDP solutions based on rank-level parallelism leave significant performance left on the table, as they do not fully reap the abundant data transfer throughput inherent in DRAM datapaths. Based on the observation that the datapath of the DRAM has a hierarchical tree structure, we propose a novel, fine-grained NDP architecture for recommendation systems, which augments the DRAM datapath with an “in-DRAM” reduction unit at the DDR4/5 rank/bank-group/bank level, achieving significant performance improvements over state-of-the-art approaches. We also propose hot embedding-vector replication to alleviate the load imbalance across the reduction units.

Arithmetic modules usually have a significant impact on performance, circuit area, energy, and power in digital circuits of DSP (Digital Signal Processing). Exploring implementation trade-offs in these circuits is of utmost importance in low-power and low-cost devices such as sensors in IoT devices which often have stringent requirements. Multipliers are of particular concern due to their ubiquitous use in DSP algorithms and their inherent implementation complexity. This work proposes a framework to efficiently generalize and explore different compositions of arithmetic operators with an emphasis on parallel binary multipliers, guiding the designer through the micro-architecture development. Several partial product encoders were combined with multiple compression trees to generate multipliers that were synthesized in a commercial 65 nm to obtain area, power, and timing results.

The tunnel field-effect transistor (TFET) is a promising solution for high energy-efficient circuits. Based on the band-to-band tunneling (BTBT) condition, fast switching characteristic with a steep subthreshold swing (SS) in the ultralow-voltage operation is feasible. Our prior work has demonstrated that the SS and ON-state current can be improved without leakage current penalty through the usage of SiGe low-bandgap material in the epitaxial tunnel layer (ETL). ETL-TFET is highly compatible with the CMOS process, enabling heterogeneous integration of TFET and MOSFET in the same technology. In this work, the circuit performance of ETL-TFET and fully depleted SOI (FDSOI) MOSFET is evaluated and compared in terms of energy and delay metrics. By combining the advantages of TFET and MOSFET, heterogeneous pMOS-NTFET dynamic logic gates are proposed. The pMOS-NTFET-based logic gates demonstrate the lowest energy consumption than other realizations. Asynchronous datapath is leveraged to combat the timing variations in the ultralow-voltage region. A 20.9%–33.9% energy reduction is achieved compared with the conventional MOSFET counterpart.

This paper presents a low-power, programmable acoustic signal processor for hearing assistive devices with speech intelligibility enhancement. The reprogrammable design provides considerable flexibility for the devices to deal with personal conditions of hearing loss. A spectral-change enhancement (SCE) algorithm is implemented to improve speech intelligibility. The power consumption is minimized by adding dedicated hardware accelerators. The short-time objective intelligibility (STOI) measure is utilized for optimizing the datapath architecture. Optimization on the critical MAC operations results in 34% power and area reductions when compared to the direct-mapped design. A 50% reduction in SRAM storage is also achieved owing to the reduced memory storage for the associated MAC operations. With the aid of the optimized MAC unit and data buffer, the overall execution time is reduced by 99.2%. Designed in a 40-nm CMOS technology, the processor integrates 431k gates in area of 0.3 mm2. The design dissipates 1.5 mW at a clock frequency of 10.5 MHz from a 0.7V supply, with a processing latency of 1.05 ms.

Diverse applications of Deep convolution neural networks (CNNs), such as image classification, semantic segmentation, video recognition, etc., in smart systems require high-throughput acceleration for real-time performance. Such CNNs when realized on edge devices of the Internet of Things, a power/energy-efficient compute platform is required, which can meet the limited power/energy budget of the devices. In this regard, an end-to-end power-optimized acceleration for the compute-intensive CNNs is proposed in this work. The proposed architecture, termed WinDConv, introduces a scheme to support both regular and energy-efficient Winograd convolutions on the same architecture through a fused datapath. Furthermore, using a thoroughly investigated data sparsity enhancement, the data reuse scheme, and a suitable memory hierarchy for power efficiency, the proposed architecture is able to exhibit a practical average power efficiency of at least 12.35 tera operations per second per Watt, which is at least $2\times $ higher than the generic $z$ -first storage baseline architecture with over $3\times $ higher energy efficiency. The proposed architecture also demonstrates the applicability of the proposed schemes in commonly occurring variants of the convolution operation.

Next generation wireless communication introduces ultra high speed and low latency requirements to baseband processors, especially for multi-user multiple-input-multiple-output (MU-MIMO) systems. Polar codes, as the channel coding scheme in the control plane of 5G eMBB scenario, still cannot satisfy the hardware implementation requirements of polar decoders for MU-MIMO systems. In this brief, a high throughput and low latency polar decoder is proposed for MU-MIMO systems. The decoding architecture is fully unfolded to maximize hardware parallelism, and is fully pipelined by decoupling the round-trip scheduling datapath to enable simultaneous processing of multiple codewords. Besides, a hybrid decoding datapath is introduced by proposing complementary decoding units with mixed data representations to reduce hardware complexity. For (1024, 512) polar codes, a decoding throughput of 100.6 Gbps is achieved, and the latency is 0.43 us when 36 users are processed simultaneously.

Among its various improvements over prior NVIDIA GPUs, the NVIDIA Turing GPU boasts of four key performance enhancements to effectively counter memory load-to-use stalls. First, reduced latency on L1 hits for global memory loads helps lower average memory lookup latency. Next, the ability to dynamically configure the L1 data RAM between cacheable memory and scratchpad or shared memory, enables driver software to opportunistically maximize L1 data cache size for programs with low shared memory requirements, increasing L1 hits and reducing load-to-use stalls. Finally, the twin enhancements of doubling of vector register file capacity and the addition of a dedicated scalar or uniform register file along with a uniform datapath, ease vector register pressure and enable higher warp level parallelism, leading to better latency tolerance. We find that the above enhancements combined deliver an average speedup of 11% on modern gaming applications.

This article presents the application-aware real-time edge acceleration of CNNs (AWARE-CNNs) accelerators, which is a novel architecture design methodology for real-time execution of deep learning algorithms on IoT devices. AWARE leverages the reconfigurability of field-programmable gate arrays (FPGAs) to create application-specific architectures customized to match the inherent dataflow of targeted deep neural networks and user-specified real-time requirements. The customized datapath is combined with a customized memory path to guarantee deterministic latency-aware execution over streaming data. For results and evaluation, we have developed a Chisel-based implementation of AWARE-CNN with a full integrative framework for application-specific architecture generation and synthesis (AWARE-CNN architecture compiler). Our results demonstrate the ability to execute Tiny DarkNet and shallow MobileNet inference at 120 frames/s (FPS) and 75 FPS, using only 2.8 and 3.4 W, respectively, on a Xilinx XCZU9EG FPGA. In addition, AWARE-CNN framework’s flexibility with respect to the targeted convolutional neural networks and user constraints is validated by targeting additional design points for AlexNet (as a baseline network) and Tiny YOLOv2.

A scalable deep-learning accelerator supporting the training process is implemented for device personalization of deep convolutional neural networks (CNNs). It consists of three processor cores operating with distinct energy-efficient dataflow for different types of computation in CNN training. Unlike the previous works where they implement design techniques to exploit the same characteristics from the inference, we analyze major issues that occurred from training in a resource-constrained system to resolve the bottlenecks. A masking scheme in the propagation core reduces a massive amount of intermediate activation data storage. It eliminates frequent off-chip memory accesses for holding the generated activation data until the backward path. A disparate dataflow architecture is implemented for the weight gradient computation to enhance PE utilization while maximally reuse the input data. Furthermore, the modified weight update system enables an 8-bit fixed-point computing datapath. The processor is implemented in 65-nm CMOS technology and occupies 10.24 mm2 of the core area. It operates with the supply voltage from 0.63 to 1.0 V, and the computing engine runs in near-threshold voltage of 0.5 V. The chip consumes 40.7 mW at 50 MHz with the highest efficiency and achieves 47.4 $\mu \text{J}$ /epoch of training efficiency for the customized CNN model.

With technology scaling, subthreshold leakage has dominated the overall power consumption in a design. Input vector control is an effective technique to minimize subthreshold leakage. Low leakage input vector determination is not often possible due to large design space and simulation time. Similarly, applying an appropriate minimum leakage vector (MLV) to each Register Transfer Level (RTL) module instance in a design often results in a low leakage state with significant area overhead. In this work, we propose a top-down and bottom-up approach for propagating the input vector interval to identify low leakage input vector at primary inputs of an RTL datapath. For each module, via Monte Carlo simulation, we identify a set of MLV intervals such that maximum leakage is within (say) 10% of the lowest leakage points. As the module bit width increases, exhaustive simulation to find the low leakage vector is not feasible. Further, we need to uniformly search the entire input space to obtain as many low leakage intervals as possible. Based on empirical observations, we observe self-similarity in the subthreshold leakage distribution of adder/multiplier modules with highly regular bit-slice architectures when input space is partitioned into smaller cells. This property enables the uniform search of low leakage vectors in the entire input space where the time taken for characterization increases linearly with the module size. We further process the reduced interval set with simulated annealing to arrive at the best low-leakage vector at the primary inputs. We also propose to reduce area overhead (in some cases to 0%) by choosing Primary Input (PI) MLVs such that resultant inputs to internal nodes are also MLVs. Compared to existing work, experimental results for DSP filters simulated in 16nm technology demonstrated leakage savings of 93.6% and 89.2% for top-down and bottom-up approaches with no area overhead.

The increasing importance of inference algorithms, such as neural networks (NNs), principle component analysis (PCA), and singular value decomposition (SVD), etc., has led to the emergence of hardware accelerators to address power-performance tradeoffs in their implementation. Their large data sets make DRAM access the bottleneck for power and performance. Private SRAM scratch-pad memory is used to mitigate the DRAM access penalty but it is a limited resource in size and bandwidth. Thus, accelerator design is not just about computation, but also how data flow is scheduled across the memory hierarchy, including DRAM, scratch-pad SRAM, and datapath registers. Current accelerator design tools automate the generation of customized datapaths to improve performance, but have limited support for reducing DRAM/SRAM accesses during the computation. In this paper, we propose a memory-driven accelerator design methodology for large-scale inference applications, to maximize data access in the datapath and SRAM. We demonstrate its efficacy using several key kernels from large-scale inference applications.

Small-footprint implementations of the advanced encryption standard (AES) algorithm are of interest in resource-constrained applications like Internet of Things (IoT). Symmetries in AES allow the datapath to be scaled down to the S-Box width of 8 bits, but the ShiftRows operation leads to a potential data hazard that must be avoided. The common method for resolving the ShiftRows hazard wastes power by moving data through a sequence of pipelined registers. We present in this article a novel 8-bit AES architecture that solves data movement inefficiencies by renaming registers and saves clock power with a single state update per AES round. We then extend register renaming to include microarchitectural randomization to mitigate susceptibility to side-channel attacks, which are a concern especially for low power implementations of AES. We fabricate and evaluate our designs in a commercial 16-nm FinFET technology. Testchip measurements show that the register renaming architecture encrypts data at 0.55 pJ/bit at nominal voltage, a $2.2\times $ improvement over a state-of-the-art reference 8-bit design implemented in the same technology. Side-channel evaluation indicates that the randomized variant of register renaming significantly reduces vulnerability to differential power analysis (DPA).

Advanced Internet-of-Things applications require control-oriented codes to be executed with low latency for fast responsivity while their advanced signal processing and decision making tasks require computational capabilities. For this context, we propose three multi-issue core designs featuring an exposed datapath architecture with high performance, while retaining energy-efficiency. These features are achieved with exploitation of instruction-level parallelism, fast branching and the use of an instruction register file. With benchmarks in control-flow and signal processing application domains we measured in the best case 64% reduced energy consumption compared to a state-of-the-art RISC core, while consuming less silicon area. A high-performance design point reaches nearly 2.6 GHz operating frequency in the best case, over 2× improvement, while simultaneously achieving a 14% improvement in system energy-delay product.

The division datapath is undoubtedly the most complex operation in a wide range of digital signal processing applications, such as in adaptive filtering algorithms. This paper proposes an optimized and approximate integer divider hardware architecture, based on the Newton–Raphson algorithm combining both fixed-point dynamic range and truncation techniques, to speed up that operation. Adaptive filters have been much studied over time, as they comprise one of the most challenging fields in signal processing. This work presents dedicated hardware architectures based on normalized least mean square adaptive filtering algorithms for the power line harmonics interference cancelling. The hardware architectures are based on 2’s complement representation and were described in VHDL and synthesized into a 65 nm CMOS dedicated ASIC. Our results show that the increased approximation level of Newton–Raphson divider approximation presents up to 223 times less power dissipation than the baseline version without our optimization and approximations, providing up to 93 times of power dissipation savings in the complete interference canceller system.

In recent years, dedicated hardware accelerators for the acceleration of the convolutional neural network (CNN) have been extensively studied. Although many studies have presented efficient designs on FPGAs for image classification neural network models such as AlexNet and VGG, there are still little implementations for CNN-based object detection applications. This paper presents an OpenCL-based high-throughput FPGA accelerator for the YOLOv2 object detection algorithm on Arria-10 GX1150 FPGA. The proposed hardware architecture adopts a scalable pipeline design to support multi-resolution input image and full 8-bit fixed-point datapath to improve hardware resource utilization. Layer fusion technology that merges the convolution, batch normalization and Leaky-ReLU is also developed to avoid transmission of intermediate data between FPGA and external memory. Experimental results show that the final design achieves a peak throughput of 566 GOP/s under the working frequency of 190 MHz. The accelerator can execute YOLOv2 inference computation ( $$288\times 288$$ resolution) and tiny YOLOv2 ( $$416\times 416$$ resolution) at the speed of 35 and 71 FPS, respectively.

Since the dawn of the Internet of Things (IoT), data and system security has been the major concern for developers. Because most IoT devices operate on 8-bit controllers with limited storage and computation power, encryption and decryption need to be implemented at the transmitting and receiving ends, respectively, using lightweight ciphers. We present novel architectures for hardware implementation for the ANU cipher and present results associated with each architecture. The ANU cipher is implemented at 4-, 8-, 16-, and 32-bit datapath sizes on four different field-programmable gate array (FPGA) platforms under the same implementation condition, and the results are compared on every performance metric. Unlike previous ANU architectures, the new architectures have parallel substitution boxes (S-boxes) for high throughput and hardware optimization. With these different datapath designs, ANU cipher proves to be the obvious choice for implementing security in extremely resource-constrained systems.

Purpose The purpose of this work is to reduce the power consumption of KSA and to improve the PDP for data path applications. In digital Very Large – Scale Integration systems, the addition of two numbers is one of the essential functions. This arithmetic function is used in the modern digital signal processors and microprocessors. The operating speed of these processors depends on the computation of the arithmetic function. The speed computation block for most of the datapath elements was adders. In this paper, the Kogge–Stone adder (KSA) is designed using XOR, AND and proposed OR gates. The proposed OR gate has less power consumption due to the less number of transistors. In arithmetic logic circuit power, delay and power delay products (PDP) are considered as the important parameters. The delays reported for the proposed OR gate are less when compared with the conventional Complementary Metal Oxide Semiconductor (CMOS) OR gate and pre-existing logic styles. The proposed circuits are optimized in terms of power, delay and PDP. To analyze the performance of KSA, extensive Cadence Virtuoso simulations are used. From the simulation results based on 45 nm CMOS process, it was observed that the proposed design has obtained 688.3 nW of power consumption, 0.81 ns of delay and 0.55 fJ of PDP at 1.1 V. Design/methodology/approach In this paper, a new circuit for OR gate is proposed. The KSA is designed using XOR, AND and proposed OR gates. Findings The proposed OR gate has less power consumption due to the less number of transistors. The delays reported for the proposed OR gate are less when compared with the conventional CMOS OR gate and pre-existing logic styles. The proposed circuits are optimized in terms of power, delay and PDP. Originality/value In arithmetic logic circuit power, delay and PDP are considered as the important parameters. In this paper, a new circuit for OR gate is proposed. The power consumption of the designed KSA using the proposed OR gate is very less when compared with the conventional KSA. Simulation results show that the performance of the proposed KSA are improved and suitable for high speed applications.

Networks-on-chip (NoCs) acquired substantial advancements as the typical solution for a modular, flexible and high performance communication infrastructure coping with the scalable Multi-/Manycores technology. However, the increasing chip complexity heading towards thousand cores, together with the approaching dark-silicon era, puts energy efficiency as an integral design key for future NoC-based multicores, where NoCs are significantly contributing to the total chip power. In this paper, we propose HPPT-NoC, a dark-silicon inspired energy-efficient hierarchical TDM NoC with online distributed setup-scheme. The proposed network makes use of the dim silicon parts of the chip to hierarchically connect quad-routers units. Normal routers operate at full-chip-frequency at high supply level, and hierarchical routers operate at half-chip-frequency and lower supply voltage with adequate synchronization. Routers follow a proposed TDM architecture that separates the datapath from the control-setup planes. This allows separate clocking and operating supplies between data and control and to keep the control-setup as a single-slot-cycle design independent of the datapath slot size. The proposed NoC architecture is evaluated versus a base NoC from the state-of-the-art in terms of performance and hardware results using Synopsys VCS and Synopsys Design Compiler for SAED90nm and SAED32nm technologies. The obtained results highlight the power-frequency-trading feature supported by the proposed hierarchical NoC through the configurable data-control clock relation and maintained over the different technology nodes. With the same power budget of the base NoC, the proposed architecture provides up to 74% setup latency enhancement, 32% increased NoC saturation load, and 21% higher success rates, offering up to 78% improved power delay product. On the other hand, with 38% power savings, the proposed NoC provides up to 37% enhanced latency and 15% higher success rates, with 72% enhanced power delay product. The proposed design consumes almost double the area of the base NoC, however with an average of 56% under-clocked (dim) silicon area operating at half to quarter the maximum chip frequency. This results in reduced power density as a main concern in the dark-silicon era down to 24% of the base NoC.

In this brief, a low resource utilization field-programmable gate array (FPGA)-based long short-term memory (LSTM) network architecture for accelerating the inference phase is presented. The architecture has low-power and high-speed features that are achieved through overlapping the timing of the operations and pipelining the datapath. Moreover, this architecture requires negligible internal memory size for storing the intermediate data leading to low resource utilization and simple routing, which provides lower interconnect delay (higher operating frequency). A designer may adjust the resource utilization (as well as the latency) of the proposed architecture readily at the register-transfer level (RTL) design by adjusting the amount of parallelization. This makes the process of mapping the architecture onto different types of FPGAs, subject to defined constraints, a simple one. The efficacy of the proposed architecture is assessed by implementing an LSTM network on different types of FPGAs. Compared with the recent works, the proposed architecture provides up to about $1.6\times $ , $43.6\times $ , $21.9\times $ , and $114.5\times $ improvements in frequency, power efficiency, GOP/s, and GOP/s/W, respectively. Finally, our proposed architecture operates at 17.64 GOP/s, which is $2.31\times $ faster than the best previously reported results.

This study presents an 8-bit serialised architecture of SEED block cipher for constrained devices. The circuit utilises 356 FPGA slices and 447 1-bit registers flip-flops (FFs) in the BASYS3 board, operates with an 8-bit datapath and is aimed for use on area constraints devices. In order to keep the usage of hardware resources to a minimum but, at the same time, achieve a high level of security, the key generation process of SEED is implemented through an on-the-fly procedure. In addition, the necessary S-boxes are implemented using composite field arithmetic without using any block RAMs, resulting in a very compact implementation. The proposed architecture achieves a maximum frequency equal to 125 MHz with a total latency of 280 clock cycles and a throughput up to 57.1 Mbps for encryption or decryption.

This article demonstrates enhanced power (P) and electromagnetic (EM) side-channel analysis (SCA) attack resistance of standard (unprotected) 128-bit advanced encryption standard (AES) engines with parallel (P-AES, 128-bit) and serial (S-AES, 8-bit) datapaths and a 128-bit SIMON engine with the bit-serial (1-bit) datapath by an on-die security-aware all-digital low-dropout (DLDO) regulator. The proposed DLDO improves SCA resistance using control-loop-induced perturbations in a nominal DLDO, enhanced by a random switching noise injector (SNI) by power-stage control and a randomized reference voltage (R-VREF) generator coupled with all-digital clock modulation (ADCM). SCA performed on the measured power/EM signatures acquired from a 130-nm CMOS testchip demonstrates up to 25 $\times $ reduction in test vector leakage assessment (TVLA) leakage for P-AES and 3579 $\times $ , 2182 $\times $ , and 500 $\times $ increase in minimum-traces-to-disclose (MTD) 80% of the subkeys for P-AES, S-AES, and SIMON cores, respectively, with respect to correlation power analysis (CPA) and correlation EM analysis (CEMA).

Convolutional neural network (CNN) inference on mobile devices demands efficient hardware acceleration of low-precision (INT8) general matrix multiplication (GEMM). The systolic array (SA) is a pipelined 2D array of processing elements (PEs), with very efficient local data movement, well suited to accelerating GEMM, and widely deployed in industry. In this work, we describe two significant improvements to the traditional SA architecture, to specifically optimize for CNN inference. Firstly, we generalize the traditional scalar PE, into a Tensor-PE, which gives rise to a family of new Systolic Tensor Array (STA) microarchitectures. The STA family increases intra-PE operand reuse and datapath efficiency, resulting in circuit area and power dissipation reduction of as much as 2.08x and 1.36x respectively, compared to the conventional SA at iso-throughput with INT8 operands. Secondly, we extend this design to support a novel block-sparse data format called density-bound block (DBB). This variant (STA-DBB) achieves a 3.14x and 1.97x improvement over the SA baseline at iso-throughput in area and power respectively, when processing specially-trained DBB-sparse models, while remaining fully backwards compatible with dense models., Comment: Accepted by IEEE Computer Architecture Letters on 3/4/2020

International audience; Modern embedded computing platforms used within Cyber-Physical Systems (CPS) are nowadays leveraging more and more often on heterogeneous computing substrates, such as newest Field Programmable Gate Array (FPGA) devices. Compared to general purpose platforms, which have a fixed datapath, FPGAs provide designers the possibility of customizing part of the computing infrastructure, to better shape the execution on the application needs/features, and offer high efficiency in terms of timing and power performance, while naturally featuring parallelism. In the context of FPGA-based CPSs, this article has a two fold mission. On the one hand, it presents an analysis of the Damped Least Square (DLS) algorithm for a perspective hardware implementation. On the other hand, it describes the implementation of a robotic arm controller based on the DLS to numerically solve Inverse Kinematics problems over a heterogeneous FPGA. Assessments involve a Trossen Robotics WidowX robotic arm controlled by a Digilent ZedBoard provided with a Xilinx Zynq FPGA that computes the Inverse Kinematic.

In the Bitcoin network, computing double SHA-256 values consumes most of the network energy. Therefore, reducing the power consumption and increasing the processing rate for the double SHA-256 algorithm is currently an important research trend. In this paper, we propose a high-data-rate low-power hardware architecture named the compact message expander (CME) double SHA-256. The CME double SHA-256 architecture combines resource sharing and fully unrolled datapath technologies to achieve both a high data rate and low power consumption. Notably, the CME algorithm utilizes the double SHA-256 input data characteristics to further reduce the hardware cost and power consumption. A review of the literature shows that the CME algorithm eliminates at least 9.68% of the 32-bit XOR gates, 16.49% of the 32-bit adders, and 16.79% of the registers required to calculate double SHA-256. We synthesized and laid out the CME double SHA-256 using CMOS $0.18~\mu m$ technology. The hardware cost of the synthesized circuit is approximately 13.88% less than that of the conventional approach. The chip layout size is $5.9 mm \times 5.9 mm$ , and the correctness of the circuit was verified on a real hardware platform (ZCU 102). The throughput of the proposed architecture is 61.44 Gbps on an ASIC with Rohm 180nm CMOS standard cell library and 340 Gbps on a FinFET FPGA 16nm Zynq UltraScale+ MPSoC ZCU102.

This paper describes HighwayNoC, a Network-on-chip (NoC) that approaches ideal network performance using a Dual Data Rate (DDR) datapath. Based on the observation that routers datapath is faster than control, a DDR NoC allows flits to be routed at DDR improving throughput to rates defined solely by the datapath, rather than by the control. DDR NoCs can use pipeline bypassing to reduce packet latency at low traffic load. However, existing DDR routers offer bypassing only on in-network, non-turning hops to simplify the required logic. HighwayNoC extends bypassing support of DDR routers to local ports, allowing flits to enter and exit the network faster. Moreover, it simplifies the DDR switch allocation and the interface of router ports reducing power and area costs. Post place and route results in 28 nm technology show that HighwayNoC performs better than current state of the art NoCs. Compared to previous DDR NoCs, HighwayNoC reduces average packet latency by 7.3-27% and power consumption by 1-10%, without affecting throughput. Compared to existing Single Data Rate NoCs, HighwayNoC achieves 17-22% higher throughput, has similar or up to 13.8% lower packet latency, and mixed energy efficiency results.

Internet of Things (IoT) applications have massive client connections to cloud servers, and the number of networked IoT devices is remarkably increasing. IoT services require both low-tail latency and high concurrency in datacenters. This study aims to determine whether an order of magnitude improvement is possible in tail latency and concurrency in mainstream systems by proposing a hardware–software codesigned labeled network stack (LNS) for future datacenters. The key innovation is a cross-layered payload labeling mechanism that distinguishes different requests by payload across the full network stack, including application, TCP/IP, and Ethernet layers. This type of design enables prioritized data packet processing and forwarding along the full datapath, such that latency-insensitive requests cannot significantly interfere with high-priority requests. We build a prototype datacenter server to evaluate the LNS design against a commercial X86 server and the mTCP research, using a cloud-supported IoT application scenario. Experimental results show that the LNS design can provide an order of magnitude improvement in tail latency and concurrency. A single datacenter server node can support over 2 million concurrent long-living connections for IoT devices as a 99-percentile tail latency of 50 ms is maintained. In addition, the hardware–software codesign approach remarkably reduces the labeling and prioritization overhead and constrains the interference of high-priority requests to low-priority requests.

This letter presents an error-detection-and-correction-free voltage scaling technique based on spatial–temporal error spreading and voltage dithering (ESVD) for video processing datapaths. By leveraging the persistence of vision and the tendency of the human eye to mix pixels in close proximity, the proposed ESVD alleviates the reduction in visual quality caused by timing errors due to the lower supply voltage without explicit detection and correction; therefore, the proposed EVSD requires neither architectural nor circuit-level modification of the datapath and is especially suitable for fixed-latency video processing datapaths. Using a framebuffer-less frame-locked video scaling engine as a test case, the test chip implemented in a 40-nm 1.1-V CMOS process demonstrates that the datapath’s power consumption can be reduced maximally by 35% when scaling video streams in real time (22.6% if the efficiency of the on-chip regulator is considered). Additionally, the measured qualities in terms of the PSNR are larger than 30 dB compared with the error-free frame, whereas the maximum quality of experience from the user’s perspective in terms of the mean opinion score is 5 based on the degradation category rating (DCR).

The rapid evolution of field-programmable gate array (FPGA) devices has strongly influenced both the design methodology and development tools. This article describes an original implementation based on a hardware structure used for static and dynamic task scheduling. The proposed custom processor has hardware-implemented RTOS (HW-RTOS) features and is verified using an FPGA circuit. The solution replaces the classical stack save concept with a resource remapping mechanism that enables a new task to be executed starting with the next processor cycle. The proposed hardware scheduler enables unified management of events and interrupts, by implementing a method of attaching interrupts to tasks while ensuring the requirements of real-time systems. The robustness and performance of the proposed platform are guaranteed by the context switch operations, presence of the intertask synchronization and communication mechanisms, and by the efficient use of the multiplexed resources. Instead of saving and restoring general-purpose registers into the memory, the latency is removed by directly commuting the datapath task resources.

As AI-based applications become pervasive, CPU vendors are starting to incorporate matrix engines within the datapath to boost efficiency. Systolic arrays have been the premier architectural choice as matrix engines in offload accelerators. However, we demonstrate that incorporating them inside CPUs can introduce under-utilization and stalls due to limited register storage to amortize the fill and drain times of the array. To address this, we propose RASA, Register-Aware Systolic Array. We develop techniques to divide an execution stage into several sub-stages and overlap instructions to hide overheads and run them concurrently. RASA-based designs improve performance significantly with negligible area and power overhead., This paper is accepted to DAC 2021

High-resolution studies of data center traffic at the network core uncover short-term bursty traffic patterns, periods of high buffer utilization that last for tens of microseconds and lead to packet loss and longer flow completion time tails. While recent attention has been directed towards studying the bursty traffic at the network core, less heed has been given to the origins of bursty traffic, e.g., host machines. In this study, we try to perform high-resolution traffic measurements in the host networking stack to quantify the impact of system software components on traffic burstiness. We enforce per-packet timestamping on the datapath using various techniques like NIC timestamping, eBPF, and direct kernel source modification and measure the gaps between egress packets under various configurations. We provide preliminary findings on how process scheduling can affect traffic burstiness.

Datacenter systems and I/O devices now run at single-digit microsecond latencies, requiring ns-scale operating systems. Traditional kernel-based operating systems impose an unaffordable overhead, so recent kernel-bypass OSes [73] and libraries [23] eliminate the OS kernel from the I/O datapath. However, none of these systems offer a general-purpose datapath OS replacement that meet the needs of μs-scale systems.' AB@This paper proposes Demikernel, a flexible datapath OS and architecture designed for heterogenous kernel-bypass devices and μs-scale datacenter systems. We build two prototype Demikernel OSes and show that minimal effort is needed to port existing μs-scale systems. Once ported, Demikernel lets applications run across heterogenous kernel-bypass devices with ns-scale overheads and no code changes.

Personalized recommendation systems are gaining significant traction due to their industrial importance. An important building block of recommendation systems consists of the embedding layers, which exhibit a highly memory-intensive characteristic. A fundamental primitive of embedding layers is the embedding vector gathers followed by vector reductions, exhibiting low arithmetic intensity and becoming bottlenecked by the memory throughput. To tackle such a challenge, recent proposals employ a near-data processing (NDP) solution at the DRAM rank-level, achieving impressive performance speedups. We observe that prior rank-level-parallelism-based NDP solutions leave significant performance potential on the table as they do not fully reap the abundant transfer throughput inherent in DRAM datapaths. We propose TRiM, an NDP architecture for accelerating recommendation systems. Based on the observation that the DRAM datapath has a hierarchical tree structure, TRiM augments the DRAM datapath with “in-DRAM” reduction units at the DDR4/5 rank/bank-group/bank level. We modify the interface of DRAM to provide commands effectively to multiple reduction units running in parallel. We also propose a host-side architecture with hot embedding-vector replication to alleviate the load imbalance that arises across the reduction units. An optimal TRiM design based on DDR5 achieves up to a 7.7 × and 3.9 × speedup and reduces by 55% and 50% the energy consumption of the embedding vector gather and reduction over the baseline and the state-of-the-art NDP architecture with minimal area overhead equivalent to 2.66% of DRAM chips.

Posit arithmetic has better dynamic range and accuracy over the conventional IEEE-754 floating-point. In this paper, architectures for posit adder/subtractor and multiplier have been proposed that work as per the desired bit size of operands. Here, 16 and 32-bit architectures with different exponent size (ES) have been designed. FPGA implementations of these architectures have been done on the Xilinx Virtex-7 xc7vx330t-3ffg1157 device. In comparison with existing work, it has been observed that the usage of LUTs with ES=2 is lowered by 7.11/16.07% for 16/32-bit adders, and 1.81% for 32-bit multiplier with ES=3. In addition, 16/32-bit adder architectures require 31.47/31.66% lesser datapath delay. The 16/32-bit posit multipliers consume 10.40/10.84% lesser delay.

Simultaneous multithreading (SMT) processors target resource under-utilization related performance problems of superscalar processors by allowing various datapath resources to be simultaneously shared among several threads with ease. This approach exploits thread-level parallelism on top of the well-studied instruction level parallelism. However, when datapath resources are shared among threads, there is always a possibility that corunning ill-intended programs may try to sniff on other programs with sensitive information like passwords or cryptocurrency information. By stress-testing and measuring many of the shared resources, this is quite achievable. These approaches are known as side-channel attacks. SMT-COP, a study published recently, is a secure architectural implementation based on resource scheduling that prevents these kind of attacks based on execution logic with a modest performance loss of nearly 10%. In this study, we aim to improve SMT-COP’s resource distribution scheme with several approaches, providing a quite close sense of security to that of SMT-COP while improving the performance by up to 8.86% on the average, over the original SMT-COP design.

The SMT (Simultaneous Multithreading) architecture is widely used in modern processors. It provides a performance gain in the system by running multiple threads simultaneously to better utilize datapath resources. In this architecture, one of the research areas is how to allocate common resources among threads. In the static approach, resources are allocated to threads equally or according to a specific predefined rule. In the dynamic approach, monitoring the system at runtime, the most appropriate allocation strategy is chosen. Hill-Climbing and Stretch are two examples of dynamic resource allocation methods. This paper proposes a hybrid approach that combines Stretch with the Hill-climbing method to improve both the throughput and the QoS metrics of the SMT processor. We compare our QoS-Oriented and Throughput-Oriented methods, showing that we can satisfy a target QoS on a latency-sensitive thread, while still achieving near-optimal (only an average of 0.6% worst performance over the Throughput-Oriented method) throughput with our QoS-Oriented approach.

We present a hardware design for the learning datapath of the Tsetlin machine algorithm, along with a latency analysis of the inference datapath. In order to generate a low energy hardware which is suitable for pervasive artificial intelligence applications, we use a mixture of asynchronous design techniques - including Petri nets, signal transition graphs, dual-rail and bundled-data. The work builds on previous design of the inference hardware, and includes an in-depth breakdown of the automaton feedback, probability generation and Tsetlin automata. Results illustrate the advantages of asynchronous design in applications such as personalized healthcare and battery-powered internet of things devices, where energy is limited and latency is an important figure of merit. Challenges of static timing analysis in asynchronous circuits are also addressed.

In this paper, a very compact architecture the newest member of the SNOW family of stream ciphers, called SNOW-V, is presented. The proposed architecture has a 128-bit datapath and is pipelined in key areas in order to achieve the maximum possible frequency while using only a small number of hardware resources. The design was coded using the VERILOG hardware description language and the BASYS3 board (Artix 7 XC7A35T) was the target of the hardware implementation. The proposed implementation utilizes only 2109 FPGA LUTs and 1352 FFs and reaches a data throughput of 2.6 Gbps at 224 MHz clock frequency.

The recent emergence of 5G network enables mass wireless sensors deployment for internet-of-things (IoT) applications. In many cases, IoT sensors in monitoring and data collection applications are required to operate continuously and active at all time (24/7) to ensure all data are sampled without loss. Field-programmable gate array (FPGA)-based systems exhibit a balanced processing throughput and datapath flexibility. Specifically, datapath flexibility is acquired from the FPGA-based system architecture that supports dynamic partial reconfiguration feature. However, device functional update can cause interruption to the application servicing, especially in an FPGA-based system. This paper presents a standalone FPGA-based system architecture that allows remote functional update without causing service interruption by adopting a redundancy mechanism in the application datapath. By utilizing dynamic partial reconfiguration, only the updating datapath is temporarily inactive while the rest of the circuitry, including the redundant datapath, remain active. Hence, there is no service interruption and downtime when a remote functional update takes place due to the existence of redundant application datapath, which is critical for network and communication systems. The proposed architecture has a significant impact for application in FPGA-based systems that have little or no tolerance in service interruption.

”Soft” GPUs are overlays that implement GPGPU-like data parallel processor architectures in FPGA logic to make FPGAs as software-programmable as ”hard” GPGPUs. Unlike hard GPUs, soft GPU architectures can be specialized to further improve efficiency by leveraging FPGA’s flexibility. Prior work has shown the software programmability potential for soft GPUs but only studied general-purpose soft GPUs with minor specializations (e.g., FPGU, FlexGrip, MIAOW, and SCRATCH) or only domain-optimized for a particular application domain (e.g., PDL-FGPU for the persistent deep learning domain.) This paper proposes a soft GPU development framework to automate the creation of soft GPU instances with aggressive application-domain optimizations (i.e., domain-optimized GPUs, or DOGPUs) that consists of a baseline general soft GPU architecture ”template” with an improved architecture over prior general purpose soft GPUs, along with a customizable partition that enables a custom datapath (macro unit) to be inserted to optimize for a target application domain. Unlike the prior PDL-FGPU which targets the persistent deep learning domain, the proposed framework can be used to target optimization for any application domain. Our evaluation on a set of data parallel workloads shows that (i) the proposed general soft GPU architecture offers average speedup of 1.8x versus the best prior soft GPUs we know of (i.e., FGPU, PDL-FGPU), (ii) DO-GPUs with domain-optimizations provide an average of 218x speedup over general soft GPUs, (iii) the proposed framework enabled building six new domain-optimized soft GPU instances in a matter of days, and (iv) enables quick GPU-like development effort (hours), where code is concise (low 100s of lines) and can be compiled in seconds without FPGA EDA tools in the loop, assuming an appropriate soft DO-GPU bitstream for the application domain is already built.

Deep neural networks (DNNs) are vulnerable to maliciously generated adversarial examples. These examples are intentionally designed by making imperceptible perturbations and often mislead a DNN into making an incorrect prediction. This phenomenon means that there is significant risk in applying DNNs to safety-critical applications, such as driverless cars. To address this issue, we present a visual analytics approach to explain the primary cause of the wrong predictions introduced by adversarial examples. The key is to analyze the datapaths of the adversarial examples and compare them with those of the normal examples. A datapath is a group of critical neurons and their connections. To this end, we formulate the datapath extraction as a subset selection problem and approximately solve it based on back-propagation. A multi-level visualization consisting of a segmented DAG (layer level), an Euler diagram (feature map level), and a heat map (neuron level), has been designed to help experts investigate datapaths from the high-level layers to the detailed neuron activations. Two case studies are conducted that demonstrate the promise of our approach in support of explaining the working mechanism of adversarial examples.

Intellectual Property (IP) core protection of Digital Signal Processing (DSP) kernels is an important subject of research for Consumer Electronics (CE) systems. An IP core may be prone to piracy, forgery and counterfeiting. The need of the hour is developing effective technique that is robust and incurs low overhead to detect IP core infringement. This paper presents a novel ‘IP core steganography’ methodology for DSP kernels that is capable of detecting IP piracy. The proposed methodology is capable of implanting concealed information into the existing IP core design of DSP datapath without using any external signature, to reflect the IP core ownership. The presented ‘IP core steganography’ methodology is non-intuitive in nature indicating that the intended secret information does not attract attention to itself from an adversary’s perspective. The implanted information incurs almost no design overhead and yields lower design cost than signature-based IP core protection techniques. Further, in the presented approach the amount of concealed information embedded is fully designer controlled through a ‘thresholding’ parameter, unlike signature-based techniques where signature pattern impacts the robustness and overhead. Results of proposed approach yielded lower cost and stronger proof of authorship compared to a signature-based approach.

Data security is essential for the proliferation of the Internet of things and cyber-physical system technologies. Data security can be efficiently achieved by incorporating lightweight cryptography techniques. In this study, a set of high-performance hardware architectures for PRESENT lightweight block cipher are proposed that perform encryption, decryption and integrated encryption/decryption operations. Datapath of the architectures is of 64 bit width that supports standard 80 and 128 bits key lengths. The architectures are synthesised on Xilinx Virtex-5 XC5VLX110T (ff1136-1) field-programmable gate array device of ML-505 platform. To perform functional verification, a large number of test vectors are used. Performance measurement is performed by evaluating maximum frequency, throughput, power dissipation and energy consumption. Experimentally, it is found that the proposed architectures are resource-efficient, high-performance and suitable for lightweight, latency-critical and low-power applications in comparison with existing architectures.

This work presents a high-level electronic design automation (EDA) tool named Witelo, which produces high-performance functional macroblocks from a given computational kernel specification in the C programming language. High-performance is achieved through both deep pipelining of functional units, and a decentralized dataflow control approach which effectively manages the datapath as a distributed system. Furthermore, a synthesizable virtual wrapper is optionally generated allowing the user to characterize circuit performance for the isolated macroblock using vendor tools and before the full system is available. Finally, results for macroblocks generated from real Computational Fluid Dynamics applications are provided.

Hyper-dimensional Computing (HDC), a bio-inspired paradigm defined on random high-dimensional vectors, has emerged as a promising IoT paradigm. It is known to provide competitive accuracy on sequential prediction tasks with much smaller model size and training time compared to conventional ML, and is well-suited for human-centric IoT. In the post-Moore scaling era, where increasing variability has challenged traditional designers, its novel computing method based on randomness can be leveraged for continued performance. This work develops a complete, programmable architecture for ultra energy-efficient supervised classification using HD computing. Its simple construction follows from basic HD operations and its massively parallel, shallow datapath ( $ /pred. for the entire benchmark at about 2.5ns cycle time, with most applications requiring < 700 nJ/pred. As a first complete design working with high dimensional stochastic signals, the main architectural decisions for similar systems harnessing variability in emerging devices (eg. CNFET and RRAM) are established. A fabricated system could be readily deployed for human-centric IoT applications.

This paper proposes a low-power advanced encryption standard (AES) that can be utilized in smaller applications such as small-scale internet- of-things (IoT) devices. The proposed AES uses 8-bit and 32-bit datapaths to satisfy low power consumption and small area requirements. We use the 32-bit datapath in MixColumns only; the 8-bit datapath was used in other blocks such as SubBytes, Byte Permutation, AddRoundKey, and KeyExpansion. In addition, we propose optimized SubBytes and MixColumns to achieve low power consumption within a small area. To optimize SubBytes, we simplify the algorithm block-by-block to decrease the area. For the MixColumns, we present a 32-bit datapath that uses the proposed 0 × 02 and 0 × 03 multiplier. The AES that we have presented in this study, is implemented through Verilog-HDL and synthesized using the Samsung 65 nm standard cell library. The proposed AES shows 5400 2-input NAND gate equivalences and a power consumption of 10.01 μW (@ 0.9 V) at 10 MHz.

In this paper, we present an accuracy-aware design framework [called accuracy-aware high-level synthesis (Achilles)], which synthesizes a high-level description of an input application with the objective of minimizing the energy consumption of the synthesized circuit. The proposed framework includes two main parts of Achilles and light-weight predictor selection. The framework leverages light-weight error predictors (i.e., machine learning-based classifiers) to achieve more energy reduction by dynamically managing the output quality level (exact or approximate) of the synthesized circuit. To synthesize the input application, first, we exploit a heuristic algorithm to determine the quality level required for each operation in the data flow graph (DFG) representation of the input application. Next, for synthesizing the input application, we propose an effective Achilles algorithm which utilizes the flexibility of the available multiquality arithmetic units in a high-level cell library to synthesize the datapath. To improve the efficiency, the process starts by iteratively reducing the number of functional units required for synthesizing the DFG. Then, a proper light-weight error predictor satisfying the user expected quality is chosen from the available predictors in the framework. Based on the quality requirements, three different quality management modes are considered. The efficacy of the proposed framework is assessed for benchmarks from image and signal processing as well as robotics domains. The study of these benchmarks indicates that Achilles may reduce the energy consumption up to 51% (36% on average), up to 72% (51% on average), and up to 57% (33% on average) in threshold, average, and hybrid modes, respectively, for the studied cases. Moreover, the results show that relative coverage of large errors may be increased from 21% to 55% by employing synthetic minority oversampling technique method.