395 results on '"Cheng-Kok Koh"'
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52. Statistical Timing Analysis Considering Spatial Correlations.
53. Recursive Function Smoothing of Half-Perimeter Wirelength for Analytical Placement.
54. Efficient Analysis of Large-Scale Power Grids Based on a Compact Cholesky Factorization.
55. Stable and compact inductance modeling of 3-D interconnect structures.
56. Clock Generation and Distribution Using Traveling-Wave Oscillators with Reflection and Regeneration.
57. SAVS: a self-adaptive variable supply-voltage technique for process- tolerant and power-efficient multi-issue superscalar processor design.
58. Adaptive admittance-based conductor meshing for interconnect analysis.
59. SASIMI: sparsity-aware simulation of interconnect-dominated circuits with non-linear devices.
60. Cascaded carry-select adder (C2SA): a new structure for low-power CSA design.
61. Statistical based link insertion for robust clock network design.
62. 3D module placement for congestion and power noise reduction.
63. Gated Decap: gate leakage control of on-chip decoupling capacitors in scaled technologies.
64. A Performance and Power Co-optimization Approach for Modern Processors.
65. Process variation robust clock tree routing.
66. Compact and stable modeling of partial inductance and reluctance matrices.
67. Post-layout logic duplication for synthesis of domino circuits with complex gates.
68. Improving the scalability of SAMBA bus architecture.
69. Floorplan management: incremental placement for gate sizing and buffer insertion.
70. Recursive bisection based mixed block placement.
71. Routability-driven placement and white space allocation.
72. Fast simulation of VLSI interconnects.
73. A fast Newton/Smith algorithm for solving algebraic Riccati equations and its application in model order reduction.
74. Priority assignment optimization for minimization of current surge in high performance power efficient clock-gated microprocessor.
75. A high performance bus communication architecture through bus splitting.
76. Post-layout logic optimization of domino circuits.
77. Passivity-preserving model reduction via a computationally efficient project-and-balance scheme.
78. Integrated architectural/physical planning approach for minimization of current surge in high performance clock-gated microprocessors.
79. Performance Optimization of Latency Insensitive Systems Through Buffer Queue Sizing of Communication Channels.
80. SAMBA-Bus: A High Performance Bus Architecture for System-on-Chips.
81. Non-Crossing OBDDs for Mapping to Regular Circuit Structures.
82. Integer linear programming-based synthesis of skewed logic circuits.
83. A metric for analyzing effective on-chip inductive coupling.
84. Interconnect Planning with Local Area Constrained Retiming.
85. Clock Scheduling for Power Supply Noise Suppression using Genetic Algorithm with Selective Gene Therapy.
86. An adaptive window-based susceptance extraction and its efficient implementation.
87. On-chip caches built on multilevel spin-transfer torque RAM cells and its optimizations.
88. Analytical estimates of stress around a doubly periodic arrangement of through-silicon vias.
89. On-chip interconnect modeling by wire duplication.
90. Exact Closed Form Formula for Partial Mutual Inductances of On-Chip Interconnects.
91. Efficient Approximate Balanced Truncation of General Large-Scale RLC Systems via Krylov Methods.
92. Flip-Flop and Repeater Insertion for Early Interconnect Planning.
93. Model Reduction in the Time-Domain Using Laguerre Polynomials and Krylov Methods.
94. Power Supply Noise Suppression via Clock Skew Scheduling.
95. Synthesis of Selectively Clocked Skewed Logic Circuits.
96. A factorization-based framework for passivity-preserving model reduction of RLC systems.
97. Decoupling capacitance allocation for power supply noise suppression.
98. Selectively clocked skewed logic (SCSL): low-power logic style for high-performance applications.
99. Short-circuit power analysis of an inverter driving an RLC load.
100. Power trends and performance characterization of 3-dimensional integration.
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