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In this work, a new approach to determine the effect of direct source-to-drain tunneling (DSDT) on 2-D double-gate (DG) MOSFETs is presented. The tunneling probability of electrons with different energy levels and tunneling distances through the potential barrier is calculated using harmonic wavelets and the results are compared to those calculated with the Wentzel-Kramers-Brillouin (WKB) method. Next, by having the tunneling probability the DSDT current is calculated and compared to TCAD simulations data, which are based on WKB model, and also to NanoMOS, a Non-Equilibrium Green's Function (NEGF) 2-D simulator for DG devices. The difference between these methods and their impacts on the resulted DSDT as well as the subthreshold behavior are investigated. Furthermore, a first step towards compact modeling is made by approximating the tunneling current density.

An analytical model of dual-material gate graded channel and dual oxide thickness cylindrical gate (DMG-GC-DOT) MOSFET is investigated in this work. Analytical model of drain current is developed u...

In this paper, new computationally implemented semi-empirical table-based and predictive model for the drain–current in DG-MOS transistors is presented. This model includes two stages; the first one is a generic table-based method to obtain the basic approximate solutions only valid for long channel conditions, the second one calculates the correction to these solutions in order to take into account the short channel effects and it is actually a method that should be calibrated a la carte for each technological parameters set used by manufacturing Integrated Circuits. The new model is valid and continuous in linear, saturation and sub threshold regimes. Short-channel effects and channel-length modulation are accurately predicted by this model that shows very good agreement not only with drain–current curves but also with and their VDS and VGS derivatives issued from Silvaco-ATLAS simulations.

Physics-based models for calculating the threshold voltage ( ${V}_{\text {th}}$ ) of GaN-based high electron mobility transistor (HEMT) is proposed. Assuming that the 2-D electron gas in III–V heterostructures originate from donor-like surface states, an analytical expression for $\phi _{b}$ is derived based on the condition of charge neutrality across the barrier layer and applied to develop ${V}_{\text {th}}$ model. Effects of introducing a GaN cap layer on distribution of surface donor states and strain relaxation due to high barrier layer Al composition are considered in the derivation of the models. Calculated ${V}_{\text {th}}$ values are in excellent agreement with the values extracted from static ${I}_{d}$ – ${V}_{g}$ measurement data for devices with different gate lengths. Furthermore, the ${V}_{\text {th}}$ models are implemented in the physics-based ${I}$ – ${V}$ model previously proposed by our group for AlGaN/GaN HEMTs and tested with devices of different geometries. Excellent agreement is obtained between the model and experimental data of the drain current and transconductance of the devices over a full range of bias conditions.

Amorphous In-Ga-Zn-O Thin Film Transistors (a-IGZO TFTs) have proven to be an excellent approach for flat panel display drivers using organic light emitting diodes, due to their high mobility and stability compared to other types of TFTs. These characteristics are related to the specifics of the metal-oxygen-metal bonds, which give raise to spatially distributed s orbitals that can overlap between them. The magnitude of the overlap between s orbitals seems to be little sensitive to the presence of the distorted bonds, allowing high values of mobility, even in devices fabricated at room temperature. In this paper, we show the effect of the distribution of states in the a-IGZO layer on the main conduction mechanism of the a-IGZO TFTs, analyzing the behavior with temperature of the drain current.

DOI: 10.1016/j.sse.2017.08.006 URL: https://www-sciencedirect-com.sabidi.urv.cat/science/article/pii/S0038110117303908?via%3Dihub Filiació URV: SI Source-to-drain (SD) tunneling decreases the device performance in MOSFETs falling below the 10 nm channel length. Modeling quantum mechanical effects including SD tunneling has gained more importance specially for compact model developers. The non-equilibrium Green's function (NEGF) has become a state-of-the-art method for nano-scaled device simulation in the past years. In the sense of a multi-scale simulation approach it is necessary to bridge the gap between compact models with their fast and efficient calculation of the device current, and numerical device models which consider quantum effects of nano-scaled devices. In this work, an NEGF based analytical model for nano-scaled double-gate (DG) MOSFETs is introduced. The model consists of a closed-form potential solution of a classical compact model and a 1D NEGF formalism for calculating the device current, taking into account quantum mechanical effects. The potential calculation omits the iterative coupling and allows the straightforward current calculation. The model is based on a ballistic NEGF approach whereby backscattering effects are considered as second order effect in a closed-form. The accuracy and scalability of the non-iterative DG MOSFET model is inspected in comparison with numerical NanoMOS TCAD data for various channel lengths. With the help of this model investigations on short-channel and temperature effects are performed.

In this paper we present a compact mole fraction-dependent modeling of the I-V and C-V characteristics in Al $$_{x}$$ Ga $$_{1-x}$$ N/GaN HEMTs using Atlas TCAD. The C-V characteristics of the Al $$_{x}$$ Ga $$_{1-x}$$ N/GaN HEMTs are obtained using a charge conserving model. Based on this modeling, we have developed an analytical model for the threshold voltage, the carrier sheet density, the drain current, and the capacitance. The model covers all the different operating regimes of the device. The model includes the Al mole fraction of the barrier layer effects and was incorporated into our previously developed charge based on I-V and C-V characteristics, and we also simulated the device transconductance of Al $$_{x}$$ Ga $$_{1-x}$$ N/GaN HEMTs. The results of the modeled I-V and C-V characteristics are in excellent agreement with the simulated data obtained by the Atlas TCAD simulator, which demonstrates the validity of the proposed model.

A crystalline-like temperature dependence of the electrical characteristics of amorphous Indium-Gallium-Zinc-Oxide (a-IGZO) thin film transistors (TFTs) is reported, in which the drain current reduces as the temperature is increased. This behavior appears for values of drain and gate voltages above which a change in the predominant conduction mechanism occurs. After studying the possible conduction mechanisms, it was determined that, for gate and drain voltages below these values, hopping is the predominant mechanism with the current increasing with temperature, while for values above, the predominant conduction mechanism becomes percolation in the conduction band or band conduction and IDS reduces as the temperature increases. It was determined that this behavior appears, when the effect of trapping is reduced, either by varying the density of states, their characteristic energy or both. Simulations were used to further confirm the causes of the observed behavior.

This paper seeks to address the effect of trap– assisted tunneling (TAT) and ambipolarity on the DC and transient behavior of tunnel-field effect transistors (TFETs) using a compact model. The model is implemented in Verilog–A language and presents both AC and DC characteristics of TFET. The robustness and flexibility of the numerical compact model make it possible to simulate the TFET not only as a single element but also in circuit level. Hence, it is used to simulate a TFET inverter and a 3–stage TFET ring–oscillator. In order to evaluate the impact of TAT and TFET ambipolarity, simulations are presented for different trap densities and drain doping concentrations. It is shown that the changes in flat–band voltage (V fb ) can drastically affect the performance of the TFET inverter, whereas ambipolarity and TAT nearly have no impact on the transient performance. In the end, TFET inverter delay as a function of channel length and in dependency of V fb is depicted and compared with conventional MOSFET.

In this paper, Low Frequency Noise (LFN) characterization of SP500 polymer-based Organic Thin Film Transistors with a nonfluorinated dielectric material is presented. The work aimed at identifying the mechanism of 1/f noise as well as inspecting the quality of the gate dielectric interface. Analysis of the LFN experimental data reveals that the 1/f noise power spectral density (PSD) follows 1/f γ frequency dependence over 1 Hz–10 kHz range. The normalized current noise PSD is found to vary similar to the squared-transconductance drain current ratio with respect to drain current, and is inversely related to the gate-area. Furthermore, the high carrier mobility (on the order of 2–3 cm 2 / Vs) obtained in these devices indicates that low density of traps exists in the semiconducting organic thin film. Such results ascribed the origin of 1/f noise to the dynamic exchange of charge carriers between the gate-dielectric traps and the channel. In addition, Nst values extracted from the 1/f noise experimental data reflect the enhanced quality of the gate dielectric and the interface it forms with the channel material.In this paper, Low Frequency Noise (LFN) characterization of SP500 polymer-based Organic Thin Film Transistors with a nonfluorinated dielectric material is presented. The work aimed at identifying the mechanism of 1/f noise as well as inspecting the quality of the gate dielectric interface. Analysis of the LFN experimental data reveals that the 1/f noise power spectral density (PSD) follows 1/f γ frequency dependence over 1 Hz–10 kHz range. The normalized current noise PSD is found to vary similar to the squared-transconductance drain current ratio with respect to drain current, and is inversely related to the gate-area. Furthermore, the high carrier mobility (on the order of 2–3 cm 2 / Vs) obtained in these devices indicates that low density of traps exists in the semiconducting organic thin film. Such results ascribed the origin of 1/f noise to the dynamic exchange of charge carriers between the gate-dielectric traps and the channel. In addition, Nst values extracted from the 1/f noise experimental...

This paper presents a compact model for the threshold-voltage shift, consisting of V T,roll–off and Drain-Induced-Barrier-Lowering (DIBL), in short-channel staggered organic thin-film transistors (OTFTs). An analytical surface potential solution is derived for a staggered geometry containing two-dimensional effects which is used to extract the V T,roll–off and DIBL out of it. Thus, the closed-form and physics-based equations extend an existing compact current model by incorporating them into expressions for V T . Verification of the modeling approach is done by comparison with TCAD Sentaurus simulations as well as measurements on organic TFTs with a channel length down to 400 nm.

This paper presents a novel compact modeling approach to consider the effect of trap-assisted tunneling (TAT) in the calculations of the tunneling current in tunnel field-effect transistors (TFETs). The closed-form and physics-based model equations are implemented in the hardware description language Verilog-A and thus extend an existing model for the B2B tunneling current calculation in double-gate (DG) TFETs.In order to verify the modeling approach, simulation results are compared to TCAD Sentaurus simulations. The compact model shows a good fit in the current transfer curves for various drain-source voltages, trap densities, drain doping concentrations and different source materials. The current output curve and the output conductance stay also in good agreement with TCAD data. In the next step, the compact model is verified with the help of measurements of fabricated complementary TFET devices. During the verification process, limitations and advantages of the modeling approach are analyzed and discussed. The influence of TAT on a fabricated single-stage TFET inverter is investigated in a last verification step, whereby the numerical stability and flexibility of the model is demonstrated.

We present a way to analytically describe short-channel effects in cylindrical gate-all-around (GAA) MOSFETs with intrinsic or lightly-doped channels. For a given device dimension, the center and surface potentials (Φ c and Φ s) are correctly determined by using the conformal mapping technique for 2-D double-gate (DG) FETs. An equivalent channel length is used in a compact drain current model of a DG device, which thereby is modified to get results for a cylindrical GAA MOSFET. To verify the introduced equivalent correlation for different channel lengths and thicknesses we compare both potentials Φc and Φ s, the subthreshold swing (S sth) and the drain-induced barrier lowering (DIBL) of our new compact model with 3-D GAA MOSFET TCAD simulation data. In addition, we compare for one chosen device dimension the DC characteristics of our model with TCAD and measurement data.

This work presents a physics-based model for the flicker (1/f) noise behavior of bottom-gated amorphous InGaZnO (a-IGZO) thin-film transistors (TFTs) with an Edge-Stop Layer (ESL). The model is derived based on the so-called Unified Method and Extraction Procedure (UMEM), a technique previously used in accurate device parameter extraction and simulation of current-voltage (I-V) characteristics of the amorphous hydrogenated Silicon (a-Si:H), polycrystalline Silicon (poly-Si), and Organic TFT (OTFT) devices. It has been reported that 1/f noise in the bottom-gated a-IGZO TFT with ESL and with a very thin film IGZO layer obeys the carrier number fluctuation theory. The unified 1/f noise model is, therefore, adapted here to take into account the correlated bulk mobility fluctuation as well. Excellent agreements of the model with measured DC and flicker noise characteristics have shown the model validation.

Spike-based neural networks have been shown to hold more computational power than other architectures and their integration into mainstream computing is projected to herald a new age for information technology. Implementation using a flexible Thin Organic Large Area Electronics TOLAE process is a promising low cost way to integrate neuromorphic circuits into sensors, however its feasibility has never been demonstrated. Here we simulate spiking neuron circuits based on the characteristics of a gravure printed scalable organic thin film transistor technology. We then explore the variability of the parameters to show how much variation the circuits can support. Our results demonstrate the feasibility of OTFT technologies for spiking neuromorphic hardware. Figure 1

We study the low frequency noise, also known as flicker noise (1/f), in polymer-based Organic Thin Film Transistors, and we review techniques to identify the mechanisms of the 1/f noise based on a specific model of the device. We found that the quality of the gate dielectric and its interface may determine the dominant noise mechamism. Three theories have been formulated to explain the origin of 1/f noise in FET devices: the carrier number fluctuation (∆N) theory[1], the mobility fluctuation (∆µ) theory [2], and the ∆N - ∆µ theory [3], which assumes that effects of insulator charge fluctuations affect the carrier mobility at the interface. The ∆N - ∆µ theory reduces to the ∆N model when the surface mobility is not affected by carrier number fluctuation. According to the ∆N - ∆µ theory [3]the plot of SID(f)/ID 2 and [gm/ID]2 against ID (gm being the transconductance and ID the drain current) allows us to identify the noise mechanism. When both curves are parallel, 1/f noise must be due to carrier number fluctuation. If there is a slight deviation from this parallel behavior, it must be due to the correlated surface mobility fludtuation (∆N - ∆µ model). A number of analysis of the noise in OTFTs have been published. In most of them, it is found to be a bulk phenomenon[4,5], and as a result the main mechanism is assumed to be mobility fluctuation. However, very often these analysis are not very complete and are based on crystalline MOSFET models instead of specific OTFT models. On the other hand, it was demonstrated that the analysis must be made over a range wide of bias in order to accurately determine the origin of noise [6,7]. We studied the origin of 1/f noise two polymeric p-type OTFT technologies developed by CEA´Liten (France). We found that in the older technology the slopes, in log-log scale, of SID(f)/ID 2 and [gm/ID]2, versus ID had quite different values. This means that the main mechanism of noise in OTFTs is not the fluctuation of the number of carriers. Plotting SID(f)/I2 Dvs (VGS-Vth) in log-log scale (Vth being the threshold voltage) for devices with different channel lengths, channel width W=2000 µm and at VDS = 1 V, we observed that the extracted slope is close to -1 (Table 1). This indicates that noise is due to the fluctuation of carrier mobility, due to the lower quality of the materials and fabrication defects. The threshold voltage was extracted assuming a physically-based OTFT model with a power-law based model of the field effect mobility [8]. In the second technology, mobility values are higher, 2-3 cm2/(V s). The normalized current noise PSD follows the squared-transconductance ratio variation (Fig. 1), not the inverse of the drain current. We concluded that the low frequency in the targeted devices of the second technology is originated from the carrier number fluctuation due to trapping/release of charge carriers by trap states uniformly distributed within the gate oxide. The extracted values of gate dielectric trap-states density are comparable to values obtained in conventional Si-based MOSFETs [7], indicating the higher quality of the gate dielectric and its interface with the polymeric material compared to the first studied technology and other previously reported OTFT devices. [1] McWhorter A. L.. "1/f noise and germanium surface prosperities," Semiconductor Surface Physics. R. H. Kingdton (Ed), University of Pennsylvania Press, Philadelphia, PA, 1957, pp. 207-228. [2] Hooge F. N., "1/f noise is no surface effect", Physics Letters, 29A (3), 1969, 139–140 [3] Ghibaudo, G., et al..,‘Improved analysis of low frequency noise in field-effect MOS transistors’, Phys. Status Solidi. A , 1991, 124, pp. 571-581 [4] L. Ke, S., et al., “Low frequency noise analysis on organic thin film transistors,” Journal of Applied Physics 104, 124502 (2008). [5] H. Kang and V. Subramanian, “Measurement and analysis of 1/f noise under switched bias in organic thin film transistors,” Applied Physics Letters 104, 023301 (2014). [6] Y. Xu, et al., “Origin of low-frequency noise in pentacene field-effect transistors,” Solid-State Electronics 61, 106–110 (2011). [7] W. E. Muhea, et al.. “1/f noise analysis in high mobility polymer-based OTFTs with non-fluorinated dielectric,” Appl. Phys. Lett. 114, 243301 (2019). [8] C.H. Kim; et al., “A Compact Model for Organic Field-Effect Transistors With Improved Output Asymptotic Behaviors,” IEEE Trans. on Electron Devices, vol. 60, no. 3, pp. 1136-1141, March 2013. Figure 1

Author(s): Bonnassieux, Y; Brabec, CJ; Cao, Y; Carmichael, TB; Chabinyc, ML; Cheng, KT; Cho, G; Chung, A; Cobb, CL; Distler, A; Egelhaaf, HJ; Grau, G; Guo, X; Haghiashtiani, G; Huang, TC; Hussain, MM; Iniguez, B; Lee, TM; Li, L; Ma, Y; Ma, D; McAlpine, MC; Ng, TN; Osterbacka, R; Patel, SN; Peng, J; Peng, H; Rivnay, J; Shao, L; Steingart, D; Street, RA; Subramanian, V; Torsi, L; Wu, Y | Abstract: This roadmap includes the perspectives and visions of leading researchers in the key areas of flexible and printable electronics. The covered topics are broadly organized by the device technologies (sections 1–9), fabrication techniques (sections 10–12), and design and modeling approaches (sections 13 and 14) essential to the future development of new applications leveraging flexible electronics (FE). The interdisciplinary nature of this field involves everything from fundamental scientific discoveries to engineering challenges; from design and synthesis of new materials via novel device design to modelling and digital manufacturing of integrated systems. As such, this roadmap aims to serve as a resource on the current status and future challenges in the areas covered by the roadmap and to highlight the breadth and wide-ranging opportunities made available by FE technologies.

A compact model for dual-material gate graded-channel and dual-oxidethickness with two dielectric constant different cylindrical gate (DMG-GC-DOTTDCD) MOSFET was investigated in terms of transconductance, drainconductance and capacitance. Short channel effects are modeled with simpleexpressions, and incorporated into the core of the model (at the draincurrent). The design effectiveness of DMG-GC-DOTTDCD was monitoredin comparing with the DMG-GC-DOT transistor, the effect of variations oftechnology parameters, was presented in terms of gate polarization and drainpolarization. The results indicate that the DMG-GC-DOTTDCD deviceshave characteristics higher than the DMG-GC-DOT MOSFET. To validatethe proposed model, we used the results obtained from the simulation of thedevice with the SILVACO-ATLAS-TCAD software.

In this paper, a compact equation for calculating energy sub-bands inside III-V gate all around nanowire MOSFET is developed taking into consideration the penetration of the wave function into the gate oxide and the effective mass discontinuity at the semiconductor-oxide interface. The values of the sub-band energies result from solving Schrodinger's equation in cylindrical coordinates is expressed in Bessel functions. We use an approximation for Bessel functions with the introduction of one fitting parameter. Additionally, a compact equation is developed for the potential due to charge associated with the first sub-band inside the semiconductor. The results show very good agreement with self-consistent Schrodinger-Poisson solver data.

This paper presents a novel approach to calculate the band-to-band (B2B) tunneling probability in tunnel-field effect transistors (TFETs) for the usage in compact models. The tunneling barrier is defined by a compact solution of the electrostatics and is approximated by an area equivalent triangular profile. For this profile the Wentzel-Kramers-Brillouin approximation (WKB) is applied. Referring to the area instead of the electric field at single points is shown to be more robust regarding numerical stability. By comparing the results of the approach with numerical TCAD Sentaurus simulation data of a double-gate (DG) TFET for various bias conditions and geometric positions within the device, the numerical stability as well as the limitations are demonstrated. Furthermore, the comparison to a quasi-2D WKB approach, the derived model shows a better fit to TCAD data at a reduced complexity.

In this paper, we present a comparison study on the performance of cylindrical gate (CG) MOSFET with graded channel doping (GC), dual metal gate (DMG) and dual oxide thickness (DOT). We develop compact model of short channel characteristics like drain current density, transconductance and drain conductance for this new structure (GC-DMG-DOT) SG MOSFET by solving 2D Poisson equation. The results are compared with the DMG MOSFET and DMG-DOT MOSFET devices. The model results are validated by numerical simulation results obtained by commercially simulator TCAD ATLAS.

The influence of Schottky barriers at NiSi 2 contacts of Si Planar p-TFETs on Ultrathin Body [1] is analyzed in terms of deviations between measurements, TCAD simulations and a proposed compact model for the intrinsic capacitances in TFETs presented in [2]. A theory for the reason of the deviations for the intrinsic capacitances is evolved and discussed. Additionally, TCAD simulations are performed to support the theory.

In this paper a two-dimensional analytical Tunnel-FET model is revised. It is used to evaluate performance enhancing measures for the TFET regarding device geometry and physical effects. The usage of hetero-junctions is discussed and a way to suppress the ambipolar behavior of the TFET is shown. In focus of this work are the emerging variability issues with this new type of device. Random-dopant-fluctuations (rdf) have a major influence on the device performance. This effect is analyzed and compared with rdf effects in a MOSFET device. The drawn conclusions lead to a re-evaluation of performance limiting aspects of fabricated TFET devices.

Electronic sensors based on graphene have a high potential in many applications, due to the unique properties of the graphene material. This study is a review where the authors discuss the properties of graphene which are useful to sensing applications and they report and describe different types of graphene electronic sensors: biological, mechanical, gas and chemical sensors. They also discuss the ways to functionalise graphene and the used device structures. They compare the performance of the main types of biological, mechanical and chemical sensors. Finally, they explain the future challenges of graphene-based sensors, in order to make graphene sensing systems and smart sensors, which would be their main breakthrough application.

In this work a compact analytical model for short-channel double-gate junctionless transistor is presented, considering variable mobility and the main short-channel effects as threshold voltage roll-off, series resistance, drain saturation voltage, channel shortening and saturation velocity. The threshold voltage shift and subthreshold slope variation is determined through the minimum value of the potential in the channel. Only eight model parameters are used. The model is physically-based, considers the total charge in the Si layer and the operating conditions in both depletion and accumulation. Model is validated by 2D simulations in ATLAS for channel lengths from 25 nm to 500 nm and for doping concentrations of 5 × 1018 and 1 × 1019 cm−3, as well as for Si layer thickness of 10 and 15 nm, in order to guarantee normally-off operation of the transistors. The model provides an accurate continuous description of the transistor behavior in all operating regions.

DC thermal effects modelling for nanometric silicon-on-insulator (SOI) and bulk fin-shaped field-effect transistors (FinFETs) is presented. Among other features, the model incorporates self-heating effects (SHEs), velocity saturation and short-channel effects. SHEs are analysed in depth by means of thermal resistances, which are determined through an equivalent thermal circuit, accounting for the degraded thermal conductivity of the ultrathin films within the device. Once the thermal resistance for single-fin devices has been validated for different gate lengths and biases, comparing the modelled output characteristics and device temperatures with numerical simulations obtained using Sentaurus Device, the thermal model is extended by circuital analysis to multi-fin devices with multiple fingers. An analytical thermal resistance model for SOI and bulk FinFETs is developed.Self-heating has been included in a drain current model for SOI and bulk FinFETs.The FinFET thermal resistance model includes the role of multiple fingers and fins.

An analytical and scalable model for the threshold voltage in FinFETs has been developed by solving the 3-D Poisson equation using appropriate techniques. The model is also based on a physical analysis of the conduction path. The mobile charge term was considered in the 3-D Poisson's equation to be solved. The threshold voltage is defined as the gate voltage to obtain a certain threshold charge density. Due to its 3-D basis, the model inherently accounts for short-channel effects, such as the threshold voltage roll-off and the Drain Induced Barrier Lowering effect. A very good agreement with 3-D numerical simulations has been observed.

In this paper, DC characteristics of an AlGaN/GaN on sapphire high-electron mobility transistor (HEMT) are measured, numerically simulated, and modelled accounting for self-heating effects (SHEs), with the main electrical parameters being extracted. Decomposing the transistor thermal resistance into the buffer and substrate components, our study can be easily extended to other substrate materials. Thus, sapphire is substituted with silicon, molybdenum, and SiC, which reduce current-collapse due to SHEs thanks to their considerably higher thermal conductivity, which improves transistor performance. Furthermore, we implement a compact model available for AlGaN/GaN HEMTs, incorporating the temperature dependence of extrinsic source/drain ohmic resistances, which are numerically evaluated for the different substrates.

This paper presents a DC/AC compact model for double-gate (DG) tunnel field-effect transistors (TFET) which is based on a unified analytical modeling framework. The closed-form model shows a good agreement with both, TCAD simulations and measurements on test structures. A Verilog-A implementation allows for a quick performance evaluation of the DC performance of logic cells. Results of a complementary TFET inverter are in good agreement to measurements. Simulations of an 8T SRAM cell clearly show the critical influence of the ambipolar behavior and leakage current on the performance. The fundamental analytical modeling framework provides deeper physical insight while considering additional effects as trap-assisted tunneling (TAT), junction profile steepness and hetero structures.

Since the last few years, Tunnel-FETs (TFET) have moved into the center of focus. The device has the physical property to go below the milestone of 60mV/dec slope, which cannot be achieved by standard MOSFETs. In the meantime, there exists a great diversity of TFETs. In order to accurately model this TFET variety, not only a precise potential calculation is sufficient. A similar precision is needed to calculated the tunneling current. There exist some methods to calculate the tunneling current in TFETs such as the Wentzel-Kramers-Brillouin (WKB) and Kane's equation. Since the tunneling current is a quantum mechanical effect, the Non-Equilibrium Green's Function (NEGF) is also able to accurately calculate this type of current. This work presents a combination of an accurate potential calculation for TFETs with an 1D compact non-iterative NEGF based current calculation method. Since the applied NEGF deals just with one conduction band and does not consider the valence band, mathematical approximations are introduced to map these two bands into an equivalent description by only one conduction band. The results show an accurate current behavior in the on- and off-state of the device.

The massive scaling of semiconducting devices is still the most favorable way to enhance device performance to this day. This leads to emerging ultra low power devices with channel lengths down to 14 nm [1]. In this small dimensions the discretization of doping profiles gains influence on the device current, namely random dopant fluctuations (RDF). Therefore, the topic of variability in terms of fabricating these devices is getting more and more important. The simulate on analysis in this paper should give a deeper insight on the variability problems emerging in this new dimension regimes regarding doping discretization and fabrication tolerances. An improved model is introduced which allows an estimation of the RDF-based threshold voltage deviation σv th for MOSFET devices. The simulations are done using randomized profiles with the FEM-Simulator TCAD Sentaurus.

In this paper a static noise margin (SNM) analysis is done for an 8T SRAM cell build up with complementary tunnel-FETs (TFETs). The simulations are done with the help of a Verilog-A implemented 2D DC compact model for a double-gate (DG) TFET, published in [1]. The compact model is adapted to measurement data of fabricated nanowire (NW) GAA TFETs before analyzing the hold/read and write SNM of the 8T TFET SRAM cell. The impact of the ambipolar behavior as well as the unidirectional current of TFETs on the SRAM cell layout and simulation are taken into account and analyzed in this work. Furthermore, the impact of various supply voltages and device widths of the access transistors on the resulting SNM are investigated.

In this paper a compact model for intrinsic capacitances for Tunnel field-effect transistors (TFETs) is presented. The model is derived from the carrier concentration and current flowing the channel of a Si Double-Gate (DG) n-type TFET. It represents a particularly good estimation of TFET capacitances and the flexibility of this model makes it possible to apply it for single-gate or p-type TFETs as well. To verify the model, the results are compared with TCAD Sentaurus simulations as well as measurement data. In both case model shows satisfying results.

This letter presents an RF noise model for AlGaN/GaN HEMTs. The model is based on active line approach and concept of two ports linear noise theory. Short channel effects such as channel length modulation and velocity saturation are considered in the model. The noise generated from the pinch off region is taken into account as well. Some of FET noise parameters are calculated and experimentally verified.

Filiació URV: SI DOI: 10.1016/j.sse.2017.02.004 URL: http://www.sciencedirect.com/science/article/pii/S0038110117301077 Memòria In this paper we provide solutions to update a long channel model in order to take into account the short channel effects. The presented model is for the junctionless GAA MOSFETs. The resulting model is analytical, explicit and valid for depletion and accumulation regimes, and consists of simple physically based equations, for better understanding of this device, and also easier implementation and better computation speed as a compact model. The agreement with TCAD simulations is very good.

In general most modeling approaches for organic field-effect transistors (OFETs) are based on the typical MOSFET equations. The threshold voltage is usually a fitting parameter without relation to physical parameters hence the impact of their variability on the threshold voltage is not clear. The presented modeling approach is charge based with a continuous equation for the channel current in organic field-effect transistors from below to above threshold. The model provides a physics based parameter set related to trap states, and a compatible parameter set from a circuit designer’s perspective. An expression for the threshold voltage is derived depending on the density of trap states. The model considers a power-law mobility model, parasitic contact resistances and channel length modulation effects and is verified with measurements on OFETs fabricated with small molecules.

10.1109/TED.2014.2342273 Analytical and explicit expressions are derived for intrinsic capacitances of the junctionless gate-all-around transistor, from the charge-control model, valid in the two regions of operation, depletion mode and accumulation mode. The advantage of this model is that it reduces to simple expressions for each region, giving a higher computation speed. We obtain very good agreement between the calculated capacitance characteristics and 3-D numerical device simulations

Calculation of the carrier concentrations in semiconductors using the Fermi-Dirac integral requires complex numerical calculations; in this context, practically all analytical device models are based on Boltzmann statistics, even though it is known that it leads to an over-estimation of carriers densities for high doping concentrations. In this paper, a new approximation to Fermi-Dirac integral, called Pseudo-Boltzmann model, is presented for modeling junctionless transistors with high doping concentrations.

10.1016/j.microrel.2014.01.020 This paper presents a method to deposit titanium oxide (TiOx) films from a sol containing IV titanium isopropoxide Ti[OCH(CH3)2] 4, 2-methoxyethanol, CH3OCH2CH2OH and ethanolamine H2NCH2CH2OH, in order to obtain layers with thickness above 220 nm with the required characteristics to be used in Metal-Insulator-Semiconductor, MIS, structures and polymeric thin film transistors, PTFTs. The effect of using different component ratios is described. The dielectric constant was in the order of 12, the critical electric field was 5 × 105 V/cm and the density of states at the interface was less than 1 × 1011 cm-2. The analysis of MIS structures prepared with these TiOx layers shows that they are suitable for using in PTFTs. The fabrication of independent bottom gate PTFTs with poly(3-hexylthiophene), P3HT, on top of the TiOx layer is described, obtaining a major reduction in the operation voltage range from -30 V to -4 V, while maintaining the typical mobility for P3HT PTFTs

A new charge-based compact analytical model for Symmetric Double-Gate Junctionless Transistors is presented. The model is physically-based and considers both the depletion and accumulation operating conditions including the series resistance effects. Most model parameters are related to physical magnitudes and the extraction procedure for each of them is well established. The model provides an accurate continuous description of the transistor behavior in all operating conditions. Among important advantages with respect to previous models are the inclusion of the effect of the series resistance and the fulfilment of being symmetrical with respect to drain voltage equal to zero. It is validated with simulations for doping concentrations of 5 × 1018 and 1 × 1019 cm−3, as well as for layer thickness of 10 and 15 nm, allowing normally-off operation.

10.1109/TED.2013.2295772 We present a compact capacitance model for organic thin-film transistors (OTFTs), which is valid not only in the accumulation regime but also in the partial and total depletion regimes. The parameters applied in the model are analytically extracted from the current-voltage characteristics of the devices, using a previously developed unified model and the parameter extraction method. The overlap capacitance effect is taken into account, and the frequency dependence is considered empirically by means of the insulator permittivity. Comparisons between modeled and experimental gate-to-channel capacitances of staggered upper contact p-channel OTFTs based on P3HT-PMMA and PCDTBT-PMMA show the validity of the model at low and medium frequencies.

Reference EPFL-ARTICLE-198077doi:10.1109/Ted.2013.2295931View record in Web of Science Record created on 2014-04-02, modified on 2017-05-10

We suggest a simple and versatile approach for the correct account of differential conductance in the saturation regime that provides a monotonic decrease of the differential conductance from its maximum value to its minimum positive or even negative value. We present all equations also in normalized form, which simplifies the analysis and usage of the approach. On the basis of the suggested approach, we have developed 'internal' does not include source and drain resistance metal-oxide-semiconductor field-effect transistor compact model and have incorporated one into an Electronic Design Automation software Symica as Verilog-A module. Copyright © 2014 John Wiley & Sons, Ltd.

Organic TFTs (OTFs) are very promising devices for flexible, wearable and printed electronics. Nowadays OTFT performances are already comparable to a-Si:H TFTs. In order to design OTFT circuits, physically-based compact models for the OTFT DC, AC and transient characteristics are needed. This requires a correct understanding of the physical effects affecting OTFT behavior. Despite a number of compact I-V models have been presented, only a few C-V models have been published [1-4]. Besides, very few models have considered the temperature dependence, even though temperature analysis is instrumental to identify relevant physical effects. Moreover, most of those temperature studies have been carried out only for I-V characteristics at high temperatures [5] and the very few analysis at low temperatures have not targeted all parameters [6]. In this work, we present a complete study of both current and gate capacitance in OTFTs for temperatures ranging from 150K to 350K. Parameters were extracted using a unified model and extraction method specific to OTFTs, based on assuming an exponential DOS and variable range hopping [7-8]. The dependences of model parameters with the temperature are analyzed. In order to carry out the temperature study of C-V characteristics, we improved an analytical capacitance model [1, 3] for OTFTs in order to be valid from the depletion to the accumulation regime with continuous and smooth regime transitions as well as for the first order gate capacitance derivative. The key parameters used in the capacitance model are the same as those of I-V characteristics and were extracted from them [4, 7]. Furthermore, we show that from the first order gate capacitance model derivative, we can identify the different operating regimes and obtain the threshold voltage () and band-flat voltage ( at different temperatures. We performed measurements on small-molecule OTFTs manufactured in CEA-Liten (Grenoble- France). The OTFTs under study were top gate bottom contact multifingers with and. Our model shows good agreement with the experimental I-V (Fig. 1) and C-V (Fig. 2) characteristics, and the first order capacitance model derivative (Fig. 3) from for temperatures ranging from 120K to 350K, and for frequencies up to 10 kHz. [1] Castro-Carranza, A., et al., (2012). Organic thin-film transistor bias-dependent capacitance compact model in accumulation regime. IET circuits, devices & systems, 6(2), 130-135 [2] Li, L., Marien, et al.,, “Compact Model for Organic Thin-Film Transistors” IEEE Electr Dev Let, vol. 31, no. 3, pp. 210-212, Mar. 2010. [3] Fadlallah, M., et al. “Modeling and characterization of organic thin film transistors for circuit design” J. Appl. Phys, vol. 99, no.104504, May 2006. [4] Estrada, M., et al.,(2013). Frequency and voltage dependence of the capacitance of MIS structures fabricated with polymeric materials. IEEE Transactions on Electron Devices, 60(6), 2057-2063. [5] Estrada, et al., (2010). Modeling the behavior of charge carrier mobility with temperature in thin-film polymeric transistors. Microelectronic Engineering, 87(12), 2565-2570. [6] Haddad, C., et al., Organic Electronics (2018), https://doi.org/10.1016/j.orgel.2018.06.037 [7] Estrada, M., at al., (2005). Accurate modeling and parameter extraction method for organic TFTs. Solid-state electronics, 49(6), 1009-1016. [8] Estrada, M.,et al., . (2008). Mobility model for compact device modeling of OTFTs made with different materials. Solid-State Electronics, 52(5), 787-794. Figure 1

Organic-inorganic hybrid quantum dot (QD) based light emitting diodes (LEDs) have been investigated. Stacked hybrid QD LED structures, based on cadmium selenide QD with cadmium sulfide barrier shells, have been fabricated at the Universtiat Rovira i Virgili using spin coating techniques. These have been modelled, with Technology Computer Aided Design (TCAD) software, using two different carrier conduction models. Two quantum confinements models are used to predict the electronic transport through these stacks. A 1D simulation of a stack with a single QD mono-layer, using the Silvaco Radiant tool based on the Atlas engine, is reported. This approach allows device designers to optimise the current density and spectral response as a function of QD radius (as shown in the figure) and transport layer thicknesses. Furthermore, a second approach using a 3D QD simulation in which the user can investigate the effect of the QD radius and barrier layer thickness on the carrier confinement in the structures is shown. This work demonstrates the capability of 1D simulations, using the Radiant software tool, to model the behavior of single QD mono-layer structures. The user friendly input graphical user interface, as well as the speed of the simulation, helps to iterate the design quickly to optimise QD size and transport layer thicknesses for maximum intensity at the desired spectral output. Figure 1

The saturation current of an organic field-effect transistor was calculated numerically by bisection method taking into account the source and drain resistances. Dependences of the saturation current as a function of the gate voltage, centred on the threshold voltage, and as a function of the "extrinsic" (taking into account the source and drain resistances) saturation voltage are presented. The calculations were carried out using an iterative scheme assuming the saturation current to be zero for iteration zero and using different numbers of iterations. In addition, we carried out a compact modelling of the saturation current in the framework of the approach we proposed earlier. It is shown that when in the equation for the compact modelling initial value of saturation current of zero value (corresponding to zero iteration) is used, a good agreement with the bisection method of over a wide range of gate voltages is obtained.

We propose a unified DC and flicker noise model for bottom-gate amorphous InGaZO (a-IGZO) thin film transistors (TFTs) with an etch stop layer (ESL) valid for subthreshold, linear, and saturation regimes. A recent study carried out by our group about the origin of 1/f noise in four ESL a-IGZO TFTs with gate lengths 15, 20, 30, and 50 μ m and a width of 100 μ m revealed that carrier number fluctuation is the dominant mechanism of flicker noise in these specific devices and the contact resistances do not significantly contribute to the overall noise level. In this paper, we extended the work to develop a physics based 1/f noise model for ESL a-IGZo TFTs. The unified model and parameter extraction method, a technique developed for accurate parameter extraction and modeling of TFT device characteristics, is adapted to develop the I-V model. The noise model is subsequently derived taking into account the observed correlated mobility fluctuation based on the unified 1/f noise modeling idea. Results showed an excellent agreement between the experimental and modeled data for both the DC and flicker noise behavior of sample ESL a-IGZO TFTs over a broad range of bias conditions, at 298, 315, and 333 K operating temperatures.

10.1016/j.sse.2013.02.040 Transport mechanisms in nanocrystalline ZnO Thin Film Transistors (TFT) were investigated in a wide temperature range. The channel is located at the ZnO-SiO2 interface and controlled with a bottom gate as in a back-channel SOI MOSFET. In this work, we propose suitable mobility models that are able to provide a good agreement with the experimental results. Not only do these models account for the regular carrier transport mechanisms but they also address the physical properties of nanocrystalline ZnO films including the effect of grain boundaries. Simple parameter extraction techniques are explored and validated with numerical calculations. Our work highlights that nanocrystalline ZnO TFT provides high mobility, low threshold voltage and reasonable subthreshold swing due to good interface quality between the ZnO film and the gate insulator. The variation of these parameters at low temperature is measured and compared to the typical behavior in SOI MOSFETs.