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In this paper, we present a two-phase design space exploration (DSE) approach to address the problem of real-time application mapping on a flexible MPSoC platform. Our approach is composed of two independent phases - analytical estimation/pruning and system simulation - communicating via a well-defined interface. The strength of the resulting strategy is twofold. On one hand, it is capable of combining the benefits of analytical models and simulation tools (i.e., speed and accuracy). And on the other hand, separating pruning and evaluation phases facilitates the integration of different or additional pruning techniques as well as other existing simulation tools. Finally, we also present several proof-of-concept DSE experiments to illustrate distinct aspects and capabilities of our framework. These experimental results reveal that our approach, compared to other approaches based only on analytical estimation models or simulations guided by e.g. genetic algorithms, not only can explore a large design space and reach a valid solution in a time-efficient way, but also can provide solutions optimizing resource usage efficiency, system traffic and processor load balancing.

The use of -doping in HFET processes has made the development of transistor circuits and logic gates possible, for very high-frequency/speed or low-power applications. This behaviour of the PHFET device is due to fast quantum well conduction. However, the effect of the operating temperature range is critical. This range depends on the transistor and circuit activity, the packaging technique, and the external operating conditions. Temperature strongly affects the device ability to confine the current flow into the quantum well channel. In this paper the effect of temperature and -doping concentration on the performance of the device is investigated by means of simulated experiments. The results are analytically and qualitatively discussed, showing how to fine tune the -doping concentration in order to optimize the P-HFET behaviour from medium- to high-temperature conditions, [300, 500] K.

Two different techniques that allow the implementation of embedded ROMs using a conventional GaAs MESFET technology are presented. The first approach is based on a novel circuit structure named low leakage current FET circuit (L2FC), which reduces significantly subthreshold currents. The second approach is based on pseudo current mode logic (PCML) which is by far the best choice in terms of noise margin levels. This characteristic is found to be the key factor when implementing GaAs ROM's because of its degradation as the number of word lines is increased. A 5-Kb ROM and a 2-Kb ROM were designed giving delays in the order of 2 ns and less than 1 ns, respectively. The results demonstrate the effectiveness of these techniques and their significance toward improving the noise margin.

A novel GaAs logic family, pseudodynamic latched logic (PDLL), is presented in this paper. It is composed of a dynamic circuit where the logic is performed and a static latch whose function is to permanently refresh the stored data on a dynamic node. Because of this hybrid structure, PDLL takes advantage of both static and dynamic families and thus, permits implementation of very complex structures with good speed-area power tradeoff. Moreover, the inclusion of the latch permits this class of logic family to be highly efficient for pipelined systems working even at high temperature without loss of data due to leakage currents. Barrel-shifters, programmable logic arrays (PLA's), and carry lookahead adders (CLA's) were verified by simulations demonstrating its feasibility for the development of high-performance very large scale integration (VLSI) systems.

This paper describes key concepts in the design and implementation of a deblocking filter (DF) for a H.264/SVC video decoder. The DF supports QCIF and CIF video formats with temporal and spatial scalability. The design flow starts from a SystemC functional model and has been refined using high-level synthesis methodology to RTL micro architecture. The process is guided with performance measurements (latency, cycle time, power, resource utilization) with the objective of assuring the quality of results of the final system. The functional model of the DF is created in an incremental way from the AVC DF model using OpenSVC source code as reference. The design flow continues with the logic synthesis and the implementation on the FPGA using various strategies. The FPGA implementation is capable to run at 100 MHz, and macro blocks are processed in 6, 500 clock cycles for a throughput of 130 fps for QCIF format and 37 fps for CIF format. A validation platform has been developed using the embedded PowerPC processor in the FPGA, composing a SoC that integrates the tasks for frame generation and visualization on a TFT screen. The FPGA implements both the DF core and a General Purpose Memory Controller (GPMC) slave core. Both cores are connected to the PowerPC440 embedded processor using Local Link interfaces. The FPGA also contains a local memory capable of storing information necessary to filter a complete frame and to store a decoded picture frame. The complete system is implemented in a Virtex5 FX70T device. An ASIC implementation of the deblocking filter has been done using UMC CMOS 65nm technology. The ASIC implementation is running at 181.8 MHz, occupying an area of 596, 392.4 μm2.

High dynamic range displays based on dual panel LCD are a viable option for building a low-cost solution for providing high bit depth visualization systems. One of the factors limiting the usability of this type of displays are the computation requirements of the algorithm necessary for correct visualization using the two stacked panels. In this work we present the methodology and the results of mapping this algorithm on a CPU+GPU platform using the OpenCL 1.1 API. Visualization of a 2048×2048 image when executed on a CPU+GPU (AMD Radeon V7800) platform is performed up to 7.6 times faster then when only the CPU is used. The first results are promising and encourage the use of GPUs (or APUs) for acceleration of this kind of processing.

This paper describes key concepts in the design and implementation of a deblocking filter (DF) for a H.264/SVC video decoder. The DF supports QCIF and CIF video formats with temporal and spatial scalability. The design flow starts from a SystemC functional model and has been refined using high‐level synthesis methodology to RTL microarchitecture. The process is guided with performance measurements (latency, cycle time, power, resource utilization) with the objective of assuring the quality of results of the final system. The functional model of the DF is created in an incremental way from the AVC DF model using OpenSVC source code as reference. The design flow continues with the logic synthesis and the implementation on the FPGA using various strategies. The final implementation is chosen among the implementations that meet the timing constraints. The DF is capable to run at 100 MHz, and macroblocks are processed in 6,500 clock cycles for a throughput of 130 fps for QCIF format and 37 fps for CIF format. The proposed architecture for the complete H.264/SVC decoder is composed of an OMAP 3530 SOC (ARM Cortex‐A8 GPP + DSP) and the FPGA Virtex‐5 acting as a coprocessor for DF implementation. The DF is connected to the OMAP SOC using the GPMC interface. A validation platform has been developed using the embedded PowerPC processor in the FPGA, composing a SoC that integrates the frame generation and visualization in a TFT screen. The FPGA implements both the DF core and a GPMC slave core. Both cores are connected to the PowerPC440 embedded processor using LocalLink interfaces. The FPGA also contains a local memory capable of storing information necessary to filter a complete frame and to store a decoded picture frame. The complete system is implemented in a Virtex5 FX70T device.

In this article, we present a flexible and extensible system-level MP-SoC design space exploration (DSE) infrastructure, called NASA. This highly modular framework uses well-defined interfaces to easily integrate different system-level simulation tools as well as different combinations of search strategies in a simple plug-and-play fashion. Moreover, NASA deploys a so-called dimension-oriented DSE approach, allowing designers to configure the appropriate number of, well-tuned and possibly different, search algorithms to simultaneously co-explore the various design space dimensions. As a result, NASA provides a flexible and re-usable framework for the systematic exploration of the multidimensional MP-SoC design space, starting from a set of relatively simple user specifications. To demonstrate the capabilities of the NASA framework and to illustrate its distinct aspects, we also present several DSE experiments in which, for example, we compare NASA configurations using a single search algorithm for all design space dimensions to configurations using a separate search algorithm per dimension. These proof-of-concept experiments indicate that the latter multidimensional co-exploration can find better design points and evaluates a higher diversity of design alternatives as compared to the more traditional approach of using a single search algorithm for all dimensions.

In this work we present a novel execution flow for the super-resolution image restoration (SRIR) non-uniform grid projection algorithm -- the macroblock-level flow. The novel flow is compared with the reference frame-level flow. The frame-level flow is characterized by the fact that transitions from one step of the algorithm to another occur only after the current step is carried out for all macro blocks (MBs) of the frame being currently processed. The novel flow carries out complete processing of one MB before the processing of another MB starts. The memory requirements of both schemes are evaluated in detail and compared. The study on the achievable memory reduction in total memory requirements was carried out for different values of the algorithm parameters: the MB size, scale factor, search area size and number of reference frames included in the sliding frame window. The results show quantitatively that the parameter that influences storage instantiation the most and has the greatest influence on the total memory size is the number of reference frames in the sliding frame window. The conducted study shows that, for a QCIF frame format, switching from frame-to macroblock-level is feasible and fully validated functionally and that the new execution flow can lead to memory reduction by a factor of 6.8 to 40, depending on the algorithm parameters values. Memory reduction greatly facilitates hardware implementations of the algorithm and this is the main result claimed. But the reduction in memory size comes at the cost of increasing the number of memory accesses and therefore communications traffic. The increase noted in memory accesses it to be quantified in future work as well as the potential impact on power consumption. The reduction in memory size might also make it fit on chip without turning to external memory, thereby reducing power consumption. This trade off in power is yet to be quantified.

The ability of additional detail extraction offered by the super-resolution image reconstruction (SRIR) algorithms greatly improves the results of the process of spatial images augmentation, leading, where possible, to significant objective image quality enhancement expressed in the increase of peak-signal-to-noise ratio (PSNR). Nevertheless, the ability of providing hardware implementations of fusion SRIR algorithms capable of producing satisfactory output quality with real-time performance is still a challenge. In order to make the hardware implementation feasible a number of trade-offs that compromise the outcome quality are needed. In this work we tackle the problem of high resource requirements by using a non-iterative algorithm that facilitates hardware implementation. The algorithm execution flow is presented and described. The algorithm output quality is measured and compared with competitive solutions including interpolation and iterative SRIR implementations. The tested iterative algorithms use frame-level motion estimation (ME), whereas the proposed algorithm relies on, performance-wise better, block matching ME. The comparison shows that the proposed non-iterative algorithm offers superior output quality for all tested sequences, while promising efficient hardware implementation able to match -at least- the software implementations in terms of outcome quality.

This work addresses the problem of analytical multiobjective optimization of combinational DCFL/SDCFL GaAs MESFETs IC. The critical path is determined by means of the GASTIM timing analyzer. The optimization strategy takes into account the slope dependency, the fan-out and the wiring capacitances. The results show that it is possible to decrease the power consumption without degrading the propagation delay. We are not aware of any automatic tool able to solve the optimization task when designing circuits on GaAs material.

A methodology is presented to calculate delays in DCFL/SDCFL GaAs circuits. The model has been implemented in a prototype timing analyzer. Input-slope influences and overlapping input transitions are taken into account. The simulation results show that the proposed model can predict the delay time within 15% error and with a speed-up of four orders of magnitude for several circuits tested as compared with HSPICE simulations.

Power dissipation is a conflicting criterium for designing high performance VLSI GaAs circuits. This paper describes a power formulation to estimate the consumption in SDCFL/DCFL circuits. It uses polynomial expressions in order to fit the power values measured with HSPICE. Besides these expressions are suitable for incorporation into an optimization strategy. The agreement with measured results is excellent, with error less than 10% over the tested cases.

In this paper we present the design and simulation of the Integer and Control Units of AsGaR, a RISC processor featuring a proprietary streamlined architecture. Running at a clock speed of 440 MHz, it delivers a peak throughput of 110 MIPS. The work reported here makes clear the level of complexity faced by this kind of designs and the need to use a wholistic approach considering all aspects of system implementation. AsGaR has been implemented in a TriQuint GaAs process, using a standard cell library. The current shortage of tools for GaAs design has been overcome by adapting the Cadence/Edge environment to this technology. Simulation has been done by describing the cell library in System Hilo and Verilog.

System-level simulation and design space exploration (DSE) are key ingredients for the design of multiprocessor system-on-chip (MP-SoC) based embedded systems. The efforts in this area, however, typically use ad-hoc software infrastructures to facilitate and support the system-level DSE experiments. In this paper, we present a new, generic system-level MP-SoC DSE infrastructure, called NASA (Non Ad-hoc Search Algorithm). This highly modular framework uses well-defined interfaces to easily integrate different system-level simulation tools as well as different combinations of search strategies in a simple plug-and-play fashion. Moreover, NASA deploys a so-called dimension-oriented DSE approach, allowing designers to configure the appropriate number of, possibly different, search algorithms to simultaneously co-explore the various design space dimensions. As a result, NASA provides a flexible and re-usable framework for the systematic exploration of the multi-dimensional MP-SoC design space, starting from a set of relatively simple user specifications. To demonstrate the distinct aspects of NASA, we also present several DSE experiments in which we, e.g., compare NASA configurations using a single search algorithm for all design space dimensions to configurations using a separate search algorithm per dimension. These experiments indicate that the latter multi-dimensional co-exploration can find better design points and evaluates a higher diversity of design alternatives as compared to the more traditional approach of using a single search algorithm for all dimensions.

In this work we present a timing analyzer suitable for dealing with GaAs MESFET SDCFL logic family and it uses inverters as an aproximation for multiple input gates. The model consists in an adaptation from a developed methodology for NMOS and CMOS Si logic families. The model has been validated against SPICE simulations. Measured errors are lower than 9%.

El sindrome de Mounier-Kuhn o traqueobroncomegalia es una enfermedad congenita rara, que se caracteriza por una importante dilatacion de la traquea y los bronquios principales. Se acompana de una tos ineficaz y a menudo complicada con infecciones pulmonares recurrentes y bronquiectasias. Existe un amplio espectro de formas clinicas de presentacion, que oscilan entre formas con una escasa afectacion de la capacidad funcional y otras progresivas, que evolucionan a una insuficiencia respiratoria que puede ser letal. Presentamos un caso excepcional de hemoptisis masiva secundaria a la presencia de aspergilomas pulmonares y bronquiectasias bilaterales, en la que la arteriografia bronquial con embolizacion o la reseccion quirurgica no fueron suficientes para solucionar estas complicaciones.

The present paper describes an Electronic System Level (ESL) design methodology which was established and employed in the creation of a H.264/AVC baseline decoder. The methodology involves the synthesis of the algorithmic description of the functional blocks that comprise the decoder, using a high level synthesis tool. Optimization and design space exploration is carried out at the algorithmic level before performing logic synthesis. Final, post-place and route implementation results show that the decoder can operate at the target frequency of 100 MHz and meet real time requirements for QCIF frames.

In this paper, we present the modelling of a real-time tracking system on a Multi-Processor System on Chip (MPSoC). Our final goal is to build a more complex computer vision system (CVS) by integrating several applications in a modular way, which performs different kind of data processing issues but sharing a common platform, and this way, a solution for a set of applications using the same architecture is offered and not just for one application. In our current work, a visual tracking system with real-time behaviour (25 frames/sec) is used like a reference application, and also, guidelines for our future CVS applications development. Our algorithm written in C++ is based on correlation technique and the threshold dynamic update approach. After an initial computational complexity analysis, a task-graph was generated from this tracking algorithm. Concurrently with this functionality correctness analysis, a generic model of multi-processor platform was developed. Finally, the tracking system performance mapped onto the proposed architecture and shared resource usage were analyzed to determine the real architecture capacity, and also to find out possible bottlenecks in order to propose new solutions which allow more applications to be mapped on the platform template in the future.

We empirically assess the winner’s curse effect in auctions for toll road concessions. First, we investigate the overall winner’s curse effects on bidding behaviour. Second, we account for differing levels of common-value components. Third, we investigate whether the possibility of renegotiation affects the winner’s curse effect. Using a unique dataset of 49 concessions, we show that the winner’s curse effect is particularly strong, i.e. bidders bid less aggressively when they expect more competition. In addition, we observe that this effect is larger for projects where the common uncertainty is greater, and is dampened in weaker institutional frameworks, in which renegotiations are easier.

Advances in the development of digital GaAs integrated circuits have progressed to the point that designers of signal and data processors can discern the system applications for which GaAs is best suited. Basic computation primitives in DSP and image processing systems are usually adders, multipliers and delay elements. In this paper we present the results of a systematic study conducted to evaluate the influence of layout and design methodologies, both conventional and innovative ones, on the performance of those DSP computation primitives.

A new method for the analysis of parallel transmission lines in multilayered dielectric media is presented. The method is based on adaptive mixed finite element techniques with improved error estimators. The analysis can be used to extract accurately the interconnect capacitances for circuit and timing simulators in the design and verification phases of high speed digital integrated circuits, and for fine tuning of the technological process for improved performance. As way of example the paper presents the cases of multiconductor and coplanar transmission lines, in typical GaAs IC designs.

In this paper, we present the strategy for evaluating the performance of a variety of configurations of an architecture template for a computer vision system (CVS). For this study a generic model of an architecture is used to address the modular design of the CVS. This modular nature approach could be used to build a more complex system by integrating several applications which perform different kind of data processing issues but sharing a common architecture. In our current work, a visual tracking system with real-time behaviour (25 frames/sec) is modelled and mapped on the model of a pipelined multiprocessor platform. The tracking system performance and shared resource usage were analyzed to determine the real architecture capacity and also to find out possible bottlenecks in order to propose new solutions which allow more applications to be mapped on the platform template in the future.

International audience; We empirically assess the effect of the winner's curse in auctions for toll road concessions, taking into account, to our knowledge for the first time, problems of commitment and enforcement, using a unique dataset of 49 worldwide road concessions.

ISSN: 1566113X; International audience; It has been observed that older high traffic motorways experience lower traffic growth than newer ones (ceteris paribus). This phenomenon is known as traffic maturity; however, it is not captured through traditional time-series long-term forecasts, due to constant elasticity to gross domestic product these models assume. In this paper we argue that traffic maturity results from decreasing marginal utility of transport. The elasticity of individual mobility with respect to the revenue tends to decrease when the level of mobility increases. In order to find evidences of decreasing elasticity we analyse a cross-section time-series sample including 40 French motorways' sections. This analysis shows that decreasing elasticity can be observed in the long term. We then propose a decreasing function for the traffic elasticity with respect to the economic growth, which depends on the traffic level on the road. This model provides a good explanation for the observed traffic evolution and gives a rigorous econometric approach to time-series traffic forecasts.

1 Instituto de Engerharia de Sistemas e Computadores Investigacâo e Desenvolvimento em Lisboa (INESC-ID) and Instituto Superior Tecnico (IST), Universidade Tecnica de Lisboa, 1000-029 Lisboa, Portugal 2Centre for Digital Video Processing, Dublin City University, Glasnevin, Dublin 9, Ireland 3 Signal Processing Laboratory, Ecole Polytechnique Federale de Lausanne (EPFL), 1015 Lausanne, Switzerland 4 Instituto Universitario de Microelectronica Aplicada (IUMA), Universidad de Las Palmas de Gran Canaria, 35017 Las Palmas de Gran Canaria, Spain

This paper presents a simple environment for the verification of AMBA 3 AXI systems in Verification IP (VIP) production called VIPACES (Verification Interface Primitives for the development of AXI Compliant Elements and Systems). These primitives are presented as a not compiled library written in SystemC where interfaces are the core of the library. The definition of interfaces instead of generic modules let the user construct custom modules improving the resources spent during the verification phase as well as easily adapting his modules to the AMBA 3 AXI protocol. This topic is the main discussion in the VIPACES library. The paper focuses on comparing and contrasting the main interconnection schemes for AMBA 3 AXI as modeled by VIPACES. For assessing these results we propose a validation scenario with a particular architecture belonging to the domain of MPEG4 video decoding, which is compound by an AXI bus connecting an IDCT and other processing resources.

In this paper we present a novel methodology to accelerate an MPEG-4 video decoder using software/hardware co-design for wireless DAB/DMB networks. Software support includes the services provided by the embedded kernel mC/OS-II, and the application tasks mapped to software. Hardware support includes several custom co-processors and a communication architecture with bridges to the main system bus and with a dual port SRAM. Synchronization among tasks is achieved at two levels, by a hardware protocol and by kernel level scheduling services. Our reference application is an MPEG-4 video decoder composed of several software functions and written using a special C++ library named CASSE. Profiling and space exploration techniques were used previously over the Advanced Simple Profile (ASP) MPEG-4 decoder to determinate the best HW/SW partition developed here. This research is part of the ARTEMI project and its main goal is the establishment of methodologies for the design of real-time complex digital systems using Programmable Logic Devices with embedded microprocessors as target technology and the design of multimedia systems for broadcasting networks as reference application.

Two approaches are presented in this paper to improve the quality of digital images over the sensor resolution using super-resolution techniques: iterative super-resolution (ISR) and noniterative super-resolution (NISR) algorithms. The results show important improvements in the image quality, assuming that sufficient sample data and a reasonable amount of aliasing are available at the input images. These super-resolution algorithms have been implemented over a codesign video compression platform developed by Philips Research, performing minimal changes on the overall hardware architecture. In this way, a novel and feasible low-cost implementation has been obtained by using the resources encountered in a generic hybrid video encoder. Although a specific video codec platform has been used, the methodology presented in this paper is easily extendable to any other video encoder architectures. Finally a comparison in terms of memory, computational load, and image quality for both algorithms, as well as some general statements about the final impact of the sampling process on the quality of the super-resolved (SR) image, are also presented.

This paper presents VIPACES (Verification Interface Primitives for the development of AXI Compliant Elements and Systems), a simple environment for the verification of AMBA 3 AXI systems in Verification IP (VIP) production. The elements come from the necessity of creating generic modules, in the verification phase, for this widely used protocol. These primitives are presented as a not compiled library written in SystemC where interfaces are the core of the library. The definition of interfaces instead of generic modules let the user construct custom modules improving the resources spent during the verification phase as well as easily adapting his own modules to the AMBA 3 AXI protocol. As validation scenario, results obtained for an AXI bus connecting IDCT and other processing resources for MPEG4 video decoding are presented.

This paper addresses practical considerations for the implementation of algorithms developed to increase the image resolution from a video sequence by using techniques known in the specialized literature as super-resolution (SR). In order to achieve a low-cost implementation, the algorithms have been mapped onto a previously developed video encoder architecture. By re-using such architecture and performing only slight modifications on it, the need for specific, and usually high-cost, SR hardware is avoided. This modified encoder can be used either in native compression mode or in SR mode, where SR can be used to increase the image resolution over the sensor limits or as a smart way to perform electronic zoom, avoiding the use of high-power demanding mechanical parts. Two SR algorithms are presented and compared in terms of execution time, memory usage and quality. These algorithms features are analyzed from a real-time implementation perspective. The first algorithm follows an iterative scheme while the second one is a modified version where the iterative behavioural has been broken. The video encoder together with the new SR features constitutes an IP block inside Philips Research, upon which several System on Chip (SoC) platforms are being developed.

This paper addresses the enhancement of the spatial resolution of a video sequence from a low resolution video sequence in real time. The technique used, known as super-resolution reconstruction, exploits the relative motion from frame to frame that produces sub-pixel shifts. The algorithm, based on a previous version mapped onto a video encoder architecture, is oriented towards a hardware implementation and requires resources optimization. In order to achieve a good resolution improvement, the motion estimation algorithm must produce motion vectors as close to the real ones as possible. At the same time, this motion estimation must match real time requirements. Therefore, an exhaustive technique is applied in combination with a simple segmentation of each frame for a motion prediction refinement. Experimental results have been obtained for a set of video sequences subjected to different motion characteristics.

Trends in multimedia consumer electronics, digital video and audio, aim to reach users through low-cost mobile devices connected to data broadcasting networks with limited bandwidth. An emergent broadcasting network is the digital audio broadcasting network (DAB) which provides CD quality audio transmission together with robustness and efficiency techniques to allow good quality reception in motion conditions. This paper focuses on the system-level evaluation of different architectural options to allow low bandwidth digital video reception over DAB, based on video compression techniques. Profiling and design space exploration techniques are applied over the ASP MPEG-4 decoder in order to find out the best HW/SW partition given the application and platform constraints. An innovative SystemC-based system-level design tool, called CASSE, is being used for modelling, exploration and evaluation of different ASP MPEG-4 decoder HW/SW partitions. System-level trade offs and quantitative data derived from this analysis are also presented in this work.

This paper addresses a low-cost and real-time solution for the implementation of super-resolution (SR) algorithms over SOC (System-On-Chip) platforms in order to achieve high-quality image improvements. Low-cost constraints are accomplished in the sense that SR is performed without developing a specific hardware, but re-using a video encoder IP block. This encoder can be used either in compression mode or in SR mode. This video encoder together with the new SR features constitutes an IP block inside Philips Research, upon which several SOC platforms are being developed. Furthermore, this work can be easily adapted to other video encoder platforms.

This contribution reports our research in developing an integrated inductor library. From a tutorial perspective the main limitations of this element, when grown on standard silicon technologies, are presented, offering measured results taken from a set of fabricated inductors and design guidelines to improve their performance. The modeling aspects are also covered, we present results for different equivalent lumped circuits and parameter extraction styles. From the designer's point of view, we state the main characteristics that a good integrated inductor library should include. We also report our proposed solution for this task consisting in a set of tools to automate the element selection such as their laying-out. This library development procedure and the associated tools cover the lack of these elements in present offered design kits.

This paper presents an approach to improve the quality of digital images over the sensor resolution using superresolution techniques. In order to obtain a feasible low cost implementation, the resources have been restricted to those that can be found in a generic video encoder, i.e.: the motion estimator, the motion compensator, image loop memory, etc. The super-resolution system has been implemented over a codesign platform developed by the Philips Research Laboratories in Eindhoven, while performing minimal changes on the overall hardware architecture. Nevertheless, this methodology can easily be extended to any generic video encoder architecture. The results show important improvements in the image quality, assuming that sufficient sample data is available. Based on these results, some generalizations can be made about the impact of the sampling process on the quality of the super-resolution image.

In this work we propose new equivalent circuit models for integrated inductors based on the conventional lumped element model. Automatic tools to assist the designers in selecting and automatically laying-out integrated inductors are also reported. Model development is based on measurements taken from more than 100 integrated spiral inductors designed and fabricated in a standard silicon process. We demonstrate the capacity of the proposed models to accurately predict the integrated inductor behavior in a wider frequency range than the conventional model. Our equations are coded in a set of tools that requests the desired inductance value at a determined frequency and gives back the geometry of the better inductors available in a particular technology.

This paper discusses and compares solutions for the issue of signalling and synchronization in the heterogeneous architecture multiprocessor paradigm. The on-chip interconnect infrastructure is split conceptually into a data transport network and a signalling network. This paper presents a SystemC based technique for modelling the communication architecture, with different topologies for the synchronization or signalling network. Each topology is parameterised for several communication requirements that define a point in the communication space. A high abstraction model leads to an experimental set-up that eases the analysis of the quantitative and qualitative behaviour of the networks for representative points in the communication space of the system design. The SystemC simulation models developed allow us to obtain information about total simulation time, processing time spent by the coprocessors, data transport time (read/write) used by the coprocessors (including arbitration time), and synchronization time spent by the coprocessors and the network. Another important metric is the coprocessor usage percentage. Results show that splitting data and signalling networks bring additional improvement to the performance of the system. The model applies well when mapping to architectural platforms the application processes expressed by abstract computational models such as Kahn process networks (KPN), synchronous data flow models (SDF), and generalized communicating sequential processes models (CSP).

Advances in fabrication and design technologies have contributed to integrate a complete system on a chip. A system-on-chip (SoC) is generally composed of a microprocessor core, on-chip memory and one or more specific coprocessors IPs. One of the major drawbacks of this approach is the differences in the interfaces that each virtual component (VC) of the SoC presents. The idea of a common bus infrastructure allows us to smooth the system integration and has been considered as a design solution for SoC architectures. This paper presents a review of different alternatives for SoC buses and summarizes some experiences of their use. Different alternatives exist for SoC buses. ARM has proposed AMBA (Advanced Microcontroller Bus Architecture) as an open specification that serves as a framework for SoC design. AMBA is a bus architecture multiplayer for high performance SoC designs. AMBA support multi-master configurations where a bus arbiter must be included. AMBA-Lite is a simpler alternative if you are using only one master. IBM uses CoreConnect Bus architecture as a SoC solution for buses. CoreConnect share some similarities with AMBA because both use a multilayer bus to accommodate different speeds in the system: AHB and PLB can be compared. The same situation occurs for APB and OPB. Other alternatives can be found. Wishbone is an Open Bus Specification form opencores.org that tries to solve the problem of IP integration. The idea is to specify a common interface between cores to accelerate the development of virtual components. VSIA has proposed Virtual Component Interface (VCI) as a solution to solve the problem of virtual component integration. VCI specify three types of protocols depending on the level of complexity: Peripheral, Basic and Advanced VCI. The development of the IPs compatible with any of the SoC buses above presented is a complex problem. One solution is the use of wrappers that adapts the interface of the Virtual Component to the protocol supported by the SoC buses. The two main characteristics of these wrappers are that the increased in latency and area would be as low as possible. The second solution is to design the IP with the final environment in mind.

At 0.25, 0.18 um processes and beyond important process variations occur not only from one fab to another among batches. Moreover as we approach the realm of deep-submicron design, process variations even across a single die are predicted to become a major source of spread. Reduced signal levels, noise margins and timing windows are all contributing to make previously minor variations in geometry and technological parameters a big issue for circuit design. Worse still, new mechanisms appear that cause important variations not only in transistors but also in interconnect. And some of those mechanisms, show greater variation across a single die than across similar structures on different dice from a wafer. Thus the chip designer must expect significant and not necessarily predictable differences between transistors and between interconnect resistances on a single die. Given this scenario widely recognised by process engineers, and given the additional spread built-in in the process of mapping from a soft IP design to a hard IP block, if the designer had the opportunity to know certain performance parameters of the final hard-cores without doing successive synthesis it would lead to an easier and more predictable and accurate integration of the blocks in the system. In this sense, pre-characterised trust-worthy soft-IP blocks would be preferred candidates to select. We have explored ways for quantifying and analysing the synthesis to layout spread so that, instead of modelling the spread in devices and interconnects, we model and quantify at a higher abstraction level the technology mapping process as a whole, for a set of seed designs that will give bounds and guidelines for the behaviour of other designs when they are mapped to the same technology. For that purpose, only the best-, typical-, worst-case and other process variation corners need to be known. The analysis is based in the actual measured spread of reference seed designs as they experience spread when passing from soft to hard designs.

Integrated inductors are key components in Radio Frequency Integrated Circuits (RFICs) because they are needed in several building blocks, such as voltage-controlled oscillators (VCOs), low-noise amplifiers (LNAs), mixers, or filters. The cost reduction, achieved in the circuit assemblage, makes them preferable to Surface Mounted Devices in spite of the different sources of lost that limits the use of integrated inductors; there are losses associated with the semiconductor substrate, and losses in the metals. We report, in this work, our research in modeling integrated inductors, particularly the losses in the metals. The model is derived from measurements taken from integrated spiral inductors designed and fabricated in a standard silicon process. The measurements reveal that the widely accepted lumped equivalent model does not properly predict the integrated inductor behavior at frequencies above 3 GHz for our technology. We propose a simple modification in the lumped equivalent circuit model: the introduction of an empirical resistor in the port 1-to-port 2 branch of the equivalent circuit. As a result, it will be demonstrated that the integrated inductor behavior is adequately predicted in a wider frequency range than does the conventional model. We also report a new methodology for characterizing the integrated inductors including the new resistor. In addition, the new model is used to build-up an integrated inductor library containing optimized integrated inductors.

This paper focuses on the mapping of low-cost and real-time super-resolution (SR) algorithms onto SOC (System-On-Chip) platforms in order to achieve high-quality image improvements. Low-cost constraints are accomplished by avoiding the need for specific SR hardware, by re-using a video encoder architecture. Only small modifications are needed for: the motion estimator, the motion compensator, image loop memory, etc. This encoder can be used either in compression mode or in SR mode. This video encoder together with the new SR features constitutes an IP block inside Philips Research, upon which several SOC platforms are being developed. Although this SR algorithm has been implemented on an encoder architecture developed by Philips Research it can be easily mapped upon other hybrid video encoder platforms. The results show important improvements in the image quality. Based on these results, some generalizations can be made about the impact of the sampling process on the quality of the super-resolution image.

This paper describes the work in progress of the European IST-2001-34410 CAMELLIA project, which focuses on a platform-based development of a smart imaging core to be embedded in smart cameras. Therefore the work within the CAMELLIA project comprises the specification and implementation of smart imaging applications including the development of required new algorithms and hardware. Based on an existing video encoding architecture for MPEG-4 Simple Profile, the aim is to design a smart imaging core, which is suitable for automotive and mobile communication applications. Thereby the encoding architecture is to be extended with processing units for low- and mid-level smart imaging functions. To indicate the applicability of this platform-based development, a first approach for a motion estimation based background detection using a hardware motion estimation unit is illustrated in this paper. Furthermore, first results employing the background detection to detect moving objects in video sequences using a functional simulator of a video encoding architecture are presented.

The results of the analysis, from a digital point of view, of some interconnection structures in GaAs integrated circuits are presented. These results are given in graphical format, as engineering charts, to assist designers, and with a polynomial fitting useful for timing analysis. In addition to computing timing parameters such as propagation time and signed slopes (waveforms), the methodology also provides estimations of noise and crosstalk levels. >

A gallium arsenide automated layout generation system (OLYMPO) for VLSI circuits and system design has been developed. Cell, macrocell and module compilers are the basis of the layout automation tool. The cell and macrocell compiler takes a circuit schematic at logic level and outputs a mask layout. The compiler uses a full-custom layout style, called RN-based cell model. The cell compiler can be used as a cell library builder and it is embedded in a random logic macrocell and an iterative logic array generator for module generation. Experimental results for datapath generation (adders, multipliers, FIR filters, register modules, among others) demonstrate that OLYMPO generates complex and compact layouts and the synthesis process can be interactively used at the system design level.