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The modular multilevel converter (MMC) is the most preferred choice for high-voltage direct current (HVdc) applications. In this article, a new hybrid-legs bridge converter (HLBC) is presented as an alternative to the MMC. This converter is a hybrid of a two-level converter and an MMC. For a three-phase system, three single-phase HLBCs are connected either in series [series-connected HLBC (SHLBC)] or in parallel [parallel-connected HLBC (PHLBC)] across the dc-link. Compared to the MMC and the series-connected MMC, the SHLBC requires only one-third and half the submodules (SMs), respectively. Besides, the SHLBC eliminates the requirement of any arm inductor or dc-side filter. The structure and operating principle of the HLBC are described. Moreover, the minimum SM capacitance required to limit its voltage fluctuation is calculated. The dc fault-tolerant capability of the SHLBC and PHLBC is achieved by replacing some of the unipolar SMs with bipolar SMs. The operation, applicability for HVdc systems, ac fault ride through and dc fault-tolerant capability of the proposed converter are verified using PSCAD simulations. Furthermore, the feasibility of the proposed converter under normal and dc fault conditions is revalidated experimentally by using a three-phase grid-connected HLBC laboratory prototype. A comparative analysis is carried out to highlight the benefits of the proposed HLBC over the existing converter topologies.

The active-neutral-point-clamped (ANPC) converter is a prominent topology for medium voltage applications. To realize a high-power-density three-level ANPC converter, silicon carbide (SiC) MOSFETs may be used but they also lead to an extremely high cost. Thus, it is important to properly utilize the SiC switches in order to achieve not only a highly efficient but also a low-cost system. In this article, a three-level enhanced hybrid ANPC (E-HANPC) structure is proposed, which optimally utilizes both Si insulated gate bipolar transistors (IGBTs) and SiC MOSFETs to achieve these objectives. A dedicated modulation scheme is also proposed that enables a reduction in the conduction and switching losses and, hence, higher efficiency is achieved. The presented method optimally distributes the losses amongst the converter switches that leads to enhanced power handling capability of the E-HANPC converter. Moreover, the proposed converter also achieves short-length commutation loops for the high-frequency SiC MOSFETs, which imparts fast-switching capability with reduced overvoltage stress on these switches. To validate the efficacy of the proposed converter and modulation scheme, extensive simulation and analytical studies are performed. A prototype of the single-phase leg of the E-HANPC converter is also developed to validate its feasibility, proposed principles, and reconfirm the simulation and analytical findings.

A compact, efficient and dc fault-tolerant hybrid series converter (HSC) topology is proposed in this article for high-voltage direct current (HVdc) applications. It contains a parallel and a series chain link (CL) per phase. The parallel CL (PCL) supports the dc-link, whereas the series CL (SCL) enables the HSC to have enhanced operating range and dc fault-tolerant capabilities. A new control technique is proposed to control the SCL submodules (SMs) capacitor voltage for its entire operating range. The performance of HSC and its control technique is evaluated using PSCAD/EMTDC for various conditions. The capability of HSC to work in the undermodulation and overmodulation index range and for HVdc system is examined. Furthermore, the response of HSC during pole-to-pole dc fault and ac faults is analyzed to substantiate its dc fault blocking and ac fault ride-through capabilities. The results obtained validate that the HSC exhibits superior performance over the existing ones. The SMs’ capacitor size design methodology in HSC and for other existing topologies is described. The loss calculation of the HSC is carried out to determine its efficiency and is compared with the prominent converter topologies. A three-phase 13-level HSC experimental setup is developed to validate its feasibility and also to reconfirm the simulation outcomes.

Hybrid multilevel converters using bidirectional thyristors and IGBTs have gained significant interest in recent times, as they possess important features of both voltage-source and line-commutated converter technologies. This article presents a classification of hybrid multilevel converters for HVdc applications. The methodologies to derive, evaluate, and select these converter topologies are proposed as well. The hybrid converters are classified from the power device to the system configuration based on the analogy of the voltage-source converter and the current-source converter. Derivation methods of hybrid cell, cluster, arm, phase, and converter, based on the topology tree presented in this article, are applied to derive both existing and new hybrid converters. Comparisons show that hybrid converters have functionality similar to either the modular multilevel converter or the line-commutated converter, depending on the ratio between thyristor and active switch IGBT counts employed. Several hybrid-station configurations are discussed in order to suggest the most suitable converter topology for each configuration. The presented analysis can provide a point of reference and a useful framework for the future developments of hybrid multilevel converters for HVdc applications.

The modular multilevel converter (MMC) is the most preferred voltage source converter high voltage direct current (VSC-HVdc) topology. However, its limitations such as, large energy storage requirements and a large number of devices and capacitors required in its chain-links (CLs), have led to the development of some hybrid multilevel converter topologies. These topologies aim to address the major technical constraints of MMC. The parallel hybrid converter (PHC) is such a hybrid topology, which has evolved as a promising alternative for high power applications because its CLs are not subjected to the fundamental component of ac current and hence the size of its submodule capacitors is substantially lower. Furthermore, for the same power rating, the device count in PHC is only a fraction of that in MMC. However, the PHC suffers from some operational constraints. The dc and ac sides of PHC are strongly coupled, which leads to a single stable operating point resulting in a fixed output voltage if a dedicated controller is not used to tackle this issue. Moreover, the PHC loses control during dc-side faults and it also necessitates a bulky dc filter inductor to filter the dc-side harmonics. Various advanced control methods and derived PHC topologies have been proposed in literature to eradicate these shortcomings of the PHC. This article presents a detailed analysis and review of these state-of-art control strategies and derived PHC topologies. The capability of the PHC and the derived topologies to ride through ac and dc faults are also discussed. This article contributes in summarizing key benefits and limitations of various existing control methods through extensive analyses, simulation, and experimental studies.

The submodule capacitor voltage sensing and balancing is necessary for proper operation of modular multilevel converters (MMC). Voltage controlled oscillator is used for capacitor voltage measurement in the reported literature where voltage sensor is required to be calibrated. In this article, a voltage sensing method that does not need calibration of individual voltage sensors is used for capacitor voltage measurement. Moreover, a simplified sorting algorithm is employed for capacitor voltage balancing. A method of sorting the capacitor voltages that selects the submodules to be inserted directly based on logic equations is used as compared to the conventional methods of arranging them in ascending or descending order. This facilitates to simplifying the sorting technique and the scheme is easy to implement using any controller. Furthermore, to simplify the overall MMC control, the decentralized control arrangement is developed. Fairly good capacitor voltage balancing is obtained. The proposed balancing and sensing schemes of submodule capacitors are validated on a three-phase seven-level MMC hardware prototype with six submodules per arm. The prototype is tested for different operating conditions such as precharging, circulating current control, and grid connected operation of MMC.

Background: Hip surgeries are frequently performed using single shot spinal anesthesia with 15-17.5 mg plain bupivacaine 0.5% which provides surgical anesthesia for 3-4 hours but is difficult to make the patients with hip fractures to lie in lateral decubitus position with the operating side dependent and to make them sit also. Using hypobaric local anesthetic for surgeries around hip, preparation time may be reduced for performing spinal anesthesia and surgery in the same position without waiting for establishment of spinal anesthesia in the supine position. Furthermore, hypobaric local anesthetics can produce more selective block on the operating side and avoid unnecessary paralysis of the nonoperating side potentially resulting in hemodynamic stability and better mobilization of patients during recovery period.Subjects and Methods:In the present study, we compared the anesthetic and hemodynamic effects of hypobaric bupivacaine with and without fentanyl in 100 ASA physical status I and II patients undergoing surgeries around hip. Patients received spinal injection of either 2.5ml (12.5mg) of isobaric bupivacaine with 1.5ml of distilled water (total 4ml) making it hypobaric or 2.5 ml (12.5mg) of isobaric bupivacaine with 1ml of distilled water and 0.5ml(25 µg) of fentanyl (total 4ml) with operative side up, in a double blinded manner. Sensory level and motor block were evaluated on the operative and non-operative sides until regression to L2 and full motor recovery. Hemodynamic changes after spinal injection and the first analgesic request for VAS >3 were noted.Results:Demographic characteristics of both the groups were comparable. Time to maximal fall in MAP and patients requiring vasopressor were similar in both the groups. None of the patients in any of the two group required atropine for bradycardia. Co-administration of fentanyl in hypobaric bupivacaine hastened the onset of sensory block (12±3 vs. 20±9.0, p value

Modular multilevel converter is the most prominent topology for high-voltage dc (HVDC) applications. However, it requires a large number and size of its submodule (SM) capacitors, proportionally large number of semiconductor switches and has high losses. To address some of these issues, the modular directed series multilevel converter (MDSMC) is proposed in this article. It requires significantly reduced size of SM capacitors and lower number of semiconductor switches and capacitors for the same power output. It is a hybrid topology having two main circuit components, namely, the chain-links consisting of a number of series-connected SMs and the director switches realized using a number of series-connected insulated-gate bipolar transistors (IGBTs). A detailed analysis and operating principles of MDSMC are presented to highlight its important features. The control and modulation schemes of MDSMC are presented that enable this converter to be utilized most effectively. The SMs capacitor size calculation is performed and compared with the major HVDC converters to validate its lowest capacitive energy storage requirement. The performance of MDSMC is evaluated using PSCAD/EMTDC for both standalone and HVDC systems under varying system conditions. Its ability to provide wide operating range and four-quadrant operation for HVDC application are also verified. Loss computation validates the ability of MDSMC to provide higher efficiency. A detailed comparison between MDSMC and other major HVDC converters is performed on the basis of their various structural parameters. Furthermore, a three-phase 13-level MDSMC experiment prototype is developed to validate its feasibility, operating principles, and control logic.

Modular multilevel converter containing half-bridge submodules (SMs) is the most preferred topology for high voltage dc (HVDC) applications. However, the inability to block/limit dc fault current and large number of capacitors requirement are some of its limitations. Recently, hybrid topologies utilizing thyristors for such applications have gained significant interest as they offer lower on-state voltage drop, higher reliability, and power handling capability. In this article, the modular embedded thyristor directed converter (METDC) is proposed, which uses series-connected thyristors as the high voltage switches and chain-links comprising of IGBT based half and full-bridge SMs. A control technique is proposed for force-commutation of thyristors by using full-bridge SMs for lagging loads, while they are naturally commutated for leading loads. The METDC offers wide operating range besides being fault tolerant. The results obtained from the METDC-HVDC model developed in PSCAD substantiate its ability to provide independent active and reactive power control required for HVDC application. The fault studies carried out validate the dc fault tolerant capability of METDC. The results obtained from the various ac fault/unbalanced case studies substantiate the efficacy of proposed controller to force-commutate the thyristors even during contingencies. Loss computation validates the ability of converter to provide higher efficiency.

The hybrid-series-converter-(HSC) has enhanced operating modulation-index-(MI) range as compared to the parallel-hybrid-converter-(PHC). However, the HSC is underutilized when employed for high-voltage-direct-current-(HVDC) applications, HSC-HVDC. The parallel-chain-links-(PCLs) of HSC-HVDC generate fixed voltage and the series-chain-links(SCLs) of HSC-HVDC serves only as voltage wave-shaping circuit and does not increasing the output voltage levels. Thus, energy storage requirement of HSC-HVDC is higher than PHC. The switches of HSC-HVDC undergo forced commutation and increase losses. This paper intends to extract all the advantages inherent with the HSC and utilize it to its maximum capability by operating it as a static-compensator-(STATCOM), HSCSTATCOM. The proposed HSC-STATCOM requires lesser switching devices, capacitors besides having reduced energy storage requirements and zero-voltage-switching-(ZVS) nature. A new capacitor voltage control technique during unbalanced grid conditions is also proposed in this paper. The operating principle of the proposed STATCOM and proposed control technique is validated using different simulation case studies.

The state-of-the-art power electronic converters demand for the switches with high switching frequency capability at low losses. The gate driver circuit plays an important role in driving such high frequency switches. In such applications, the losses in the gate driver is one of the major concerns. In such scenarios, current source gate-drivers (CSD) are preferred over the conventional drivers due to reduced losses and energy recovery capability. This paper focuses on the optimal deign and selection of inductor for the CSD in order to effectively drive the power MOSFET leading to reduced switching and conduction losses, along with the reduction of crosstalk effect due to high frequency operation. The switching performance and characteristics of the high frequency switching SiC MOSFET is obtained by performing the double pulse test (DPT) with different inductor values. From the obtained curves, the optimum value of the inductor is suggested. The prototype of the CSD is also constructed for the experimental verification

A new delta hybrid series converter-(DHSC) is proposed to compensate reactive power in the transmission lines operating at medium and high voltage ranges. The proposed DHSC converter has unique advantages over the existing modular-multilevel-converters-(MMCs) based static-compensators(STATCOMs) such as DSCC and DSBC in terms of number of capacitors and energy storage requirements. The series chain-links(SCLs) of the proposed DHSC contributes in increasing the output voltage levels unlike the hybrid-series-converter-(HSC) and hence has less number of switches and capacitors. The DHSC converter has zero-voltage-switching-(ZVS) nature and has reduced switching losses than the HSC. The proposed DHSC accommodates zero-sequence currents in its individual phases and hence has an extra degree of freedom to regulate its capacitor voltages even during unbalanced grid conditions. A capacitor voltage control technique is also proposed using the zero-sequence current. The working of the proposed DHSC STATCOM and proposed capacitor voltage control is verified using simulation results.

DC microgrids have been gaining popularity over the past few decades. Most proposed works do not factor in the variabilities associated with the renewable power generation. The present work is aimed at validating a bus voltage signal method based strategy for a photovoltaic (PV) based DC microgrid system that is able to sustain load under both grid connected and islanded modes and ensures smooth mode transition factoring in the renewable intermittency. A power-based droop control technique is employed to determine the operating mode of the distributed energy resource (DER) converter. A battery energy storage system (BESS) interfaced through a bi-directional converter ensures that the PV panel operates at its maximum power point (MPP) at all loading conditions in both the modes. A total of eight possible scenarios in terms of load conditions, solar insolation variation and output power set-points are modelled and simulated in MATLAB Simulink environment and verified in real-time through controller-hardware-in-loop (CHIL) on an Opal-RT platform results are presented and discussed.

Recently, Silicon (Si) and Silicon-carbide (SiC) based hybrid active neutral-point-clamped (ANPC) topologies have gained significant interests owing to their high efficiency to cost ratio. Among these hybrid ANPCs, the enhanced-hybrid-ANPC (E-HANPC) minimizes the commutation issues of SiC switches and offers high efficiency. In this paper, a carrier-based space-vector-modulation (SVM) scheme is proposed for EHANPC topology. The proposed SVM scheme reduces converter switching losses using SiC MOSFETs, while conduction losses are reduced by operating Si IGBTs in parallel conduction paths. Moreover, with the proposed SVM scheme, Si IGBTs are switched at either zero or reduced current value. In this way, the overall converter losses are reduced with the proposed SVM scheme. This paper presents detailed derivation of proposed scheme. Moreover, converter loss analysis and selection criterion for Si IGBTs to achieve maximum loss reduction are presented. The performance of proposed scheme is validated with the simulation and experimental results using reduced-scale three-phase experimental prototype.

The alternate arm converter (AAC) is being considered as a potential alternative for MMC in HVDC applications because of lower energy storage requirement and dc-fault tolerant capability. However, to achieve energy balancing over wide range of operating modulation indices, it requires a dedicated controller that needs to exchange the unbalanced energies between the upper and lower arms of each phase-leg to achieve the balancing of its SMs capacitor voltages. In this paper, a new control scheme is proposed for AAC to balance its SMs capacitor voltages. The proposed scheme is based on the constant overlap-time and the magnitude of current during overlap-time is varied depending on the operating modulation index and power-factor. As the overlap-time is kept constant in the proposed control scheme, the operation of AAC can be extended to higher modulation range without increasing the number of SMs per arm. A detailed analysis of arm energy in AAC is presented to determine the required magnitude of current to be injected during the overlap for energy balancing. The efficacy of the analysis and the control scheme is verified using simulation and experimental studies on a scaled down laboratory prototype.

Multilevel converters are popular choice for high-power applications to achieve high-power density and efficiency. This paper presents a seven-level hybrid fault tolerant converter (HFTC), with two identical sub-modules. The proposed HFTC is comprised of a combination of Si/SiC devices, where Si IGBTs are operated at fundamental frequency, while SiC MOSFETs are switched at high switching frequency to achieve reduced losses. In addition to the reduction in converter losses, SiC MOSFETs in the HFTC provide a fault tolerant operation with fast isolation or bypass capability to have minimum effect on the converter operation. Furthermore, the HFTC can isolate ac and dc side faults without the need of external circuit in addition to providing the elimination of leakage current, making it a prominent choice for transformerless grid connected converter for PV systems. In this paper, analytical and simulation studies are presented with the experimental validation to demonstrate the converter features.

Modular multilevel converter (MMC) is the most preferred topology for high voltage dc (HVDC) transmission. The circulating current (CC) in MMC is a natural phenomenon, which is conventionally suppressed to enhance efficiency. Nonetheless, proper control of circulating current in MMC can help in reducing the peak value of arm current and/or size of the SMs capacitor. However, minimizing SMs capacitor size using the CC control leads to an increase in the peak and rms values of the arm current. Similarly, minimizing the peak and rms values of the arm current using CC control can lead to an increased SMs capacitor size. In this paper, an optimized circulating current injection control scheme is proposed to reduce the peak value of arm current while keeping the size of SMs capacitor the same. A generalized expression of the magnitude of circulating current to be injected is derived. Using this expression, a comparative analysis is presented to show the merits of the proposed control scheme over the existing schemes. Two circulating current controllers that can be used to control the second harmonic circulating current to have magnitude and phase-angle as per the derived expressions are discussed. The efficacy of the proposed scheme is verified using a 9-level grid-connected simulation model developed in PSCAD/EMTDC. The principles are further verified using a 7-level grid-connected scaled-down lab prototype.

This report covers the research work being carried out under the Visvesvaraya PhD Scheme for Electronics & IT.

The silicon carbide (SiC) devices are getting popular due to their numerous advantages for the modern power electronic applications. Further, in order to cater the limitation of the high cost of these devices and to enhance their application demand, the topologies with hybrid utilization of the Si and SiC devices are proposed in the literature. In such topologies, the device losses are distributed unevenly which plays a vital role in converter operation. In this paper, such Si and SiC based hybrid topologies are analyzed for the converter operating conditions such as junction temperatures and device losses. The paper initially considers the conventional thermal model and evaluates the effect of uneven distribution of losses on their junction temperatures. Then, the actual heat sink model is simulated using the FEM simulations to verify the conventional thermal model. Based on these results, the issues in application of the conventional thermal model for the converter design of the topologies with uneven loss distribution are identified and the modified analytical approach is proposed. Moreover, a detailed procedure for accurate determination of the converter operating conditions using the parameters of the designed experimental prototypes for the considered topologies is presented. Finally, the results are given to compare the difference between the conventional and proposed approach for the considered topologies.

Recently introduced Silicon carbide (SiC) devices have significantly improved the performance of the power electronic converters. These devices are able to provide higher power density with high efficiency compared to the Silicon (Si) devices. In this paper, the topology based on Si IGBTs and SiC MOSFETs is proposed to achieve high efficiency with reduced cost. The proposed converter achieves zero current switching of Si IGBTs for all power factor values using the selected switching states in the proposed modulation scheme. Therefore, high efficiency can be obtained even at high switching frequency operation for wide range of operating conditions. Additionally, the utilization of the SiC MOSFETs further reduces the switching losses. Moreover, the conduction losses of the SiC MOSFETs are minimized by strategically selecting the switching states in such a way that SiC MOSFETs conduct in parallel conduction paths during the null state operation. This paper presents the detailed operating principle of the proposed topology using the presented modulation scheme. Further, a switching loss analysis is presented to evaluate the conduction and switching losses of the proposed topology. Moreover, the experimental results are presented to demonstrate the basic operating principle of the proposed topology. Finally, the efficiency values of the proposed topology are compared with the existing topologies for different operating conductions.

Electric vehicles (EV) can act as distributed energy storage and provide ancillary services to the grid. For this purpose, a high-efficiency operation of the interfacing converter is desired over the entire power and voltage range. In this paper, firstly, a design procedure is outlined for the dual active bridge (DAB) stage of an on-board EV charger considering the prevalent charging standards and the ratings of the EVs. Thereafter, a comparison of three modulation techniques (single phase shift, dual phase shift and extended phase shift modulation) as applied to the DAB stage has been performed. The comparison study demonstrated that these techniques perform differently in various zones of operation. It is further shown that an overall gain in efficiency can be attained by changing between the modulation techniques depending on the operating point of the converter. Finally, based on these observations, the suitability of these techniques for different power-based and energy-based ancillary services has been discussed.

The series connected converters (SCCs) are popular for high voltage direct current (HVDC) applications like off-shore, city infeed and current taping. However, most of the SCCs suffer from dc voltage and current harmonics, which necessitates bulky filters. A new control technique is proposed in this paper to eliminate the dc side harmonics in the SCCs. The proposed method can be used in any SCC containing two chain links (CLs) per phase such as series bridge converter (SBC) and hybrid cascaded converter (HCC). Also, a new parallel series hybrid converter (PSHC) is proposed, which does not suffer from any dc side harmonics and is tolerant to dc side faults. To control the energy exchanged amongst the CLs in PSHC, a modified control technique is proposed. The ability of the proposed control technique to eliminate the dc side harmonics in PSHC are verified using various three-phase simulation and experimental models.

The parallel hybrid converter (PHC) is gaining popularity for high voltage direct current applications. The chain-links (CLs) in the PHC bear only a fraction of the output phase current and exhibit double frequency nature. This reduces the energy storage requirement and the losses occurring in the CLs of the PHC. The PHC converter also requires lower number of sub-modules (SMs) and switching devices. The existing PHC configuration requires harmonic voltage injection in the CLs to feed the ac grid, thereby injecting harmonic currents into the main DC-link and it is not dc fault-tolerant. A new front-front dc-dc hybrid configuration for high voltage transmission systems using PHC is presented, which eliminates the need for harmonic voltage injection. The proposed dc-dc configuration is dc fault-tolerant and requires reduced SM capacitors size and smaller interlinking transformers owing to high-frequency switching operation. The authenticity of the proposed dc-dc converter is verified by caring out various simulation and hardware studies.

The multi-terminal high voltage dc (HVdc) networks require isolated dc-dc converters for voltage matching, power flow control and fault protection. The dc-dc converters based on modular multilevel converter (MMC) are continuously gaining popularity. The trapezoidal modulation method in dc-dc converters provides controlled dv/dt stress, high dc voltage utilization and power transfer capability. The simulation based models are gaining interest in recent literature. However, more focus is required on the mathematical modeling aspect of these converters. This paper presents an averaged dynamic model of MMC working in the trapezoidal modulation. The developed model effectively captures both ac and dc side dynamics along with the internal dynamics of sub-module capacitors. The presented average model provides a simplified method of analyzing large converter system. The comparison between simulation and analytical model validates the performance of the developed model. A laboratory prototype is also developed to observe MMC operation in the trapezoidal modulation scheme.

The objective of this research is to design a model for predicting diesel fuel parameters from the data obtained from near infrared spectroscopic analysis of the fuel. Due to the complexity and the sheer number of peaks obtained in the spectral data, only those wavelengths that have a significant impact on the parameters are filtered out. Four types of variable selection techniques (LASSO, correlation coefficient, Mallow's Cp criterion, Relative sensitivity ratio) were applied on the NIR spectra data. Following variable selection, two models based on ridge regression and regression tree were developed. The models were used to successfully predict six diesel fuel parameters: cetane number, boiling point, freezing point, total aromatic content, viscosity and density from NIR spectra data. Variable selection by LASSO followed by regression tree modelling produced the best prediction accuracy

An H-bridge hybrid modular converter (HBHMC) is proposed for high-voltage direct current (HVDC) applications. It uses a wave-shaping circuit consisting of series-connected full-bridge submodules (FBSMs) at the output of the main H-bridge converter. For a three-phase system, three HBHMCs are connected either in series (series-HBHMC) or in parallel (parallel-HBHMC) across the dc-link. The operating modes of HBHMC, novel modulation strategies for voltage balancing of FBSMs, and control of HBHMC-based HVDC system are presented in this paper. A detailed comparison between HBHMC and other hybrid topologies is performed on the basis of required number of switches and capacitors. The HBHMC has the features of dc fault blocking capability, lower footprint structure, and extra degree of freedom for submodules capacitor voltage balancing. The efficacy of the HBHMC-based HVDC system for three-phase balanced and unbalanced grid conditions and its fault-tolerant capability are validated using PSCAD simulation studies. Furthermore, the feasibility of the proposed converter under normal and dc fault conditions and of the proposed capacitor voltage control scheme is validated experimentally by using a three-phase grid-connected HBHMC laboratory prototype. The results demonstrate the effectiveness of the proposed HBHMC topology, control techniques, and satisfactory responses of the HBHMC-based HVDC system.

The hybrid modular multilevel converter with cascaded full bridges (HMMC-CFB) is a recently proposed dc fault tolerant converter topology for high-power applications. It has a director part (DP) consisting of a series of connected half-bridge submodules, and a wave-shaping part (WSP) composed of a series of connected full-bridge submodules (FBSMs). The submodules in DP avoid high voltage stresses and improve synchronization between DP and WSP by slowing down the change rate of DP output voltage. This slowdown is achieved by using a trapezoidal reference signal for DP. The WSP attenuates the voltage harmonics produced by DP. However, the energy exchanged by WSP changes with modulation index, which may cause improper voltage regulation of the submodule capacitors. This paper proposes a new control technique to regulate the energy exchanged by WSP, which uses a variable slope trapezoidal reference signal of DP. To obtain this slope, the feedforward and feedback controllers are used. The feedforward controller gives the value of slope depending on the modulation index (m(v)) to keep the energy exchanged by WSP nearly equal to zero, whereas the losses and nonideality of the converter are taken care of by the feedback controller. This technique guarantees proper voltage regulation of the submodule capacitors for all modulation indices. The efficacy of the proposed technique is confirmed using simulations and experimentations. This paper also presents a circulating current suppressing controller for HMMC-CFB. The proposed control schemes and dc fault tolerant capability of HMMC-CFB are tested on a grid-connected model built in PSCAD.

A modular multilevel converter (MMC) is one of the latest multilevel converters used for high and medium-voltage power conversion. It is based on cascade connection of multiple identical modules using IGBTs as switching devices. Module switches of MMC are preferably driven by a source derived from the module capacitor. In each MMC module, the control circuit, consisting of gate drivers, is powered from a dc supply derived from the local capacitor. The module capacitors need to be pre-charged, to power the control circuit. The problem faced while doing so experimentally for MMC with two modules per arm and a solution have been reported earlier. If a fly-back converter is used to generate the power supply for driving the control circuit, the module capacitor voltages become unstable during uncontrolled pre-charging. It has been reported earlier that the reason for this is approximately constant power load on the module capacitor. This work provides theoretical understanding of the problem and shows by analysis that the power supply can be made stable if the load on the module capacitor is made a positive resistance load. As the complexity of MMC with more than two modules per arm is higher, the phenomenon is studied by simulation for MMC with four modules per arm. It shows that when a fly-back converter is used for generating the power supply, similar instability occurs in MMC with four modules per arm. It shows that when the module capacitor is made to have a load with positive resistance characteristics, the module capacitor voltages and consequently the power supplies stabilize even for MMC with four modules per arm. It further shows that even if the load on the module capacitor is negative resistance type, when fly-back converter is used to generate the module power supply, by switching devices in those modules where power supply becomes available first, followed by sorting algorithm, stable power supplies can be developed on all the modules and the capacitors can be fully charged to the desired voltage.

The parallel hybrid modular multilevel converter (PHMMC) is gaining more popularity for HVDC applications due to lower losses and requirement of small sub-module (SM) capacitor. However, PHMMC suffers from fixed modulation index (MI), large dc side voltage ripples and inability to act against dc faults. A novel hybrid phase converter (HPC) topology is presented in this paper to eliminate the aforementioned limitations of PHMMC. The proposed HPC not only has wide MI range but is also tolerant to dc faults. The dc side voltage ripples of the HPC can be minimized by using the proposed modified control method, which excludes the requirement of dc inductor. A new control method is also proposed to maintain the SMs capacitor voltage. DC fault analysis is also carried out to substantiate the fault blocking capability of HPC. Component level models are developed in PSCAD to validate the working of the proposed HPC and its controller. SM capacitor size is determined analytically, which proves that the HPC requires lower capacitive energy storage per unit apparent power and consequently has lower footprint.

The photovoltaic (PV) power electronic converter using silicon devices is a matured technology, which targets for high efficiency, high power density, and reduced volume. However, recently introduced SiC devices have raised the benchmark due to their distinguished features like high thermal conductivity, wider band-gap which helps to block the higher voltages with the reduced drift layer enabling faster switching operation. In this paper, the effect of the high-frequency operation on the performance of a three-level hybrid Si/SiC based converter is discussed. The parasitic components due to the addition of external antiparallel diode are analyzed and performance is compared with the one without external diode for different load current and power factors. This enables the decision on the selection of antiparallel diode for the required operating condition in SiC-based converter. This work also gives an idea on the use of discrete SiC switches for a converter configuration involving hybrid devices.

The Parallel Hybrid MMC (PH-MMC) is characterized by a fixed modulation index (MI). The MI can be varied by injecting a third harmonic voltage component to the chain-links (CLs), which increases the voltage and current ratings of the converter. Moreover, the range of MI obtained with third harmonic injection method (THIM) is limited. This paper analyses the reactive power injection capability of the PH-MMC during balanced and unbalanced loading conditions. The PH-MMC as static compensator (STATCOM) provides wide MI range without any requirement of THIM. During unbalanced loading conditions, the sum of the capacitor voltages of the CLs tends to diverge from its reference value owing to unequal exchange of power by each CL with the grid. An expression for negative sequence current is derived, which regulates the capacitor voltages by redistributing cluster powers within CLs. The proposed analyses are substantiated using the developed models in PSCAD. Results obtained prove the excellent performance of PH-MMC-STATCOM.

The Modular multilevel converter (MMC) is the most popular suited topology for high voltage dc (HVDC) transmission applications. The circulating current in MMC is majorly, in addition to the dc current, second harmonic in nature. To enhance the efficiency of the converter, the circulating current in an MMC is required to be suppressed. Many control methods are proposed in the literature to suppress the second harmonic current, which are mainly based on sensing and calculating the second harmonic circulating current (SHCC) and then suppressing it. In this paper, a circulating current elimination controller is proposed to suppress the SHCC which is based on instantaneous voltage of the sub-modules capacitor voltage. Hence, the sensing and communicating the sensed signal of arm currents can be avoided, which increases the reliability and decreases the overall cost of the system. The efficacy of the proposed controller is verified using the simulation studies in PSCAD/EMTDC and also by using scaled-down lab prototype.

The neutral point clamped (NPC) converter and the modular multilevel converter (MMC) are among the most popular multilevel converter topologies for medium and high voltage applications. Conventionally, Silicon (Si) switches are used in these converters, but the usage of evolving Silicon Carbide (SiC) switches can enhance their performance. This paper investigates the impact of SiC switches on the performance of the three-level MMC and NPC converter for the medium voltage (MV) Photovoltaic system. The detailed analysis of loss distribution in the switching devices and the impact of SiC switch on the achievable converter rating is given. The obtained results for conduction and switching losses are compared for both the converters. Finally, from the obtained results, conclusions are made for the selection of devices and the converter for a given rating. The analysis is done by first obtaining the device parameters using the simulation of detailed device models using the circuit simulator and then using them to get the equations for the device losses. These equations are then incorporated into the system level simulations of both of the converters to evaluate losses.

Research in solar photovoltaics over the past decade has resulted in significant improvement of the PV array efficiency. To further improve efficiency, transformerless PV inverter topologies are developed and are successfully employed in single phase PV systems. However, as the output power of solar PV becomes more than 15 kW it is recommended to use three phase converters instead of single phase owing to the size of the DC link capacitor and its lifetime. Due to the lack of galvanic isolation in case of transformerless inverter, the parasitic capacitance between the PV surface and grid ground faces varying common mode voltage across it. This results in the flow of common mode leakage current and compromises overall safety of the inverter. This paper discusses some of the prominent three phase grid connected transformer-less Voltage source inverters (VSI) for solar photovoltaic (PV) application. Various topological modifications and control strategies proposed in literature to minimize the ground current or the common mode current are presented.

A three-winding transformer based asymmetrical dual active bridge (TWT-ADAB) isolated dc-dc converter is proposed in this study. The converter comprises of three stages: primary, isolation, and secondary. The primary stage consists of an H-bridge converter, the isolation stage consists of a three-winding transformer with one primary and two secondary windings, and the secondary stage consists of a bridge converter having three legs and six active switches. The load current is shared equally by the secondary windings of the transformer resulting in reduced currents through switches of the secondary converter. Therefore, the turn-off losses of these switches get reduced. Further, zero voltage switching turn-on can be achieved for all switches of the TWT-ADAB converter to reduce the switching losses. A detailed analysis of the modelling and control of the proposed TWT-ADAB converter is presented. The theoretical analysis is verified using the simulation and experimental results. These demonstrated results show that the proposed TWT-ADAB converter offers wider ranges of the output voltages and powers and higher efficiency as compared with the existing dual bridge isolated dc-dc converters. Therefore, it can be an eminent structure for high-power isolated dc-dc power conversion applications.

The fault-tolerant multilevel converters are gaining increased interests for high-voltage direct current (HVDC) applications due to their ability to suppress the fault current during dc-side faults. However, most of these topologies use full-bridge submodules (FBSMs) resulting in the requirement of a large number of semiconductor switches. In this paper, a new generalized cross-connected SM (GX-SM) structure is presented, which requires lesser number of switching devices and provides the same functionality as the FBSM. A comparison of the switches required in the different converter topologies using FBSMs and GX-SMs is performed. The performance evaluation of two of the dc-side fault-tolerant converter topologies, namely alternate arm modular multilevel converter (AAMMC) and hybrid cascaded modular multilevel converter (HCMC) with the GX-SM, is performed using simulation studies done in PSCAD/EMTDC. The modulation and control schemes for these GX-SMs-based converters are presented. A new mixed-SM configuration of AAMMC is proposed which utilizes an optimal combination of GX-SMs and half-bridge SMs. The study results demonstrate the effectiveness of the proposed GX-SM structure, and satisfactory responses of the GX-SMs-based AAMMC and HCMC systems controlled using the presented modulation and control strategies under various system conditions.

Multilevel current source converters are a smart choice for the high-power applications with low-voltage and high-current requirements. This paper presents the detailed analysis of a current source modular multilevel converter (CSMMC) and its application as a STATCOM. Various properties of CSMMC are compared with the voltage-source modular multilevel converter (VSMMC). The submodule inductance selection method and a sorting-based algorithm for inductor current balancing are proposed for CSMMC. The validity of the inductance selection method and the inductor current balancing algorithm are confirmed by the simulation of a three-phase CSMMC using PSCAD/EMTDC. The carrier phase-shifted sinusoidal pulsewidth modulation is used as the switching technique. The performance of a converter is analyzed with interleaved and noninterleaved carrier signals for the upper and lower arms. Results show that CSMMCs and corresponding VSMMCs have analogous features. Hence, the development on VSMMCs can be used for reference to CSMMCs and vice-versa. Furthermore, the control designs for CSMMC-based STATCOM are presented and verified using simulations. The obtained results of the proposed STATCOM show that the steady-state and transient performance of the system are quite satisfactory. This makes the CSMMC suitable for HVDC and flexible ac transmission systems applications.

The use of medium frequency allows the transformer size to be reduced at the higher power level. Reduction in size of the transformer leads to a reduction in installation area which is of prime concern in many renewable energy resources. But the reduction in size at higher power level comes with the cost of higher loss density and lower thermal stability. Therefore, this paper deals with the various constraints and considerations that are required to be taken care of while designing the medium frequency high power transformer (MFHPT). This paper also provides the optimal design of transformer w.r.t. frequency and power. For analysis and comparison purpose, both core and shell type design is developed in Ansys Maxwell (Ver. 16) for 3 MVA transformers at 1000 Hz of frequency using nanocrystalline core material.

Modular multilevel converter (MMC) based high voltage direct current (HVDC) systems are quite popular in high power transmission systems as it offers low losses, high quality output voltage, modular and scalable structure as compared to the two level voltage source converter based HVDC systems. However, inability to block dc fault current is a major concern of conventional MMC-HVDC system, especially for the overhead HVDC system. In this paper, the performance of conventional MMC with half bridge submodules is analyzed for dc side fault. In the event of a dc side fault, the conventional MMC acts as an uncontrolled diode rectifier and feeds very high current to dc fault. To tackle this problem, different techniques have been discussed in the literature. This paper gives a brief overview of dc fault tolerant techniques discussed in the literature. Moreover, in this paper, a detailed comparison between different hybrid topologies with dc fault tolerant capability is performed on the basis of required number of switches and capacitors. Furthermore, the fault tolerant capability of MMC with bipolar (full bridge) submodule is experimentally validated.

Modular multilevel converter (MMC) has gained a huge research interest for high voltage direct current (HVDC) applications. Recently significant research has been carried out to develop hybrid MMC to address the technical constraints of the MMC. Parallel hybrid converter (PHC) is the most promising topology for high power applications due to its series connected chain-links on dc side and smaller sub-module capacitors. Moreover in PHC, the chain-link SMs are not in the main conduction path and the H-bridges are switched at fundamental frequency, which leads to lower semiconductor losses. However, the dc and ac side of the PHC are strongly coupled which lead to a fixed output voltage without using a dedicated control to tackle this issue. Moreover, PHC loses controls during dc fault. Various methods have been proposed in literature to decouple the dc and ac side of the converter and to make it tolerant to dc fault. In this paper, a review of these state of art control strategies are presented. This paper contributes in summarizing key benefits and limitations of various existing control methods through extensive analyses and simulation studies.

The Modular Multilevel Converter (MMC) has modular and redundant structure, which makes it more reliable during certain fault conditions. Hence MMC technology has received considerable attention among various topologies for interconnecting High Voltage Direct Current (HVDC) grid. Existing literature has devoted limited focus on the behavior of the MMC during internal fault condition. This paper presents the switching as well as approximate voltage source model of MMC with analysis of its internal fault current behavior. It also presents an analytical approach for calculating harmonic components in arm current. The simulation studies with both MMC models rated at 161 kV, 625 MVA are performed using MATLAB/Simulink. For this study the power transfer is controlled by changing modulation signal. Presented results emphasize on understanding fault current behavior for various internal faults in MMC.

Modular multilevel converter (MMC) has become the most prominent topology for high voltage direct current (HVDC) applications due to its modularity, lower losses, less filtering requirements and flexible controllability. However, MMC still lacks in terms of efficiency and fault tolerant capability compared to the line commutated converters (LCC) based HVDC systems. This paper proposes a thyristor bypassed fault tolerant half bridge submodule (TBFT-HBSM) for MMC to achieve high efficiency as that in LCC while retaining DC fault tolerant capability and controllability. The lower switch of conventional HBSMs is replaced by anti-parallel thyristor switches to reduce the overall conduction losses of the converter. A new control algorithm has been proposed to balance the arm voltages. Moreover, loss analysis of proposed submodule (SM) is carried out and its efficiency compared with existing SM topologies. Simulation as well as experimental studies are carried out to verify the effectiveness of the proposed SM structure and its control.