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International audience; We compare in this work, the electrical properties of gate leakage currents induced through the thin SiO2 oxide layer of metal-oxide-semiconductor structures by high energy ion implantation and high field stresses. Even if the high-frequency capacitance-voltage characteristics are very different after both treatments, a comparable increase and similar shapes are found at low fields in static gate current–voltage curves, typical of equivalent oxide damage. Moreover, these stress or implantation induced leakage currents (SILC or IILC, respectively) are both removed in a similar way by a thermal anneal under forming gas at 430°C. We conclude that similar defects could be induced through the oxide by both processes and generate those excess currents by a defect assisted tunneling mechanism.

International audience; The hot-carrier reliability of a 0.25μm CMOS technology with a 5nm-thick gate-oxide is studied from low (−40°C) to high temperature (125°C). Channel hot-carriers are investigated using DC and AC experiments on single transistors and on ring oscillators. Turn-around effects are observed in the degradation of the ring oscillator frequency at short times when P-MOSFET's degradation totally compensate the N-MOSFET's current reduction. As the electron trapping becomes much less efficient in thin gate-oxide P-MOSFET's with respect to field enhanced detrapping, the influence of the generated interface traps dominates leading to a cumulative current reduction in both device types at long stress time which results in a reduction of the oscillator frequency. The degradation behavior of the oscillator frequency exhibits a clear dependence on the P-MOSFET channel-width and on temperature as negative bias temperature instability occurs at 125°C during the high state in P-MOSFET's and the field-assisted discharge of electron traps occurs at −40°C.

International audience; AC stressing is investigated to determine the hot-carrier reliability in a 0.5 μm CMOS technology and is interpreted by a quasi-static model based on distinct damage mechanisms. The hot-carrier dependence of n-MOSFETs operating in pass-transistor configurations is carefully studied as a function of the propagation time and geometry. It is shown that device degradation may exhibit in some cases a strong dependence on the propagation time and clearly differs from the simple case of inverter operation.

International audience; Stress Induced Leakage Currents (SILC) are studied in 5 nm-thick oxides on both capacitors and N-MOSFET's after homogeneous FOWLER-NORDHEIM injections under high field stress (

We present a multi techno trend of HCI time acceleration and VD power law exponent for various processes. We review the results of defect localization analysis based on a rigorous correlation and interaction study for different HCI degradation modes and BTI. Finally, we check HCI impact on TDDB to get an accurate comprehension about defect nature. Hence, we point out the necessity of new appropriate reliability modeling specially for recent ultra-short channel technologies.

Gate oxide breakdown is an important reliability issue. This mechanism is widely investigated at device level but the development of a compact model and the assessment at circuit level is much more complex to handle. We first characterize soft and hard breakdown. Then a transistor-level model is presented. The model is calibrated for a large range of breakdown severity. Finally the model is used at circuit level. The impact of breakdown on both static current and ring oscillator frequency is discussed.

We present new reliability features related to the use of a wide range of bulk back biasing in advanced UTBB FDSOI devices. NBTI and HCI stresses were done addressing degradation dependencies vs. bulk bias with the help of TCAD simulations in order to validate our new proposed NBTI physical model in UTBB FDSOI CMOS node.

Hot Carrier induced degradation is modeled using the carrier energy distribution function including Carrier-Carrier Scattering process. Silicon-hydrogen bond breaking through single particle and multiple particles interactions is considered in the modeling of the microscopic defect creation along the channel length. The model is applied to short channel devices and confronted to Monte Carlo simulations including Electron Electrons Scattering, showing a small contribution of EES over the whole damage, mainly dominated by multiple carrier interactions.

This paper introduces for the first time a new test structure for electromigration which allows increased statistics and reliability tests in a testchip under typical High Temperature Operating Life experimental ranges. Following the electrical analysis, a large panel of failure analysis methodologies was suitably used to categorize defects such as size, location, resistance impact, etc. This thorough analysis allows us to confirm that silicon failures are accurately predicted by our electromigration checker, based on reliability design rules.

High-K Metal-Gate 28nm node (C28) with equivalent gate-oxide thickness EOT= 1.35nm has been compared to low power 40nm CMOS node (1.7nm) on silicon bulk. Hot-Carrier damage in C28 originates from the same permanent ΔNIT mechanism under current driven Multiple Particle (MP) interactions, relative to the SiON interface layer while border to bulk oxide traps make the larger difference between NMOS and PMOS transistors. This has been obtained by their respective temperature activation and AC response behaviors at Room Temperature and High Temperature due to the distinct proportion of accessible shallow/deep defects in the HK-MG structures.

International audience; This paper presents a theoretical framework about interface states creation rate from SiAH bond breaking at the Si/SiO2 interface during Hot Carrier (HC) stress. It involves two mains mechanisms of bond breaking through incident carriers, either being very energetic or very numerous but less energetic. This concept allows physical modeling of the reliability of MOS transistors, for different HC stress conditions. Simulation is validated by measurement of both defect lateral profiles and degradation of MOS parameters. This poses a general framework for the study of HC degradation at defect level

International audience; The hot-carrier reliability in p+ poly-gate p-MOSFET's with pure and nitrided 8nm thick gate-oxide is investigated under uniform and localized electron injections. The effects of bidirectionally DC-(AC) stressing on the saturated (linear) - mode transistor parameters are monitored as they represent the worst limitating factor in pass transistors for digital logic applications. With a proper RTA condition and nitridation ambient, it is found that the gate-oxide process obtained by low-pressure plasma nitridation shows better hot-carrier immunity than pure oxide with a significant reduction of charge trapping.

A new methodology of defect characterization, through combination of measurements and simulations, is used to monitor the defect creation rate leading to gate-oxide breakdown. Two defect time-power creation rates were extracted, thus modifying the classical understanding of Weibull slope variation with oxide thickness. Based on our methodology, an explanation of the gate current increase prior to hard BD is proposed.

Based on simulation results, we show that defects at the Si/Box interface of FDSOI transistors can have a detrimental impact on reliability. In particular, attention is paid to Hot Carriers degradations (HC) on ultra thin film FDSOI NMOSFETs for which defects can be created very close to the back gate interface. A new technique based on capacitance measurements is proposed to localize HC degradation at front gate and/or back gate interface on FDSOI transistors. Thanks to this method, it is shown that, similarly to bulk technologies, only the front gate interface is degraded during a classical HC stress. Finally, despite the presence of an additional Si/BOx interface, FDSOI NMOSFETs down to 30nm gate length exhibit HC lifetimes over 10 years, even when a back bias is applied.

The persistence of hot-carrier degradation down to low voltages is analyzed in recent CMOS nodes through the effect of multivibration excitation (MVE) of the Si-H bonds and deexcitation by multiphonon emission. This new mechanism is described by an energy framework and originates from the channel current density independently of voltage and geometry. MVE mode is enhanced with temperature in NMOS and PMOS devices due to its strong coupling to the lattice disregarding the negative bias contribution in PMOS.

Microscopic characterization of interface defects along the channel length is used to monitor the HC induced defect generation. The modeling of HC degradation is adapted to a microscopic scale and is found to be consistent with obtained lateral profiles.

Microscopic characterization of defects into the depth of the gate oxide is used to compare defects generated during both Hot-Carrier Stress (HCS) and Fowler-Nordheim Stress (FNS). Measured defects are linked to the breakdown (BD) process and there creation rate is modeled.

As CMOS technology continues to downscale to a deep submicron level (40 nm and beyond), Soft Oxide Breakdown (SBD) is becoming a real problem that could lead to a serious degradation in the performances and the functional operations of SoC. In this paper we study the SBD, using two models, and quantify its impact on the functionality of a 40 nm SRAM memory.

PBTI in La-doped HfSiON/TiN stacks is investigated using Ultra Fast IV measurements. Excellent PBTI lifetime of these oxides is demonstrated. We also show that PBTI is explained only by trapping in stress induced defects and not by trapping in pre-existing ones. Dependence on oxide field, temperature activation and recovery of PBTI are also investigated and modeled.

Degradation modeling is based usually on macroscopic parameters which can yield to wrong conclusions, since similar degradation might result from very different microscopic situations. The focus on degradation modeling at a microscopic level is proposed. Other authors only compare results from different characterization methods on their common measurement area. This paper proposes to use their complementarities to extend the probed areas. A more accurate determination of defects is obtained with multiple characterization method cross-fertilization allowing 1) ascertaining defect localizations, 2) extending probed areas and 3) identifying microscopic differences between similar macroscopic parameters. The tested devices are NMOS transistors with a 5 nm SiO2 gate oxide and with various gate geometries.

Hot-Carrier degradation is analyzed with 3 mode lifetime modeling extended to the cases of PMOSFETs and Off state modes in last CMOS nodes. Damage worsens in subthreshold region with positive temperature activation due to interface traps generation in the gate-drain overlap (GDO) and localized charge trapping into the spacer oxide. Care has been done on the distinct impact of the measuring bias and stressing conditions in Sub-V T regime. The latter can be much more degraded than On-state parameters showing the amphoteric nature of Si-H bonds breaking rates throughout the channel-GDO. Off-mode damage has been included in the 3 mode energy device lifetime giving a useful modeling for any AC waveforms suitable for digital to analog operations.

International audience; Power law time-to-breakdown voltage acceleration is investigated down to ultra-thin oxides (1.1 nm) in the ESD regime in inversion and accumulation. Breakdown modes, oxide degradation and device drifts under ESD-like stress are discussed as function of the oxide thickness. The consequent impacts on the ESD design window are presented.

International audience; This paper presents a theoretical framework about interface state creation rate from Si–H bonds atthe Si/SiO2 interface. It includes three main ways of bond breaking. In the first case, the bond canbe broken, thanks to the bond ground state rising with an electrical field. In two other cases, incidentcarriers will play the main role either if there are very energetic or very numerous but less energetic.This concept allows one to physically model the reliability of metal oxide semiconductor field effecttransistors, and particularly negative bias temperature instability permanent part, and channel hotcarrier to cold carrier damage.

International audience; Channel hot-carrier degradation presents a renewed interest in the last NMOS nodes where the device reliability of bulk silicon (core) 40 nm and Input/Output (IO) device is difficult to achieve at high temperature as a function of supply voltage VDD and back bias VBS . A three mode interface trap generation is proposed based on the energy acquisition involved in distinct interactions in all the VGS , VDS (V BS ) conditions as a single IDS lifetime dependence is observed with VGD > 0. This gives a new age(t) function useful for accurate DC to AC transfers. Positive temperature activation is explained by the rise of ionization rate with electron-electron scattering (medium IDS ) and multi vibrational excitation (higher IDS ) which increase the H desorption by thermal emission. The use of forward VBS has shown no gain under CHC for both device types. The main limitation occurs under reverse VBS = -VDD in IO where the smaller temperature activation partially compensates the larger damage. In that case a security margin can be established giving a limit of VBS = -VDD /2 for design reliability.

a general framework is proposed to characterize digital library gates for NBTI and HCI ageing effects. Required parameters extraction is demonstrated for practical cases using accurate, state-of-the-art reliability simulation flow. Both NBTI recovery and HCI models are required to accurately assess digital product degradation

The understanding of the relationship between circuit lifetime and device DC hot carrier (HC) stress lifetime is becoming increasingly important for advanced nodes since supply voltage (Vdd) and channel length (L) do not scale anymore in similar proportions. This paper proposes a novel approach to tackle HC risk assessment through a combination of refined transistor HC modeling, Wafer Level Reliability (WLR) & High Temperature Operating Lifetest (HTOL) experimental results and simulations.

International audience; This paper presents an improvement of the R-D model explaining analytically the 0.5 exponent observed during HCI stress. An original model based on diffusion equation is proposed where the balance between the hot-hole-induced generation of dangling bonds and the passivation mechanisms via a Multi-Vibrational Hydrogen Release is enlightened. The second and smaller slope observed is explained and modelled with the hot spot displacement along the Si-SiO2 interface.

International audience; The distinct channel hot-carrier (CHC) degradation mechanisms have been observed in NLDEMOS processed from a SOI CMOS technology. The charge-pumping (CP) technique has evidenced the larger hot-hole efficiency in the damage mechanisms at maximum substrate current condition where a net hole trapping is observed in the overlap region which is further screened by the large increase of interface traps in this region. As a consequence, the device suffers from a mobility reduction due to the series-resistance increase mostly in linear mode which impacts the device speed response to AC signal. Off state stressing exhibits a very similar CHC degradation behavior due to the interface traps which may represents a limitative case for the pulses shape optimisation encountered in Class-E operation. A modified reaction-diffusion modelling is proposed based on the multi-vibrational hydrogen release mechanism which matches the time dependence and saturation effect. Finally, we show that the efficiency of E-Class power amplifier is weakly affected by the series-resistance degradation.

International audience; In this paper, we investigate the recovery characteristics associated with negative bias temperature instability and channel hot carrier degradation in p-channel metal–oxide– semiconductor using a novel method of on-the-fly patterns of biases. We demonstrate experimentally that we can identify two types of mechanisms associated with degradation. One of them is associated with recovery dynamics, and the other relates to non-recoverable degradation.

In this paper, we propose to distinguish the distinct carrier degradation modes as a function of the energy range developing a complete lifetime extrapolation technique down to the low voltage operation. This provides a starting point of a more accurate modeling of CHC effects during product operations. This work shows that CHC effects in nMOSFET consist in three different regimes depending on the gate voltage (Vg). A simple way to extrapolate lifetime at nominal bias conditions from data get under accelerated stress conditions was detailed for each regime. We also propose an answer to the contradictory debate of the respective contributions of electron-electron scattering (EES) (Rauch et al., 2001) and the multiple vibrational excitation (MVE) (Hess et al., 1999) to CHC effects in the low energy range.

This work views NBTI and various conditions of channel hot carrier (CHC) degradation in PMOS and NMOS devices from a unified perspective. This is accomplished by a novel technique using sequential application of stress biases and monitoring the degradation on-the-fly. Thereby, we are able to observe and segregate the distinct mechanisms co-existing during a particular condition of degradation. In particular, we gain critical insights into recovery phenomena, which are observed during certain conditions of CHC degradation (Mistry et al., 1991) as well as during NBTI (Rangan, 2003). These findings set the stage for consistent physical models for degradation as well as for design simulation under multiple operating modes

In this work, we confirm that the energy is the driving force of hot carrier effects. In the high energy-, long channel-case, the LEM picture is still valid. But when the energy is lowered, high energy electrons generated by electron-electron scattering (EES) become the dominant contribution to the degradation. Finally, for even lower energy, the hot carrier degradation becomes a composite mode combining both multiple vibrational excitation (MVE) mechanism (Hess, 1999) and medium-energy electrons heated by EES (Rauch, 2001)

Practical and accurate Design-in Reliability methodology has been developed for designs on 90-45nm technology to quantitatively assess the degradation due to Hot Carrier and Negative Bias Temperature Instability. Simulation capability has been built on top of an existing analog simulator ELDO. Circuits are analyzed using this methodology illustrating the capabilities of the methodology as well highlighting the impacts of the two degradations modes.

This work shows that Channel Hot Carrier (CHC) in nMOSFET consists in two different regimes depending on the gate voltage (Vg). At low Vg, a simple way to extrapolate lifetime at nominal bias conditions from data get under accelerated stress conditions will be detailed. At high Vg, the second degradation mode becomes worse depending on Vd. This work focuses on the worst case degradation determination and the model effects on the device lifetime prediction in relation to the CHC degradation mechanisms. A combined and complementary use of Charge Pumping (CP) and Direct Current Current Voltage (DCIV) allows us to obtain the spatial interface traps (Nit) localization giving more information on Nit impact on linear transistor parameters degradation.

Assessment of design implications due to degradation of CMOS devices is increasingly required in the latest technologies. This paper discusses degradation due to channel hot carriers, NBTI and oxide breakdown from a design perspective — in terms of characterization, mechanisms and circuit analysis — introducing assessment of multiple degradation modes on same device.

This paper presents new reliability investigations in NLDEMOS transistor in 0.13 mum SOI CMOS technology. Reliability tests under hot carrier injections (HCI) and OFF state regimes show a strong dependence with the drain extension length Lext. The use of borderless nitride in order to create contacts is suspected to be the origin of degradation. Mobiles charges in this nitride can move under electrical field in HCI or OFF-state stress and then modulate the conductivity of the drain extension region. With a reverse electrical field applied after OFF-state (drain) or HCI stress, we show that the degraded NLDEMOS can completely recover its initial performances. A novel nitride borderless with a decrease of SiH4 rate during process step shows a strong reliability improvement due to the decrease of dangling bonds at SiPROT/bordeless nitride interface

In this paper, we show that the effect of hot hole injections in ultra-thin oxide P-MOSFETs, is merged into the hole tunneling through the gate oxide. Thus, extrapolated lifetime techniques have to take into account both mechanisms. Even if quantitative distinction is difficult, we propose a first attempt to distinguish both contributions. This modelling allows to separate both mechanism consequences in relation to the extension of drain space charge region /spl Delta/L.

This work shows that the channel hot carrier (CHC) degradation for a p-MOSFET consists of two different regimes. At low V/sub g/, the degradation is dominated by hot electrons produced by impact ionization. The hot electrons are responsible for the creation of both interface traps and electron traps within the oxide. At high V/sub g/, a NBT-induced hot carrier effect is evidenced as well as an anomalous CHC effect. This work should help understanding the CHC degradation of pMOSFET as well as determining the worst case degradation.

This paper discusses the characterization and modeling methodology for NBTI for subsequent use in reliability simulations. Given the integral recovery post NBTI stress, we use on-the-fly technique to measure degradation. A new and fully experimental means of interpretation of results from OTF is presented. We also present some new evidence of hole-trapping/detrapping during NBTI degradation

In this work, we investigate recovery characteristics post NBTI stress when the recovery bias remains negative but lower in magnitude than the stress bias, consolidating the viewpoint involving role of hole trapping during NBTI degradation. We show that successive negative recovery biases can be applied to view trapping and detrapping behavior explicitly.

Despite large efforts given by the semiconductor community to overcome NBTI challenges in ultra-thin gate dielectrics, both the understanding of mechanisms [1-9] and the characterization methodology are not completely achieved yet. It is well accepted that the mechanisms lying behind NBTI are the interface traps generation, the fixed charges build-up and the hole trapping in the gate oxide [8]. The effort is devoted reducing the inherent recovery during the NBTI characterization. The standard methodology [12] has been shown to have serious effects on the degradation itself [13, 11, 8]. In this context and since the degradation is not permanent but recoverable, we propose in this work a new framework to manage NBTI in ultra-scaled technologies. This takes into account both the recoverable proportion of the degradation, which is studied in the first part of the paper, and the electrical parameter legitimacy for DC and AC modes analysis developed in the second part.

This work presents new perspectives of the NBTI in advanced technology. Both modelling and characterization of NBTI are investigated for the maturation of the reliability management in advanced node technologies. A physical-based VT instability model is presented considering interface trapped charges, fixed charges and oxide trapped holes effects. Finally, we discuss on the lifetime concept in the case of recoverable NBTI-induced degradation.

International audience; This paper presents results of reliability investigation of 20 V N-Drift MOS transistor in 0.13 μm CMOS technology. Due to high performances required for CMOS applications, adding high voltage devices becomes a big challenge to guarantee the reliability criteria. In this context, new reliability approaches are needed. Safe Operating Area are defined for switch, Vds limited and Vgs limited applications in order to improve circuit designs. For Vds limited applications, deep doping dose effects in drift area are investigated in correlation to lifetime evaluations based on device parameter shifts under hot carrier stressing. To further determine the amount and locations of hot carrier injections, accurate 2D technological and electrical simulations are performed and permit to select the best compromise between performance and reliability for N-Drift MOS transistor.

We focus in this study on the negative bias temperature instability (NBTI)-induced /spl Delta/N/sub IT/ phenomenon and we point out its relative gate-oxide thickness (T/sub OX/) dependences. Studies are carried out in a large T/sub OX/ range, comparing the gate-oxide quality which was grown with or without nitrogen incorporation. We have developed an oxide field (F/sub OX/) dependence for /spl Delta/N/sub IT/ and we show the two opposite effects of T/sub OX/ on the threshold voltage shift (/spl Delta/V/sub T/). Simulation of both effects shows a good correlation with experimental results in pure oxide and confirms the reduced interface trapped charge effect in /spl Delta/V/sub T/ in nitrided devices. Results enable us to extrapolate the NBTI impact when T/sub OX/ is varied which allows us to determine in a useful way the security margin during the gate-oxide process optimization.

We have developed in this work a new characterization methodology which includes stressing and measurement in a single experimental step. This overcomes the influence of the hole detrapping effect in ultra-thin gate-oxides (T/sub OX/=1.4-1.6 nm) and enables comparison of gate-oxide nitridation impacts on negative bias temperature instability (NBTI). This new approach offers possibilities to measure the whole degradation and to improve DC NBTI characterization in operating logic circuits.

International audience; An overview of evolution of transistor parameters under negative bias temperature instability stress conditions commonly observed in p-MOSFETs in recent technologies is presented. The physical mechanisms of the degradation as well as the different defects involved have been discussed according to a systematic set of experiments with different stress conditions. According to our findings, a physical model is proposed which could be used to more accurately predict the transistor degradation. Finally, the influence of different process splits as the gate oxide nitridation, the nitrogen content, the source/drain implant and poly doping level on the NBTI degradation is investigated and discussed with our present understanding.

International audience; We propose a new methodology to characterize the negative bias temperature instability (NBTI) degradation without inherent recovery. The extracted parameters are the linear drain current, the threshold voltage and the transconductance. We compare the new and the usual methodologies and show a logarithmic time dependence of both the degradation and the recovery. The hole trapping (detrapping) is directly correlated to the VT degradation (recovery), and plays the main role in the NBTI in ultra-thin gate-oxide PMOSFET's.

We have studied the possibility to use hot carrier stresses to reveal the damage due wafer charging during plasma process steps in 0.18 /spl mu/m, 0.25 /spl mu/m and 0.6 /spl mu/m CMOS technologies. We have investigated various hot carrier conditions in N- and P-MOSFETs and compared the results to classical parameter studies and short high field injections using a relative sensitivity factor. The most accurate monitor remains the threshold voltage and the most sensitive configuration is found to be short hot electron injections in PMOSFET's.

This work gives an insight of the degradation mechanisms during negative and positive bias temperature instability in advanced CMOS technology with a 2nm gate-oxide. We focus on generated interface traps and oxide traps to distinguish their dependencies and effects on usual transistor parameters. NBTI and PBTI in NMOS and PMOS have been compared a possible explanation for all configurations has been suggested. Relaxation and temperature effects under NBTI were also investigated showing different behaviors of the two components of threshold voltage shift, i.e. the interface traps and the oxide traps.

International audience; Hot-carrier reliability is studied in core logic PMOSFETs with a thin gate-oxide (Tox=2 nm) and in Input/Output PMOSFETs with a thick gate-oxide (6.5 nm) used for systems on chip applications. Hot-hole (HH) injections are found to play a more important role in the injection mechanisms and in the degradation efficiency. This depends on the technology node for stressing voltage conditions corresponding to channel hot-hole injections, i.e. closer to the supply voltage than the other voltage condition. Distinct mechanisms of carrier injections and hot-carrier degradation are found in core devices used for high speed (HS) and low leakage (LL) applications where the hole tunneling current dominates at low voltages while the electron valence band tunneling from the gate occurs at gate-voltages above −1.8 V. Devices with Tox=6.5 nm have shown the existence of a thermionic hot-hole gate-current which is directly measured at larger voltages. This is related to the increase in the surface doping, the thinning of the drain junction depth and the location of the hot-carrier generation rate which is closer to the interface. Results show that hole injections worsen the hot-carrier damage in thin and thick gate-oxides which are both distinguished by the effects of the interface trap generation, the permanent hole trapping and the hole charging–discharging from slow traps using alternated stressing in thin gate-oxides. This consequently leads to a significant lifetime increase in 2 nm HS, LL devices with respect to 6.5 nm Input/Output devices explained by the dominant effect of the fast interface trap generation due to the hole discharge from slow traps and bulk oxide traps in 2 nm devices at the tunneling distance of the interface.