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We introduce a new method for adaptive one-bit quantization of linear measurements and propose an algorithm for the recovery of signals based on generalized approximate message passing (GAMP). Our method exploits the prior statistical information on the signal for estimating the minimum-mean-squared error solution from one-bit measurements. Our approach allows the one-bit quantizer to use thresholds on the real line. Given the previous measurements, each new threshold is selected so as to partition the consistent region along its centroid computed by GAMP. We demonstrate that the proposed adaptive-quantization scheme with GAMP reconstruction greatly improves the performance of signal and image recovery from one-bit measurements.

The continuous-time bandpass delta-sigma analog-to-digital conversion is an interesting approach for direct conversion of radiofrequencies signals. To go towards fast and reconfigurable conversion systems, the feasibility of a delta-sigma band-pass converter with a tunable central frequency on a limited bandwidth is studied through the design of an integrated circuit in a GaAs P-HEMT technology.The modulator architecture includes a loop filter, which has a parallel structure to ensure the stability as well as the precision of the device, an adder and a comparator. The loop filter is composed of several Q-enhanced Gm-LC resonators. The optimal delay for this architecture (1:25Te, with Te the sampling period) is approximately reached through a latched comparator (1,12 Te). The adjustment of the central frequency is carried out through one tunable capacity on the front-end resonator.The transistor level simulation in the nominal case shows a resolution of 10 bits in a useful bandwidth of 4 MHz, for a central frequency of 750 MHz and a 3 GHz sampling frequency. The central frequency of the modulator can be adjusted at 730 MHz where the resolution reaches 9 bits. Consumption is estimated to be 5,7 W. The layout of the chip occupies 12 mm2.This work presents a design methodology based on multi-level simulations (transistor, functional).This approach makes it possible to isolate the impact from circuit level non-idealities on the general behaviour of the modulator. Solutions are proposed to correct these drawbacks. The circuit sensitivity was also studied in terms of technological dispersions and parasitic elements introduced by the layout., La conversion analogique-numérique sigma-delta passe-bande à temps continu constitue une approche intéressante pour la numérisation directe de signaux radiofréquences. Pour faire un premier pas vers des systèmes de conversion rapides et agiles basés sur cette approche, la faisabilité d'un convertisseur sigma-delta passe-bande à fréquence centrale ajustable sur une bande de fréquence limitée est étudiée au travers de la conception d'un circuit intégré prototype en technologie GaAs P-HEMT 0.2 µm.L'architecture du modulateur sigma-delta comprend un filtre de boucle à structure parallèle, afin d'assurer à la fois la stabilité et la précision du dispositif, un sommateur et un comparateur. Les filtres passe-bande, constitutifs du filtre de boucle, sont du type Gm-LC à résistance négative. Le retard optimal théorique pour cette architecture est de 1,25 Te (Te : période d'échantillonnage) et ce retard est approximativement atteint grâce à un comparateur verrouillable (1,12 Te). Le réglage de la fréquence centrale s'opère par le biais de varicaps dans le résonateur d'entrée. La simulation du circuit au niveau transistor permet d'évaluer une résolution de 10 bits sur une bande de 4 MHz pour une fréquence centrale de 750 MHz et une fréquence de sur-échantillonnage de 3 GHz. La fréquence centrale du modulateur peut être abaissée à 725 MHz où la résolution atteint 9 bits. La consommation est estimée à 5,7 W. Le circuit a été implanté et la surface de la puce s'élève à 12 mm2.Ce travail présente une méthodologie de conception basée sur des simulations multi-niveaux (transistor, fonctionnel). Cette approche permet d'isoler l'impact des non-idéalités de chacun des blocs au niveau circuit sur le fonctionnement général du modulateur. Des solutions sont proposées pour la correction de ces défauts. La robustesse du circuit a aussi fait l'objet d'une étude en termes de dispersions technologiques et d'éléments parasites introduits par l'implantation. Des remèdes sont proposés pour pallier ces problèmes.

A new method is presented for the calibration and the linearity testing of analog-to-digital converters (ADCs) and dc digital instruments, such as digital voltmeters (DVMs). The test is truly static, because it uses only dc voltages with a small superimposed noise (dithering). It is much faster than that described in the IEEE Standard 1057/94 since it uses a minimal number of test signals and acquired samples in a theoretically nearly optimal manner, i.e., maximum-likelihood estimation. In addition, contrary to the test described in the IEEE Standard 1241/00, it allows offline measurements and testing of stand-alone instruments, such as DVMs. Another advantage of the proposed method is that the resolution requirements for the source of test signals are relaxed. After a review of the state of the art, this paper provides the mathematical derivation of the employed estimator. Simulations, theoretical analyses, and experimental results are also provided to illustrate the performances of the proposed test method.

An analytical model to evaluate the hybrid architecture of a wide bandwidth high-speed digitizer is proposed. The model is based on the robust approach of multi-rate signal processing theory and allows analyzing the effects of the impairments that can affect the digitizer, and consequently evaluating achievable performance. The proposed model can also be used at design stage to identify viable solutions for counteracting the effects of the impairments. More specifically, it can be used to identify the correction filters that provide a digital representation of the input signal that minimizes spurious terms and distortions.

In recent years, modern imaging sensors and systems have become increasingly complex following the growing demand for high-quality and high-resolution imaging. Commercially available sensors having 30-40 mega-pixel resolutions are common nowadays, while professional and scientific imaging systems (e.g. telescope and satellite sensors) often have hundreds of mega-pixels or even giga-pixel resolution. Such sensors or multi-sensor systems generate extreme amounts of data and require an excessive amount of power in order to process and stream-out the acquired data at the required speed. Consequently, three difficult and closely related bottlenecks appear in such systems: power consumption, data bandwidth and memory storage. Nevertheless, the vast majority of applications (such as machine vision, bio-medical, surveillance, space imaging, etc.) do not process all the data acquired from the conventional image acquisition. In fact, most of the image (video) data is extremely redundant in both temporal and spatial domain. Moreover, in many of these applications, this excessive data is simply discarded despite the additional resources that were used to acquire it. This Thesis explores new and and "smart" ways of image acquisition that can exploit this redundancy and reduce the required image data. The ultimate goal of the research conducts into reducing the power consumption, system bandwidth, memory requirements and improve the overall system efficiency in numerous modern image acquisition applications. The main focus of this Thesis is the investigation of three unconventional approaches to image acquisition that offer power, bandwidth and memory storage reduction. All three methods are explored in the context of CMOS integrated circuit implementation directly on the focal-plane in order to maximize their efficiency. The first investigated method is called "relative imaging" (RI). The image sensor detects the relative ratios of the photo-currents corresponding to the neighboring pixels without performing pixel integration. This method allows high frame-rates with a very high dynamic range. Moreover, detecting the photo-current ratios (instead of the absolute amplitudes) corresponds better to the intrinsic nature of VLSI design. The second investigated method which enables the reduction of the required image information is compressive sampling (CS). Compressive sampling exploits image sparsity in order to reduce the amount of information that is required to guarantee correct image reconstruction. The third method, multi-band edge detection (MBED), decomposes the image content into separate frequency bands and performs single-bit quantization of each frequency band separately. It achieves 1-1.33 bit-per-pixel compression level, while preserving most of the image information and demonstrating robust performance in the presence of noise and other physical non-idealities. An additional focus of this Thesis is the design of unconventional analog-to-digital converter (ADC) topologies convenient for "smart" image acquisition.

Consider the problem of sampling signals which are not bandlimited, but still have a finite number of degrees of freedom per unit of time, such as, for example, nonuniform splines or piecewise polynomials, and call the number of degrees of freedom per unit of time the rate of innovation. Classical sampling theory does not enable a perfect reconstruction of such signals since they are not bandlimited. Recently, it was shown that, by using an adequate sampling kernel and a sampling rate greater or equal to the rate of innovation, it is possible to reconstruct such signals uniquely . These sampling schemes, however, use kernels with infinite support, and this leads to complex and potentially unstable reconstruction algorithms. In this paper, we show that many signals with a finite rate of innovation can be sampled and perfectly reconstructed using physically realizable kernels of compact support and a local reconstruction algorithm. The class of kernels that we can use is very rich and includes functions satisfying Strang–Fix conditions, exponential splines and functions with rational Fourier transform. This last class of kernels is quite general and includes, for instance, any linear electric circuit. We, thus, show with an example how to estimate a signal of finite rate of innovation at the output of an RC circuit. The case of noisy measurements is also analyzed, and we present a novel algorithm that reduces the effect of noise by oversampling.

In this paper, a new frequency-domain approach to measure and correct the static nonlinearity error of analog-to-digital converters is analyzed. The nonlinearity is measured as a linear combination of the Chebyshev polynomials, whose coefficients are derived via frequency-domain analysis, and corrected with a nonlinear equation solving method, which makes use of the parametric form of the static characteristics. The proposed methodology is especially suited for dithered converters, due to their particular features of smoother nonlinearity and very high resolution. Both simulation and experimental results are reported, quantifying also the achieved increase of effective bits.

In this paper, the use of the fast Fourier transform (FFT) test to measure the integral nonlinearity (INL) of analog-to-digital (A/D) converters is examined. The derived INL is a linear combination of Chebyshev polynomials, where the coefficients are the spurious harmonics of the output spectrum. The accuracy of the test is examined theoretically, in simulations and in practical devices, particularly for the critical (and typical) case when sudden jumps are present in the actual INL. The examined methodology appears to be very convenient when the device under test has high resolution (16-20 bits) and a smoothed approximation of the INL is sufficient, as the FFT test is in this case thousands of times faster than the customary histogram test and static nonlinearity test.

A computer based test system for FM signal generators is presented. The proposed measurement procedure is based on the economical software implementation of an analog-to-digital conversion (ADC) linearization algorithm followed by an accurate short-time Fourier transform analysis with spectral interpolation. The very good accuracy performance of the system is illustrated through computer simulation and experimental results.

This paper introduces a concept of analog-to-digital conversion for very high-speed applications. Like the time-interleaving conversion, this method uses different conventional ADCs (channels), which work in parallel, but the approach is different. The basic principle is close to techniques used in signal processing, such as the discrete Fourier transform (DFT) and sub-band coding. Because of its low sensitivity to sampling-clock jitter; this technique can achieve a 6 bit effective accuracy up to the Nyquist frequency.

As CMOS processes continue to scale to smaller dimensions, the increased fT of the devices and smaller parasitic capacitance allow formore power efficient and faster digital circuits to be made. But at the same time, output impedance of transistors has gone down, as have the power supply voltages, and leakage currents have increased. These changes in the technology havemade analog design more difficult.More specifically, the design of a high gain op-amp, a fundamental analog building block, has becomemore difficult in scaled processes. In this work, to improve the performance considering the speed, accuracy and power consumption of the analog-digital interface, both system level optimization and circuit level technique are explored. At first, a generalized graphic model (GGM) is proposed to analyze the resolution of ADC for wireless receiver. This model could show the trade-off between ADC the RF front-end in the power level graph. As a result, the optimization between them becomes practical. Next, two kinds of open loop ADCs are designed and implemented for ultra-wide bandwidth (UWB) receiver and capacitive sensor interface respectively. There is no closed loop stage in the flash ADC, which ensures the fastest conversion speed. An intended spatial filter technique is adopted to attenuate the distortion coming from the interpolation network. The successive approximation (SAR) ADC based switched capacitor sensor interface digitizes the capacitance variation to binary code. A cascade binary weighted DAC is used to reduce the power consumption and area. The noise and distortion performance are optimized throughout the design.