501. A High-Voltage LDMOS Compatible With High-Voltage Integrated Circuits on p-Type SOl Layer.
- Author
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Xiaorong Luo, Tianfei Lei, Yuangang Wang, Huanmei Gao, Jian Fang, Ming Qiao, Wei Zhang, Hao Deng, Bo Zhang, Zhaoji Li, Zhiqiang Xiao, Zhengcai Chen, and Jing Xu
- Subjects
SEMICONDUCTOR research ,ELECTRIC fields ,HIGH voltages ,INTEGRATED circuits ,SILICON-on-insulator technology - Abstract
Breakdown mechanism for a high-voltage n-channel LDMOS compatible with a high-voltage integrated circuit (HVIC) on a p-type silicon-on-insulator (SOI) layer is investigated theoretically and experimentally. The device is characterized by buried n-islands on a buried oxide layer (BOX). For the proposed structure, ionized donors in n-islands enhance the bottom-interface electric field of the SOI layer from 10 V/μm in the conventional devices on p-SOI layer to 27 V/μm, resulting in enhancement of the BOX electric field E
I from 30 to 82 V/μm. Moreover, holes located between the depleted n-islands help to increase EI as well. Both improve the blocking capability of the device. A 660-V SOI LDMOS is obtained, in which the implanted n-type drift region, along with the n-islands on a p-type SOI layer, realizes the self-isolation in HVIC. [ABSTRACT FROM AUTHOR]- Published
- 2009
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