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442 results on '"Platzner, Marco"'

401. Real Environments Image Labelling Based on Reconfigurable Architectures

Author

Chamizo, Juan Manuel García, Guilló, Andrés Fuster, López, Jorge Azorín, Hutchison, David, editor, Kanade, Takeo, editor, Kittler, Josef, editor, Kleinberg, Jon M., editor, Mattern, Friedemann, editor, Mitchell, John C., editor, Naor, Moni, editor, Nierstrasz, Oscar, editor, Pandu Rangan, C., editor, Steffen, Bernhard, editor, Sudan, Madhu, editor, Terzopoulos, Demetri, editor, Tygar, Dough, editor, Vardi, Moshe Y., editor, Weikum, Gerhard, editor, Becker, Jürgen, editor, Platzner, Marco, editor, and Vernalde, Serge, editor

Published
2004
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402. A VHDL Generator for Elliptic Curve Cryptography

Author

Järvinen, Kimmo, Tommiska, Matti, Skyttä, Jorma, Hutchison, David, editor, Kanade, Takeo, editor, Kittler, Josef, editor, Kleinberg, Jon M., editor, Mattern, Friedemann, editor, Mitchell, John C., editor, Naor, Moni, editor, Nierstrasz, Oscar, editor, Pandu Rangan, C., editor, Steffen, Bernhard, editor, Sudan, Madhu, editor, Terzopoulos, Demetri, editor, Tygar, Dough, editor, Vardi, Moshe Y., editor, Weikum, Gerhard, editor, Becker, Jürgen, editor, Platzner, Marco, editor, and Vernalde, Serge, editor

Published
2004
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403. FPGA-Based Parallel Comparison of Run-Length-Encoded Strings

Author

Bogliolo, Alessandro, Freschi, Valerio, Miglioli, Filippo, Canella, Matteo, Hutchison, David, editor, Kanade, Takeo, editor, Kittler, Josef, editor, Kleinberg, Jon M., editor, Mattern, Friedemann, editor, Mitchell, John C., editor, Naor, Moni, editor, Nierstrasz, Oscar, editor, Pandu Rangan, C., editor, Steffen, Bernhard, editor, Sudan, Madhu, editor, Terzopoulos, Demetri, editor, Tygar, Dough, editor, Vardi, Moshe Y., editor, Weikum, Gerhard, editor, Becker, Jürgen, editor, Platzner, Marco, editor, and Vernalde, Serge, editor

Published
2004
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404. A Dynamically Reconfigurable Function-Unit for Error Detection and Correction in Mobile Terminals

Author

Pionteck, Thilo, Stiefmeier, Thomas, Staake, Thorsten R., Glesner, Manfred, Hutchison, David, editor, Kanade, Takeo, editor, Kittler, Josef, editor, Kleinberg, Jon M., editor, Mattern, Friedemann, editor, Mitchell, John C., editor, Naor, Moni, editor, Nierstrasz, Oscar, editor, Pandu Rangan, C., editor, Steffen, Bernhard, editor, Sudan, Madhu, editor, Terzopoulos, Demetri, editor, Tygar, Dough, editor, Vardi, Moshe Y., editor, Weikum, Gerhard, editor, Becker, Jürgen, editor, Platzner, Marco, editor, and Vernalde, Serge, editor

Published
2004
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405. Artificial Neural Networks Processor – A Hardware Implementation Using a FPGA

Author

Ferreira, Pedro, Ribeiro, Pedro, Antunes, Ana, Dias, Fernando Morgado, Hutchison, David, editor, Kanade, Takeo, editor, Kittler, Josef, editor, Kleinberg, Jon M., editor, Mattern, Friedemann, editor, Mitchell, John C., editor, Naor, Moni, editor, Nierstrasz, Oscar, editor, Pandu Rangan, C., editor, Steffen, Bernhard, editor, Sudan, Madhu, editor, Terzopoulos, Demetri, editor, Tygar, Dough, editor, Vardi, Moshe Y., editor, Weikum, Gerhard, editor, Becker, Jürgen, editor, Platzner, Marco, editor, and Vernalde, Serge, editor

Published
2004
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406. FPGA Implementation of the Ridge Line Following Fingerprint Algorithm

Author

Cantó, E., Canyellas, N., Fons, M., Fons, F., López, M., Hutchison, David, editor, Kanade, Takeo, editor, Kittler, Josef, editor, Kleinberg, Jon M., editor, Mattern, Friedemann, editor, Mitchell, John C., editor, Naor, Moni, editor, Nierstrasz, Oscar, editor, Pandu Rangan, C., editor, Steffen, Bernhard, editor, Sudan, Madhu, editor, Terzopoulos, Demetri, editor, Tygar, Dough, editor, Vardi, Moshe Y., editor, Weikum, Gerhard, editor, Becker, Jürgen, editor, Platzner, Marco, editor, and Vernalde, Serge, editor

Published
2004
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407. FPGA Implementation of a Neuromimetic Cochlea for a Bionic Bat Head

Author

Clarke, Chris, Qiang, Lin, Peremans, Herbert, Hernández, Álvaro, Hutchison, David, editor, Kanade, Takeo, editor, Kittler, Josef, editor, Kleinberg, Jon M., editor, Mattern, Friedemann, editor, Mitchell, John C., editor, Naor, Moni, editor, Nierstrasz, Oscar, editor, Pandu Rangan, C., editor, Steffen, Bernhard, editor, Sudan, Madhu, editor, Terzopoulos, Demetri, editor, Tygar, Dough, editor, Vardi, Moshe Y., editor, Weikum, Gerhard, editor, Becker, Jürgen, editor, Platzner, Marco, editor, and Vernalde, Serge, editor

Published
2004
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408. Seven recipes for setting your FPGA on fire – A cookbook on heat generators.

Author

Agne, Andreas, Hangmann, Hendrik, Happe, Markus, Platzner, Marco, and Plessl, Christian

Subjects
*FIELD programmable gate arrays, *GENERATORS (Computer programs), *THERMAL management (Electronic packaging), *COMPUTER simulation, *ELECTRIC oscillators
Abstract

Due to the continuously shrinking device structures and increasing densities of FPGAs, thermal aspects have become the new focus for many research projects over the last years. Most researchers rely on temperature simulations to evaluate their novel thermal management techniques. However, these temperature simulations require a high computational effort if a detailed thermal model is used and their accuracies are often unclear. In contrast to simulations, the use of synthetic heat sources allows for experimental evaluation of temperature management methods. In this paper we investigate the creation of significant rises in temperature on modern FPGAs to enable future evaluation of thermal management techniques based on experiments. To that end, we have developed seven different heat-generating cores that use different subsets of FPGA resources. Our experimental results show that, according to external temperature probes connected to the FPGA’s heat sink, we can increase the temperature by an average of 81 °C. This corresponds to an average increase of 156.3 °C as measured by the built-in thermal diodes of our Virtex-5 FPGAs in less than 30 min by only utilizing about 21 percent of the slices. [ABSTRACT FROM AUTHOR]

Published
2014
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409. Efficient Utilization of DSPs and BRAMs Revisited: New AES-GCM Recipes on FPGAs

Author

Nele Mentens, Jo Vliegen, Tolga Yalcin, Elif Bilge Kavun, Andrews, David, Cumplido, René, Feregrino, Claudia, and Platzner, Marco

Subjects
Block cipher mode of operation, business.industry, Computer science, Append, AES implementations, GCM transcription factors, MPSoC, Embedded system, ComputerSystemsOrganization_SPECIAL-PURPOSEANDAPPLICATION-BASEDSYSTEMS, Multiplication, Hardware_ARITHMETICANDLOGICSTRUCTURES, business, Field-programmable gate array, Hardware_REGISTER-TRANSFER-LEVELIMPLEMENTATION, Digital signal processing
Abstract

In 2008, Drimer et al. proposed different AES implementations on a Xilinx Virtex-5 FPGA, making efficient use of the DSP slices and BRAM tiles available on the device. Inspired by their work, we evaluate the feasibility of extending AES with the popular GCM mode of operation, still concentrating on the optimal use of DSP slices and BRAM tiles. We make use of a Xilinx Zynq UltraScale+ MPSoC FPGA with improved DSP features. For the AES part, we implement Drimer's round-based and unrolled pipelined architectures differently, still using DSPs and BRAMs efficiently based on the AES Tbox approach. On top of AES, we append the GCM mode of operation, where we use DSP slices to support the GCM finite field multiplication. This allows us to implement AES-GCM with a small amount of FFs and LUTs. We propose two implementations: A relatively compact round-based design and a faster unrolled design.

Published
2019

410. ROS-Enabled Hardware Framework for Experimental Robotics

Author

Leon Bonde Larsen, Beck Strohmer, Anders Bøgild, Anders Stengaard Sørensen, Andrews, David, Cumplido, Rene, Feregrino, Claudia, and Platzner, Marco

Subjects
Single chip, business.industry, Computer science, Interface (computing), 020206 networking & telecommunications, Robotics, 02 engineering and technology, Microcontroller, Embedded system, Middleware, Hardware_INTEGRATEDCIRCUITS, 0202 electrical engineering, electronic engineering, information engineering, Code (cryptography), Robot, 020201 artificial intelligence & image processing, Artificial intelligence, business, Field-programmable gate array
Abstract

Applying FPGAs and real-time bare-metal code in experimental robots has many benefits but puts high demands on the skills of students and researchers. This contribution presents an interface between FPGA, hard-macro microcontroller cores and the popular middleware ROS implemented on a single chip.

Published
2019

411. Automated Mapping of Coarse-Grain Pipelined Applications to FPGA Systems

Author

Ziegler, Heidi E., Hutchison, David, editor, Kanade, Takeo, editor, Kittler, Josef, editor, Kleinberg, Jon M., editor, Mattern, Friedemann, editor, Mitchell, John C., editor, Naor, Moni, editor, Nierstrasz, Oscar, editor, Pandu Rangan, C., editor, Steffen, Bernhard, editor, Sudan, Madhu, editor, Terzopoulos, Demetri, editor, Tygar, Dough, editor, Vardi, Moshe Y., editor, Weikum, Gerhard, editor, Becker, Jürgen, editor, Platzner, Marco, editor, and Vernalde, Serge, editor

Published
2004
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412. A System on Chip Design Framework for Prime Number Validation Using Reconfigurable Hardware

Author

Cheung, Ray C. C., Hutchison, David, editor, Kanade, Takeo, editor, Kittler, Josef, editor, Kleinberg, Jon M., editor, Mattern, Friedemann, editor, Mitchell, John C., editor, Naor, Moni, editor, Nierstrasz, Oscar, editor, Pandu Rangan, C., editor, Steffen, Bernhard, editor, Sudan, Madhu, editor, Terzopoulos, Demetri, editor, Tygar, Dough, editor, Vardi, Moshe Y., editor, Weikum, Gerhard, editor, Becker, Jürgen, editor, Platzner, Marco, editor, and Vernalde, Serge, editor

Published
2004
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413. Scalable Defect Tolerance Beyond the SIA Roadmap

Author

Mishra, Mahim, Hutchison, David, editor, Kanade, Takeo, editor, Kittler, Josef, editor, Kleinberg, Jon M., editor, Mattern, Friedemann, editor, Mitchell, John C., editor, Naor, Moni, editor, Nierstrasz, Oscar, editor, Pandu Rangan, C., editor, Steffen, Bernhard, editor, Sudan, Madhu, editor, Terzopoulos, Demetri, editor, Tygar, Dough, editor, Vardi, Moshe Y., editor, Weikum, Gerhard, editor, Becker, Jürgen, editor, Platzner, Marco, editor, and Vernalde, Serge, editor

Published
2004
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414. A Specific Scheduling Flow for Dynamically Reconfigurable Hardware

Author

Resano, Javier, Hutchison, David, editor, Kanade, Takeo, editor, Kittler, Josef, editor, Kleinberg, Jon M., editor, Mattern, Friedemann, editor, Mitchell, John C., editor, Naor, Moni, editor, Nierstrasz, Oscar, editor, Pandu Rangan, C., editor, Steffen, Bernhard, editor, Sudan, Madhu, editor, Terzopoulos, Demetri, editor, Tygar, Dough, editor, Vardi, Moshe Y., editor, Weikum, Gerhard, editor, Becker, Jürgen, editor, Platzner, Marco, editor, and Vernalde, Serge, editor

Published
2004
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415. The case for reconfigurable hardware in wearable computing.

Author

Plessl, Christian, Enzler, Rolf, Walder, Herbert, Beutel, Jan, Platzner, Marco, Thiele, Lothar, and Tröster, Gerhard

Subjects
*WEARABLE technology, *PORTABLE computers, *MOBILE computing, *COMPUTER input-output equipment, *EMBEDDED computer systems, *COMPUTER operating systems
Abstract

Wearable computers are embedded into the mobile environment of their users. A design challenge for wearable systems is to combine the high performance required for tasks such as video decoding with the low energy consumption required to maximise battery runtimes and the flexibility demanded by the dynamics of the environment and the applications. In this paper, we demonstrate that reconfigurable hardware technology is able to answer this challenge. We present the concept and the prototype implementation of an autonomous wearable unit with reconfigurable modules (WURM). We discuss experiments that show the uses of reconfigurable hardware in WURM: ASICs-on-demand and adaptive interfaces. Finally, we present an experiment with an operating system layer for WURM. [ABSTRACT FROM AUTHOR]

Published
2003
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416. Efficient FPGA-Based Security Kernels

Author

Baker, Zachary K., Hutchison, David, editor, Kanade, Takeo, editor, Kittler, Josef, editor, Kleinberg, Jon M., editor, Mattern, Friedemann, editor, Mitchell, John C., editor, Naor, Moni, editor, Nierstrasz, Oscar, editor, Pandu Rangan, C., editor, Steffen, Bernhard, editor, Sudan, Madhu, editor, Terzopoulos, Demetri, editor, Tygar, Dough, editor, Vardi, Moshe Y., editor, Weikum, Gerhard, editor, Becker, Jürgen, editor, Platzner, Marco, editor, and Vernalde, Serge, editor

Published
2004
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417. On Computing Maximum Likelihood Phylogeny Using FPGA

Author

Mak, Terrence S. T., Lam, K. P., Hutchison, David, editor, Kanade, Takeo, editor, Kittler, Josef, editor, Kleinberg, Jon M., editor, Mattern, Friedemann, editor, Mitchell, John C., editor, Naor, Moni, editor, Nierstrasz, Oscar, editor, Pandu Rangan, C., editor, Steffen, Bernhard, editor, Sudan, Madhu, editor, Terzopoulos, Demetri, editor, Tygar, Dough, editor, Vardi, Moshe Y., editor, Weikum, Gerhard, editor, Becker, Jürgen, editor, Platzner, Marco, editor, and Vernalde, Serge, editor

Published
2004
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418. Minimising Reconfiguration Overheads in Embedded Applications (Abstract)

Author

Malik, Usama, Hutchison, David, editor, Kanade, Takeo, editor, Kittler, Josef, editor, Kleinberg, Jon M., editor, Mattern, Friedemann, editor, Mitchell, John C., editor, Naor, Moni, editor, Nierstrasz, Oscar, editor, Pandu Rangan, C., editor, Steffen, Bernhard, editor, Sudan, Madhu, editor, Terzopoulos, Demetri, editor, Tygar, Dough, editor, Vardi, Moshe Y., editor, Weikum, Gerhard, editor, Becker, Jürgen, editor, Platzner, Marco, editor, and Vernalde, Serge, editor

Published
2004
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419. Implementing Graphics Shaders Using FPGAs

Author

Thomas, David B., Luk, Wayne, Hutchison, David, editor, Kanade, Takeo, editor, Kittler, Josef, editor, Kleinberg, Jon M., editor, Mattern, Friedemann, editor, Mitchell, John C., editor, Naor, Moni, editor, Nierstrasz, Oscar, editor, Pandu Rangan, C., editor, Steffen, Bernhard, editor, Sudan, Madhu, editor, Terzopoulos, Demetri, editor, Tygar, Dough, editor, Vardi, Moshe Y., editor, Weikum, Gerhard, editor, Becker, Jürgen, editor, Platzner, Marco, editor, and Vernalde, Serge, editor

Published
2004
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420. Application Specific Small-Scale Reconfigurability

Author

Kumar, Vinu Vijay, Hutchison, David, editor, Kanade, Takeo, editor, Kittler, Josef, editor, Kleinberg, Jon M., editor, Mattern, Friedemann, editor, Mitchell, John C., editor, Naor, Moni, editor, Nierstrasz, Oscar, editor, Pandu Rangan, C., editor, Steffen, Bernhard, editor, Sudan, Madhu, editor, Terzopoulos, Demetri, editor, Tygar, Dough, editor, Vardi, Moshe Y., editor, Weikum, Gerhard, editor, Becker, Jürgen, editor, Platzner, Marco, editor, and Vernalde, Serge, editor

Published
2004
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421. Optimized Field Programmable Gate Array Based Function Evaluation

Author

Sidahao, Nalin, Hutchison, David, editor, Kanade, Takeo, editor, Kittler, Josef, editor, Kleinberg, Jon M., editor, Mattern, Friedemann, editor, Mitchell, John C., editor, Naor, Moni, editor, Nierstrasz, Oscar, editor, Pandu Rangan, C., editor, Steffen, Bernhard, editor, Sudan, Madhu, editor, Terzopoulos, Demetri, editor, Tygar, Dough, editor, Vardi, Moshe Y., editor, Weikum, Gerhard, editor, Becker, Jürgen, editor, Platzner, Marco, editor, and Vernalde, Serge, editor

Published
2004
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422. MemMap-pd: Performance Driven Technology Mapping Algorithm for FPGAs with Embedded Memory Blocks

Author

Manimegalai, R., ManojKumar, A., Jayaram, B., Kamakoti, V., Hutchison, David, editor, Kanade, Takeo, editor, Kittler, Josef, editor, Kleinberg, Jon M., editor, Mattern, Friedemann, editor, Mitchell, John C., editor, Naor, Moni, editor, Nierstrasz, Oscar, editor, Pandu Rangan, C., editor, Steffen, Bernhard, editor, Sudan, Madhu, editor, Terzopoulos, Demetri, editor, Tygar, Dough, editor, Vardi, Moshe Y., editor, Weikum, Gerhard, editor, Becker, Jürgen, editor, Platzner, Marco, editor, and Vernalde, Serge, editor

Published
2004
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423. Run-Time Reconfiguration Management for Adaptive High-Performance Computing Systems

Author

Taher, Mohamed, El-Ghazawi, Tarek, Hutchison, David, editor, Kanade, Takeo, editor, Kittler, Josef, editor, Kleinberg, Jon M., editor, Mattern, Friedemann, editor, Mitchell, John C., editor, Naor, Moni, editor, Nierstrasz, Oscar, editor, Pandu Rangan, C., editor, Steffen, Bernhard, editor, Sudan, Madhu, editor, Terzopoulos, Demetri, editor, Tygar, Dough, editor, Vardi, Moshe Y., editor, Weikum, Gerhard, editor, Becker, Jürgen, editor, Platzner, Marco, editor, and Vernalde, Serge, editor

Published
2004
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424. Automated Speculation and Parallelism in High Performance Network Applications

Author

Schelle, Graham, Grunwald, Dirk, Hutchison, David, editor, Kanade, Takeo, editor, Kittler, Josef, editor, Kleinberg, Jon M., editor, Mattern, Friedemann, editor, Mitchell, John C., editor, Naor, Moni, editor, Nierstrasz, Oscar, editor, Pandu Rangan, C., editor, Steffen, Bernhard, editor, Sudan, Madhu, editor, Terzopoulos, Demetri, editor, Tygar, Dough, editor, Vardi, Moshe Y., editor, Weikum, Gerhard, editor, Becker, Jürgen, editor, Platzner, Marco, editor, and Vernalde, Serge, editor

Published
2004
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425. Design and Evaluation of an FPGA Architecture for Software Protection

Author

Zambreno, Joseph, Hutchison, David, editor, Kanade, Takeo, editor, Kittler, Josef, editor, Kleinberg, Jon M., editor, Mattern, Friedemann, editor, Mitchell, John C., editor, Naor, Moni, editor, Nierstrasz, Oscar, editor, Pandu Rangan, C., editor, Steffen, Bernhard, editor, Sudan, Madhu, editor, Terzopoulos, Demetri, editor, Tygar, Dough, editor, Vardi, Moshe Y., editor, Weikum, Gerhard, editor, Becker, Jürgen, editor, Platzner, Marco, editor, and Vernalde, Serge, editor

Published
2004
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426. Preemptive Hardware Task Management

Author

Koch, Dirk, Hutchison, David, editor, Kanade, Takeo, editor, Kittler, Josef, editor, Kleinberg, Jon M., editor, Mattern, Friedemann, editor, Mitchell, John C., editor, Naor, Moni, editor, Nierstrasz, Oscar, editor, Pandu Rangan, C., editor, Steffen, Bernhard, editor, Sudan, Madhu, editor, Terzopoulos, Demetri, editor, Tygar, Dough, editor, Vardi, Moshe Y., editor, Weikum, Gerhard, editor, Becker, Jürgen, editor, Platzner, Marco, editor, and Vernalde, Serge, editor

Published
2004
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427. Design Space Exploration for Distributed Hardware Reconfigurable Systems

Author

Haubelt, Christian, Hutchison, David, editor, Kanade, Takeo, editor, Kittler, Josef, editor, Kleinberg, Jon M., editor, Mattern, Friedemann, editor, Mitchell, John C., editor, Naor, Moni, editor, Nierstrasz, Oscar, editor, Pandu Rangan, C., editor, Steffen, Bernhard, editor, Sudan, Madhu, editor, Terzopoulos, Demetri, editor, Tygar, Dough, editor, Vardi, Moshe Y., editor, Weikum, Gerhard, editor, Becker, Jürgen, editor, Platzner, Marco, editor, and Vernalde, Serge, editor

Published
2004
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428. TPR: Three-D Place and Route for FPGAs

Author

Ababei, Cristinel, Hutchison, David, editor, Kanade, Takeo, editor, Kittler, Josef, editor, Kleinberg, Jon M., editor, Mattern, Friedemann, editor, Mitchell, John C., editor, Naor, Moni, editor, Nierstrasz, Oscar, editor, Pandu Rangan, C., editor, Steffen, Bernhard, editor, Sudan, Madhu, editor, Terzopoulos, Demetri, editor, Tygar, Dough, editor, Vardi, Moshe Y., editor, Weikum, Gerhard, editor, Becker, Jürgen, editor, Platzner, Marco, editor, and Vernalde, Serge, editor

Published
2004
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429. Code Re-ordering for a Class of Reconfigurable Microprocessors

Author

Veale, Brian F., Antonio, John K., Tull, Monte P., Hutchison, David, editor, Kanade, Takeo, editor, Kittler, Josef, editor, Kleinberg, Jon M., editor, Mattern, Friedemann, editor, Mitchell, John C., editor, Naor, Moni, editor, Nierstrasz, Oscar, editor, Pandu Rangan, C., editor, Steffen, Bernhard, editor, Sudan, Madhu, editor, Terzopoulos, Demetri, editor, Tygar, Dough, editor, Vardi, Moshe Y., editor, Weikum, Gerhard, editor, Becker, Jürgen, editor, Platzner, Marco, editor, and Vernalde, Serge, editor

Published
2004
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430. Low Power Reconfigurable Devices

Author

Gayasen, Aman, Hutchison, David, editor, Kanade, Takeo, editor, Kittler, Josef, editor, Kleinberg, Jon M., editor, Mattern, Friedemann, editor, Mitchell, John C., editor, Naor, Moni, editor, Nierstrasz, Oscar, editor, Pandu Rangan, C., editor, Steffen, Bernhard, editor, Sudan, Madhu, editor, Terzopoulos, Demetri, editor, Tygar, Dough, editor, Vardi, Moshe Y., editor, Weikum, Gerhard, editor, Becker, Jürgen, editor, Platzner, Marco, editor, and Vernalde, Serge, editor

Published
2004
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431. Optimization Algorithms for Dynamic Reconfigurable Embedded Systems

Author

Ahmadinia, Ali, Hutchison, David, editor, Kanade, Takeo, editor, Kittler, Josef, editor, Kleinberg, Jon M., editor, Mattern, Friedemann, editor, Mitchell, John C., editor, Naor, Moni, editor, Nierstrasz, Oscar, editor, Pandu Rangan, C., editor, Steffen, Bernhard, editor, Sudan, Madhu, editor, Terzopoulos, Demetri, editor, Tygar, Dough, editor, Vardi, Moshe Y., editor, Weikum, Gerhard, editor, Becker, Jürgen, editor, Platzner, Marco, editor, and Vernalde, Serge, editor

Published
2004
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432. System-Level Design Tools Can Provide Low Cost Solutions in FPGAs: TRUE or FALSE?

Author

Dickinson, Mark, Hutchison, David, editor, Kanade, Takeo, editor, Kittler, Josef, editor, Kleinberg, Jon M., editor, Mattern, Friedemann, editor, Mitchell, John C., editor, Naor, Moni, editor, Nierstrasz, Oscar, editor, Pandu Rangan, C., editor, Steffen, Bernhard, editor, Sudan, Madhu, editor, Terzopoulos, Demetri, editor, Tygar, Dough, editor, Vardi, Moshe Y., editor, Weikum, Gerhard, editor, Becker, Jürgen, editor, Platzner, Marco, editor, and Vernalde, Serge, editor

Published
2004
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433. FPGAs and the Era of Field Programmability

Author

Roelandts, Wim, Hutchison, David, editor, Kanade, Takeo, editor, Kittler, Josef, editor, Kleinberg, Jon M., editor, Mattern, Friedemann, editor, Mitchell, John C., editor, Naor, Moni, editor, Nierstrasz, Oscar, editor, Pandu Rangan, C., editor, Steffen, Bernhard, editor, Sudan, Madhu, editor, Terzopoulos, Demetri, editor, Tygar, Dough, editor, Vardi, Moshe Y., editor, Weikum, Gerhard, editor, Becker, Jürgen, editor, Platzner, Marco, editor, and Vernalde, Serge, editor

Published
2004
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434. Text Analytics on Reconfigurable Platforms

Author

Polig, Raphael, Stechele, Walter (Prof. Dr.), and Platzner, Marco (Prof. Dr.)

Subjects
Ingenieurwissenschaften, text analytics, information extraction, fpga, reconfigurable, nlp, acceleratio, text analyse, informationsextraktion, fpga, rekonfigurierbar, beschleunigung, ddc:620
Abstract

Extracting information from unstructured text data is an important and compute intensive task. To cope with the ever growing amount of data, an accelerator architecture and compiler for text analytics is presented, leveraging reconfigurable hardware. It is coherently integrated into an enterprise server system allowing end-to-end acceleration of text analytics queries. Results show, that queries can be executed orders of magnitude faster and more energy efficient than on a general purpose processor. Informationen aus unstrukturierten Textdaten zu extrahieren ist eine wichtige Aufgabe moderner IT Systeme. Um mit der immer wachsenden Menge an Daten Schritt zu halten, wir eine Beschleuniger Architektur und ein Compiler für Text Analyse präsentiert, welche rekonfigurierbare Hardware nutzt. Der Beschleuniger ist kohärent in ein Server System integriert, um eine Ende-zu-Ende Beschleunigung von Text Analyse Abfragen zu ermöglichen. Im Vergleich zu einem konventionellen Prozessor, können die Abfragen um ein Vielfaches schneller und energieeffizienter ausgeführt werden.

Published
2015

435. Dynamic Protocol Stacks

Author

Trammell-Keller, Ariane, Plattner, Bernhard, and Platzner, Marco

Subjects
NETWORK PROTOCOLS + COMMUNICATION PROTOCOLS (COMPUTER SYSTEMS), Data processing, computer science, DATA SECURITY + DATA PROTECTION (OPERATING SYSTEMS), DATA COMMUNICATIONS (COMPUTER SYSTEMS), DATENKOMMUNIKATION (COMPUTERSYSTEME), NETZWERKPROTOKOLLE + KOMMUNIKATIONSPROTOKOLLE (COMPUTERSYSTEME), DATENSICHERHEIT + DATENSCHUTZ (BETRIEBSSYSTEME), ddc:004
Abstract

TIK-Schriftenreihe, 149

Published
2014

436. Hardware Virtualization on a Coarse-Grained Reconfigurable Processor

Author

Plessl, Christian, Thiele, Lothar, Platzner, Marco, and Cheung, Peter

Subjects
Data processing, computer science, SIMULATION (HARDWARE), PROGRAMMABLE LOGIC DEVICES, PLD (COMPUTER SYSTEMS), PROGRAMMIERBARE LOGISCHE ELEMENTE (COMPUTERSYSTEME), ddc:004
Abstract

TIK-Schriftenreihe, 84, ISBN:3-8322-5561-3, ISBN:978-3-8322-5561-9

Published
2006
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437. Operating System Design for Partiallly Reconfigurable Logic Devices

Author

Walder, Herbert, Thiele, Lothar, and Platzner, Marco

Subjects
Data processing, computer science, PROGRAMMABLE LOGIC DEVICES, PLD (COMPUTER SYSTEMS), PROGRAMMIERBARE LOGISCHE ELEMENTE (COMPUTERSYSTEME), BETRIEBSSYSTEME, ddc:004, OPERATING SYSTEMS
Abstract

TIK-Schriftenreihe, 68/2 (2)

Published
2005

438. Architectural trade-offs in dynamically reconfigurable processors

Author

Enzler, Rolf, Platzner, Marco, and Tröster, Gerhard

Subjects
Data processing, computer science, PROZESSORARCHITEKTUREN + RECHNERARCHITEKTUREN (COMPUTERSYSTEME), CONTROL STRUCTURES + MICROPROGRAMMING (HARDWARE), STEUERSTRUKTUREN + MIKROPROGRAMMIERUNG (HARDWARE), PROCESSOR ARCHITECTURES + COMPUTER ARCHITECTURES (COMPUTER SYSTEMS), ddc:004
Published
2004
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439. Towards robust HD EMG pattern recognition: reducing electrode displacement effect using structural similarity.

Author

Boschmann A and Platzner M

Subjects
Adult, Algorithms, Electrodes, Electromyography methods, Forearm physiology, Humans, Male, Muscle, Skeletal physiology, Pattern Recognition, Automated, Signal Processing, Computer-Assisted
Abstract

Even small changes of electrode recording sites after training a classifier heavily influence robustness and usability of traditional pattern recognition-based myoelectric control schemes. This effect occurs during donning and doffing of the prosthesis or when changing the arm position and generally leads to a significant decrease of classification accuracy. On the other hand, image representations taken from high density electromyographic (EMG) signals offer high spatial resolution and only seem to change slightly during electrode shift, preserving most structural information. In this paper, we present a simple one-against-one nearest neighbor classifier based on the Structural Similarity Index (SSIM). SSIM quantifies visual similarity of two images based on decomposition into three components: luminance, contrast and structure. Our experimental results indicate that an SSIM-based classifier can outperform an LDA-based classifier using structural information taken from high density EMG signals during simulated electrode shift.

Published
2014
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440. Improving transient state myoelectric signal recognition in hand movement classification using gyroscopes.

Author

Boschmann A, Nofen B, and Platzner M

Subjects
Acceleration, Activities of Daily Living, Adult, Electrodes, Electromyography, Extremities, Female, Humans, Male, Pattern Recognition, Automated, Reproducibility of Results, Wrist physiology, Artificial Limbs, Hand physiology, Movement physiology, Signal Processing, Computer-Assisted
Abstract

Pattern recognition of myoelectric signals in upper-limb prosthesis control has been subject to intense research for several years. However, few systems have yet been successfully clinically implemented. One possible explanation for this discrepancy is that published reports mostly focus on classification accuracy of myoelectric signals recorded under laboratory conditions as the metric for the system's performance. These data are usually acquired only during the static state of the contraction in a fixed seated position. This supports the test subject in performing repeatable contractions throughout the experiment and generally results in an unrealistically high classification accuracy. In clinical testing however, subjects have to perform various activities of daily living, causing the limb to move in different positions. These variations in limb positions can significantly decrease robustness and usability of myoelectric control systems. Recent reports have shown that the so-called limb position effect can be resolved for the static state of the signal by adding accelerometer data to the feature vector. Including data from the transient state of the signals for classifier training generally significantly increases the classification error so it is mostly not considered in published reports. In this paper, we investigate the classification accuracy of transient EMG data, taking into account the limb position effect. We demonstrate that a classifier trained with features from EMG, accelerometer and gyroscope outperforms classifiers using only EMG or EMG and accelerometer data when classifying transient EMG data.

Published
2013
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441. Reducing classification accuracy degradation of pattern recognition based myoelectric control caused by electrode shift using a high density electrode array.

Author

Boschmann A and Platzner M

Subjects
Adult, Algorithms, Feedback, Physiological physiology, Humans, Reproducibility of Results, Sensitivity and Specificity, Artifacts, Electrodes, Electromyography instrumentation, Electromyography methods, Muscle Contraction physiology, Muscle, Skeletal physiology, Pattern Recognition, Automated methods
Abstract

The robustness and usability of pattern recognition based myoelectric control systems degrade significantly if the sensors are displaced during usage. This effect inevitably occurs during donning, doffing or using an upper-limb prosthesis over a longer period of time. Electrode shift has been previously studied but remains an unsolved problem. In this study we investigate if increasing the number of electrode channels and recording locations can improve the degraded classification accuracy caused by electrode shift. In our experiment we use a 96 channel high density electrode array to distinguish 11 different hand and wrist movements. Our results show that for electrode shifts up to 1 cm an array of about 32 sensors in combination with state-of-the-art pattern recognition algorithms is sufficient to compensate the electrode displacement effect.

Published
2012
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442. Fluctuating emg signals: investigating long-term effects of pattern matching algorithms.

Author

Kaufmann P, Englehart K, and Platzner M

Subjects
Humans, Algorithms, Electromyography methods, Pattern Recognition, Automated methods
Abstract

In this paper, we investigate the behavior of state-of-the-art pattern matching algorithms when applied to electromyographic data recorded during 21 days. To this end, we compare the five classification techniques k-nearest-neighbor, linear discriminant analysis, decision trees, artificial neural networks and support vector machines. We provide all classifiers with features extracted from electromyographic signals taken from forearm muscle contractions, and try to recognize ten different hand movements. The major result of our investigation is that the classification accuracy of initially trained pattern matching algorithms might degrade on subsequent data indicating variations in the electromyographic signals over time.

Published
2010
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