Search

This paper proposed a dead-time compensation method with fractional-order proportional integral (FOPI) error voltage control. The disturbance voltages caused by the power devices’ dead time and non-ideal switching characteristics are compensated for with the FOPI controller and fed to the reference voltage. In this paper, the actual error voltage is calculated based on the model and actual voltage of the permanent magnet synchronous motor. Considering the parameter error of the permanent magnet synchronous motor and the voltage error caused by the dead-time effect, a FOPI controller is used to calculate the compensation voltage. An improved particle swarm optimization (PSO) algorithm is utilized to design the parameters of the FOPI controller in order to eliminate the dead-time effect, and the optimal fitness function is designed. Compared with other optimization algorithms, the improved PSO algorithm can achieve faster convergence speed in the error voltage controller parameter design. The proposed dead-time compensation method can improve the performance of the current response and eliminate the dead-time effect. This method also eliminates all harmonic disturbances and has a good suppression effect on high-frequency harmonics. The simulation and experimental results show that the dead-time compensation method using optimal FOPI error voltage control makes the current ripple smaller and the response speed faster than that of the traditional optimal integer-order PI control, thus demonstrating the effectiveness and advantages of the proposed method.

Accurate current polarity detection is a major issue for successful compensation of dead-time distortion in pulse-width-modulated (PWM) voltage source inverter. The present study is concerned with the concept of shift in current-zero-crossing due to dead-time distortion compensation that results in error in current polarity detection and thus causes a problem with regard to the successful continuation of compensation. The phenomenon is analysed in detail, along with its dependence on different factors. The proposed concept is validated in digital simulation and also through experimental verification. The study also recommends the possible correction to be incorporated in view of such zero-crossing shift for achieving proper compensation, especially in case of current-sensor-less compensation techniques.

This research analyzes the asymmetric control strategies in multilevel inverters, including asymmetric techniques in space vector modulation of power converters. Modulation parameters such as reference voltage vector (Vref), switching time, and duty cycle are derived in the three-dimensional spatial vector geometry formulation. Asymmetric space vector pulse width modulation (SVPWM) is unique in specifying modulation parameters, has unequal tetrahedron patterns, accompanied by application examples for the upper and lower sector pairs of a tetrahedron. The combination of the switch in the form of an inclined cylinder produces twelve pairs of asymmetric tetrahedrons where the voltage vector positions are in the other twenty-four tetrahedrons. The calculation shows processing dead-time in switching, which is used for current compensation in three-phase power converters.

This article proposes a three-stage dead-time adjustment scheme for the leading-leg and lagging-leg switches of phase-shift full-bridge converter (PSFBC) according to the load conditions to enhance the conversion efficiencies at light loads. This article also investigates an iterative rigorous loss calculation for light loads under dead-time adjustment. The proposed iterative calculation can be used to modify the duty ratio of the transition region and estimate the operating currents more accurately; therefore, the losses of a PSFBC at light loads and under the dead-time adjustments can be effectively estimated. A PSFBC prototype with an input voltage of 380 V, an output voltage of 48 V, and a rated output power of 480 W is designed and implemented in this article. Experimental results show that comparing with the PSFBC without the dead-time adjustment and with the conventional dead-time adjustment, the conversion efficiency enhancements of 12.13% and 5.97% can be achieved by the proposed three-stage dead-time adjustment scheme at about 5% load condition, respectively. For a small-scale data center with 100 designed PSFBCs, simulated results indicate that about 3.21 MWh of electricity and 1.03 tons of carbon dioxide emission can be saved and reduced per year, respectively, by the proposed dead-time adjustment scheme.

Industrial processes of unstable/integrating nature having a dead time and inverse response characteristics are challenging to control. For controlling such processes, double-loop control structures have proven to be more efficient than conventional PID controllers in a unity feedback configuration. Therefore, a new design method to obtain PI-PD controller settings is proposed for a set of unstable/integrating plant models with dead time and inverse response. The stabilizing proportional–derivative (PD) controller is designed using maximum sensitivity considerations and Routh–Hurwitz stability criteria. The PI controller settings are obtained by comparing the first and second derivatives of expected and actual closed-loop transfer functions about the origin of the s-plane. Adjustable parameters of the inner and outer loops are selected such that the desired value of maximum sensitivity is achieved. Simulation studies are conducted on some benchmark linear and nonlinear plant models used in literature. Robustness of the proposed design is analyzed with perturbed plant models, and quantitative performance measures are computed. It is found that the proposed design yields enhanced and robust closed-loop response than some contemporary works.

A current-mode four-phase synchronous buck converter with a dynamic dead-time control (DDTC) method is presented in this work. A brief analysis of the multiphase buck converter power efficiency in both continuous conduction mode (CCM) and discontinuous conduction mode (DCM) is performed to provide design guidelines for minimizing power losses. In synchronous converters, the power efficiency can always be improved by optimizing the dead-time. Therefore, a gate driver with DDTC is designed to optimize the dead-time in every switching cycle, thereby improving power efficiency particularly under heavy load conditions. The proposed buck converter has the ability to deliver a maximum load current of 6.0 A at a typical output voltage of 1.2 V from a power supply of 3.0 V. A power efficiency improvement of over 1.0% is achieved when the load current is over 2.0 A, and an improvement of about 2.4% is obtained at a load current of 4.0 A. A peak power efficiency of 92.8% is measured at an output voltage of 1.8 V.

A dynamic model of surface-mounted permanent magnet synchronous motors (SPMSMs) is constructed to include the dead-time disturbance voltage of the voltage-source inverter and SPMSM parameter uncertainty. The constructed model reveals that both the disturbance voltage and the parameter uncertainty degrade the SPMSM stator current control performance. Based on this notion, a nonlinear damping compensator is designed to simultaneously compensate for the dead-time disturbance voltage and parameter uncertainty in a unified structure. The designed compensator is advantageous because it is implemented with only the static feedback of available system variables with a low computational load, which enables the compensation signal to be calculated within one sampling period without requiring a specific calculation cycle. A rigorous analysis using a Lyapunov function shows that the designed compensator achieves the global exponential ultimate boundedness of the stator current errors with arbitrarily small bounds and fast decay rates in the presence of both the dead-time disturbance voltage and parameter uncertainty. The designed compensator performance is demonstrated by performing experiments using a 750-W laboratory SPMSM drive and comparing the experimental results with those of a conventional proportional-integral controller with a feedforward compensator.

In the three-phase inverters, high common-mode voltage (CMV) will produce some serious negative effects. Compared with the conventional pulse width modulation, the use of reverse carrier scheme (RCS) is a simple way to reduce the CMV peaks to one third of the original peaks in theory. However, in practice, some CMV spikes will appear in the inverter when using the RCS. The CMV spikes are caused by the switching dead-time effect. This article presents an improved RCS, which is called the scheme of symmetrical rotation reverse carriers (SRRCs). In this scheme, three-phase carriers are reversed periodically in turn. This ensures that only one phase carrier is reversed at any time, which eliminates the generation mechanism of the CMV spikes. The SRRC scheme is not only suitable for the three-phase inverters with a fixed-frequency carrier but also suitable for the inverters with the carrier frequency modulation. The feasibility and effectiveness of the proposed SRRC scheme are verified by the simulations and experimental results in a three-phase inverter.