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Implementation of design functions by available devices is a key step in any design activity. This paper proposes an algorithm for automatically achieving a mapping between the functions and the devices. As an integral part of the approach, a novel scheme for modeling the device and the function behaviors is proposed, for reducing the complexity of the mapping process.

Design of embedded systems has brought the discipline of hardware software codesign into focus. A major task of such codesign activity is partitioning the functions into hardware and software implementation sets. In this paper, we propose an algorithm which performs such partitioning and also allocates the functions to modules. The task has been formulated as a consistent labeling problem. To deal with the combinatorial nature of the problem, a number of heuristics have been proposed and their relative performances have been evaluated experimentally. The algorithm has been applied to solve several design problems.

Background Most patients with head and neck squamous cell carcinoma are older and may have coexistent or comorbid diseases. Objectives To determine the prognostic impact of individual comorbid conditions in patients with head and neck cancer, to combine the individual comorbid conditions to form a new a head and neck–specific comorbidity instrument, and to compare it with the Modified Kaplan-Feinstein Index to determine if the new disease-specific instrument offers any improvement in survival prediction over a general comorbidity index. Design Retrospective review of medical records. Population The study population comprised 1153 patients with biopsy-proven, newly diagnosed squamous cell carcinoma of the oral cavity, oropharynx, or larynx. Results Seven comorbid conditions (congestive heart disease, cardiac arrhythmia, peripheral vascular disease, pulmonary disease, renal disease, cancer controlled, and cancer uncontrolled) were significantly related to survival. These comorbid conditions were assigned integer weights to reflect their relative prognostic importance and combined to create the new Washington University Head and Neck Comorbidity Index (WUHNCI). Survival was significantly related to levels of comorbidity severity as defined by the WUHNCI. The WUHNCI predicted survival better than the Modified Kaplan-Feinstein Index despite containing far fewer ailments. Conclusions Comorbidity is an important feature of the patient with head and neck cancer. The WUHNCI can be used for retrospective review or prospective outcomes research.

An electron can bind to positronium (Ps) to form positronium negativeion (Ps −), provided that the two electron are in a singlet spin state. As a result, there has been a revival of interest to investigate polyelectron systems. However, this system and its charge conjugate counterpart consisting of two positrons and one electron was predicted to be bound in1946 by Wheeler1. No other bound state of Ps − exists, like that of H −, but the system does possess several autodetaching states in the electron -positronium continuum. Bhatia and Drachman2, Ho3, Petelenz and Smith4 and Frolov and Yeremin5 have predicted binding energies using different variational techniques. Their results are consistent with the measured data obtained by Mills6. The energies and widths of the resonances in the electron - positronium continuum have been studied by different workers. Ho7 has employed the complex coordinate rotation method to investigate these, whereas, Ward et al 8 has employed Kohn variational model. An adiabatic potential model involving hyperspherical coordinates was used by Botero and Greene9. We would also like to add that the positions and widths ofresonances due to the autodetaching states of Ps − differ amongst themselves. Although every model employed is theoretically sound within its limitations. These indicate that this three particle system is very sensitive to the theoretical model.

Arsenic is widely distributed in nature in air, water and soil in the form of either metalloids or chemical compounds. It is used commercially, as pesticide, wood preservative, in the manufacture of glass, paper and semiconductors. Epidemiological and clinical studies indicate that arsenic is a paradoxical human carcinogen that does not easily induce cancer in animal models. It is one of the toxic compounds known in the environment. Intermittent incidents of arsenic contamination in ground water have been reported from several parts of the world. Arsenic containing drinking water has been associated with a variety of skin and internal organ cancers. The wide human exposure to this compound through drinking water throughout the world causes great concern for human health. In the present review, we have attempted to evaluate and update the mutagenic and genotoxic effects of arsenic and its compounds based on available literature.

Scattering of orthopositronium off helium target has been investigated using close-coupling method in the energy range 0--110 eV. Two basis sets, (a) $\mathrm{Ps}(1s)+\mathrm{He}{(1s}^{2},{1s2}^{1}s,{1s2}^{1}p)$ and (b) $\mathrm{Ps}(1s,2p)+\mathrm{He}{(1s}^{2},{1s2}^{1}s,{1s2}^{1}p),$ have been employed to find the scattering parameters. Low-order phase shifts, scattering length, and elastic and excitation cross section up to $n=2$ are reported using close-coupling approximation. Total cross section is also given by adding other partial cross section and compared with available measured data and existing theoretical predictions. Our total cross section at zero energy is very close to the theoretical prediction of Drachman and Houston [J. Phys B 3, 1657 (1970)] and measured data of Canter et al. [Phys. Rev. A 12, 375 (1975)]. Present total cross section is in qualitative agreement with measured data of the University College London group in the energy range considered. In particular, present predictions are in good agreement with the UCL group in the energy range 20--30 eV. It has been found that elastic cross section is dramatically reduced, at zero or near zero energies, with the inclusion of target excitation in the expansion scheme. Moreover, ionization cross section of the Ps atom is found to be a major contributor to the total cross section above the ionization threshold.

Scattering of a Ps atom off a He target has been investigated in the framework of the close-coupling approximation using two basis sets: (a) $\mathrm{Ps}(1s)+\mathrm{He}{(1s}^{2}{,1s2}^{1}{s,1s2}^{1}p)$ and (b) $\mathrm{Ps}(1s,2p)+\mathrm{He}{(1s}^{2}{,1s2}^{1}{s,1s2}^{1}p).$ Target inelastic channels reduce the elastic cross sections appreciably near zero energy. The present results are in good agreement with the theoretical prediction of Drachman and Houston and the measured data of Canter, McNutt, and Roellig and Coleman et al. and are also in good agreement with the measured data of the UCL group from 15--20 eV.

Code optimization for digital signal processors (DSPs) has been identified as an important new topic in system-level design of embedded systems. Both DSP processors and algorithms show special characteristics usually not found in general-purpose computing. Since real-time constraints imposed on DSP algorithms demand for very high quality machine code, high-level language compilers for DSPs should take these characteristics into account. One important characteristic of DSP algorithms is the iterative pattern of references to array elements within loops. DSPs support efficient address computations for such array accesses by means of dedicated address generation units (AGUs). In this paper, we present a heuristic code optimization technique which, given an AGU with a fixed number of address registers, minimizes the number of instructions needed for address computations in loops.

p-wave electron–hydrogen scattering has been investigated in a Debye plasma environment employing a close-coupling approximation. Three different basis sets have been used to estimate the resonance parameters. Plasma screening has been taken into account via the Debye–Huckel model potential. Auto-detaching 1, 3Po resonances of the hydrogen negative ion below the n = 2 threshold have been studied under various plasma conditions. The present predicted resonance energies and widths are in close agreement with those of Kar and Ho (2006 Few Body Syst. 40 13).

Electron-hydrogen scattering in Debye plasma environments has been investigated using the close-coupling approximation. Three different models, viz. 3-state CCA, 6-state CCA, and 9-state CCA, have been employed in the present investigation. The positions and respective widths of the 2s2 1Se resonance of hydrogen negative ion have been investigated for various plasma conditions. The inter-particle interactions have been taken to be of Debye-Huckel type. The present results are in close agreement with those of Kar and Ho (New J. Phys., 7 (2005) 141).

In this paper, we discuss the nonlinear computational power provided by dendrites in biological and artificial neurons. We start by briefly presenting biological evidence about the type of dendritic nonlinearities, respective plasticity rules and their effect on biological learning as assessed by computational models. Four major computational implications are identified as improved expressivity, more efficient use of resources, utilizing internal learning signals, and enabling continual learning. We then discuss examples of how dendritic computations have been used to solve real-world classification problems with performance reported on well known data sets used in machine learning. The works are categorized according to the three primary methods of plasticity used—structural plasticity, weight plasticity, or plasticity of synaptic delays. Finally, we show the recent trend of confluence between concepts of deep learning and dendritic computations and highlight some future research directions.

In this paper a second order log-domain bandpass filter using multiple input translinear elements (MITEs) operating at a 3V supply. We enhance the capabilities of the filter by utilizing programmable MITE structures as well as programmable current sources, which are covered in this paper. The synthesized bandpass filter is implemented and fabricated using these programmable translinear devices (MITEs). Experimental results are shown from circuit fabricated on a 0.5/spl mu/m nwell CMOS process available through MOSIS.

This paper describes a sampled analog architecture, for computing DCT or DST, using switched capacitor principle with capacitance switching. The input sample stream is applied to an array of capacitors and multiplied by all the DCT/DST coefficients concurrently using capacitor ratios. These capacitors are switched properly with the help of a switching matrix, to realize switched capacitor integrators for performing necessary addition/subtraction. Proposed architecture simple, regular with lower gate count may be used for online computations.

The concept of learning digital hardware is presented here. A proof of concept of a circuit that can arbitrarily control the current, and thus the switching speed and power consumption, of a digital circuit is given. This control of current is directly tuned by the feedback from the digital circuit itself, thus a learning digital computer. An argument for a completely new paradigm in digital computing follows whereby an entire system of learning digital circuits is proposed.

This paper presents application of Banditron - an online reinforcement learning algorithm (RL) in a discrete state intra-cortical Brain Machine Interface (iBMI) setting. We have analyzed two datasets from non-human primates (NHPs) - NHP A and NHP B each performing a 4-option discrete control task over a total of 8 days. Results show average improvements of ≈ 15%, 6% in NHP A and 15%, 21% in NHP B over state of the art algorithms - Hebbian Reinforcement Learning (HRL) and Attention Gated Reinforcement Learning (AGREL) respectively. Apart from yielding a superior decoding performance, Banditron is also the most computationally friendly as it requires two orders of magnitude less multiply-and-accumulate operations than HRL and AGREL. Furthermore, Banditron provides average improvements of at least 40%, 15% in NHPs A, B respectively compared to popularly employed supervised methods - LDA, SVM across test days. These results pave the way towards an alternate paradigm of temporally robust hardware friendly reinforcement learning based iBMIs.

BackgroundCytogenetic biomarkers are essential for assessing environmental exposure, and reflect adverse human health effects such as cellular damage. Arsenic is a potential clastogen and aneugen. In general, the majority of the studies on clastogenic effects of arsenic are based on frequency of micronuclei (MN) study in peripheral lymphocytes, urothelial and oral epithelial cells. To find out the most suitable cell type, here, we compared cytogenetic damage through MN assay in (a) various populations exposed to arsenic through drinking water retrieved from literature review, as also (b) arsenic-induced Bowen's patients from our own survey.ResultsFor literature review, we have searched the Pubmed database for English language journal articles using the following keywords: "arsenic", "micronuclei", "drinking water", and "human" in various combinations. We have selected 13 studies consistent with our inclusion criteria that measured micronuclei in either one or more of the above-mentioned three cell types, in human samples. Compared to urothelial and buccal mucosa cells, the median effect sizes measured by the difference between people with exposed and unexposed, lymphocyte based MN counts were found to be stronger. This general pattern pooled from 10 studies was consistent with our own set of three earlier studies. MN counts were also found to be stronger for lymphocytes even in arsenic-induced Bowen's patients (cases) compared to control individuals having arsenic-induced non-cancerous skin lesions.ConclusionOverall, it can be concluded that MN in lymphocytes may be superior to other epithelial cells for studying arsenic-induced cytogenetic damage.

There has been a lack of progress in developing spiking neuron models for pattern classification, which can achieve similar performance as state-of-the-art. To pursue this goal of creating powerful spike-based classifiers, the role of dendrites in neuronal information processing is considered. The neurobiological evidence for dendritic processing has been established in the last few years by neuroscientists across the globe. However, computational models of spiking neurons in machine learning systems have not utilized this mechanism yet. Our work attempts to bridge this gap and explore the possible computational benefits of passive delay and active ionic dendritic mechanisms. A spike-based model for pattern classification is presented which employs neurons with functionally distinct multicompartment dendritic branches. In this model, synaptic integration involves location-dependent processing of inputs on each dendritic compartment, followed by nonlinear processing of the total synaptic input on a dendrite and finally linear integration of the total dendritic output at the soma. This gives the neuron a capacity to perform a large number of input-output mappings. Firstly, a spiking neuron model is developed based on modifying delays associated with the spikes arriving at an afferent. The application of this model is demonstrated on memorizing spatio-temporal patterns by updating only a few delays corresponding to the most synchronous part of a spike pattern. This model explores the time-based computing approach to design a novel learning algorithm which provides an alternative to the traditional weight-based learning and offers the advantage of simpler hardware implementation without multipliers or digital-analog converters (DACs). The classification accuracy of the system with a load (number of patterns relative to the number of synapses) of up to 2 was shown to be about 80−100%. In our pursuit of achieving improved performance and a hardware-friendly learning algorithm, a model is further proposed which consists of nonlinear dendrites and is inspired by the structural plasticity involving correlation-based grouping of synaptic contacts onto dendrites. The model utilizes sparse synaptic connectivity, where each synapse takes a binary value, and learns the optimal input connections of a neuron. The modification of connectivity matrix renders the model suitable for implementation in address-event representation (AER) based neuromorphic systems. A modified margin-based model is also presented, which is shown to result in significant improvement in generalization performance. This performance is found to be comparable with that of standard methods like support vector machine (SVM) and extreme learning machine (ELM) on benchmark data sets and moreover, it is achieved by utilizing 10−50% less number of low resolution synapses compared to these algorithms. The structural learning rule for nonlinear dendrites is also extended to perform multiclass classification and demonstrate the application of this multiclass model on the classification of handwritten digits from the MNIST dataset. For this application, our model is shown to attain comparable performance (≈ 2% more error) with other spike-based classifiers while using much less synaptic resources, up to 10% of that used by other methods. Two approaches are used to train the model: 1) a branch-specific spike-time-based structural learning rule and; 2) a rate-based version of this rule to reduce training time. The correspondence between these two forms of learning is also established. Enhancements are proposed in this model by developing an adaptive structural scheme to learn the number of dendrites by progressively adding dendrites to the network and simultaneously forming synaptic connections on these dendrites, thereby allocating synaptic resources as per the complexity of the given problem. The model is further enhanced by using an ensemble method which combines several dendritic classifiers to achieve enhanced generalization over individual classifiers. The performance of these enhanced learning algorithms is again demonstrated on the classification of MNIST data, which shows that an ensemble model created with adaptively learned classifiers can attain accuracy of 96.2% which is at par with the best performance reported for any spiking neural network. Moreover, the ensemble has the advantage of using much less number of synapses, about 20% of other spike algorithms. Finally, the performance benefits of combined learning of delays associated with afferents and connection pattern of these afferents are investigated. This novel learning algorithm is used by a spiking neuron model comprising nonlinear dendrites with multiple delay compartments on each dendrite to classify spatio-temporal patterns. The multicompartment dendritic neurons are different from our earlier model using lumped dendritic nonlinearity in which all synaptic inputs on a dendrite were lumped together in one compartment. The combined learning rule inspired by the Tempotron rule uses correlation computations to form synaptic connections on specific delay compartments of the nonlinear dendrites. Our neurobiologically realistic multicompartment dendritic model achieves enhanced classification accuracy, which is about 5% higher than that attained by lumped dendrite scheme. Moreover, the Tempotron rule with weights quantized to 4-bits attains about 5% less accuracy than our multicompartment model, which uses binary weights, thereby rendering our proposed learning scheme more appealing for hardware implementation. DOCTOR OF PHILOSOPHY (EEE)

Large-scale spiking neural networks (SNN) are typically implemented on the chip by using mixed analog-digital circuits. While the models of the network components (neurons, synapses, and dendrites) are implemented by analog VLSI techniques, the connectivity information of the network is stored in an on-chip digital memory. Since the connectivity information is virtual, the user has full flexibility in reconfiguring the network. When a new task is encountered, a software model of the network is trained in computer and the trained weights are downloaded to the digital memory. Hence, the analog part works in conjunction with the digital part to form a properly weighted SNN suitable for the task at hand. However, very few hardware systems emulating SNN have been reported to solve real-world pattern recognition tasks with performance comparable to their software counterparts. A major challenge in obtaining a classification accuracy comparable to a software implementation of a system on a computer is that statistical variations in VLSI devices diminish the accuracy of synaptic weights. Most of the current neuromorphic systems require high-resolution synaptic weights and hence are affected by this problem. In this thesis, for enhanced stability to mismatch and efficient hardware implementation we have considered neurons with binary synapses for recognition of spatiotemporal spike trains. To compensate for the reduced computational power provided by binary synapses we look into more bio-physical models of neurons. Inspired by the nonlinear properties of dendrites in biological neurons, the proposed networks incorporate neurons having multiple dendrites with a lumped nonlinearity (two compartment model). We have shown that such a neuron with nonlinear dendrites (NNLD) has higher memory capacity than their linear counterpart and networks employing them provide state-of-the-art performance. Since binary synapses are considered, learning happens through formation and elimination of connections between the inputs and the dendritic branches to modify the structure or morphology of the network. Hence, the learning involves network rewiring (NRW) of the spiking neural network similar to structural plasticity observed in its biological counterparts. However, for structural plasticity based learning rules high dimensional sparse inputs are required. A popular way to map any input pattern into a high dimensional space enforcing sparse coding is by using non-overlapping binary valued receptive fields. But this method, though suitable for rate coded inputs, cannot be applied to spike-coded inputs. To overcome this issue, taking inspiration from Liquid State Machine (LSM), a popular model for reservoir computing, we have used a spiking neural network reservoir to convert the spike train inputs to a high dimensional sparse spatiotemporal spike encoding. Subsequently, we have used this high dimensional spike data to train our NNLD network having binary synapses through the proposed learning rule. We have shown that compared to a single perceptron using analog weights, this architecture for the readout can attain, even by using the same number of binary valued synapses, up to 3.3 times less error for a two-class spike train classification problem and 2.4 times less error for an input rate approximation task. Even with 60 times larger synapses, a group of 60 parallel perceptrons cannot attain the performance of the proposed dendritically enhanced architecture. Furthermore, we have shown that due to the use of binary synapses, our proposed method is more robust against statistical variations. We have also looked into the on-chip implementation of NNLD and NRW learning rule for online training of the proposed readout. This is the first contribution of this thesis. The second contribution arises from increasing memory capacity of NNLD-based networks in recognizing high dimensional spike trains. A morphological learning algorithm inspired by the 'Tempotron', i.e., a recently proposed temporal learning algorithm is presented in this thesis. Unlike 'Tempotron', the proposed learning rule uses a technique to automatically adapt the neuronal ring threshold during training. Experimental results indicate that our NNLD with binary or 1-bit synapses can obtain similar accuracy as a traditional Tempotron with 4-bit synapses in classifying single spike random latency and pair-wise synchrony patterns. We have also presented results of applying this rule to real life spike classification problems from the field of tactile sensing. The two earlier contributions are supervised learning rules for training NNLD with binary synapses. The third contribution of this thesis is to provide an unsupervised learning rule for training NNLD. We have proposed a novel Winner-Take-All (WTA) architecture employing an array of NNLDs with binary synapses and an online unsupervised structural plasticity rule for training it. The proposed unsupervised learning rule is inspired by spike timing dependent plasticity (STDP) but differs for each dendrite based on its activation level. It trains the WTA network through formation and elimination of connections between inputs and synapses. To demonstrate the performance of the proposed network and learning rule, we have employed it to solve two, four and six class classification of random Poisson spike time inputs. The results indicate that by proper tuning of the inhibitory time constant of the WTA, a trade-off between specificity and sensitivity of the network can be achieved. We use the inhibitory time constant to set the number of subpatterns per pattern we want to detect. We show that while the percentage of successful trials are 92%, 88% and 82% for two, four and six class classification when no pattern subdivisions are made, it increases to 100% when each pattern is subdivided into 5 or 10 subpatterns. However, the former scenario of no pattern subdivision is more jitter resilient than the later ones. Apart from bio-realism and performance, an additional advantage of this method for hardware implementations is that the 'choice' of connectivity can be easily implemented exploiting address event representation (AER) protocols commonly used in current neuromorphic systems where the connection matrix is stored in memory. Also, due to the use of binary synapses, our proposed algorithms are less affected by VLSI mismatch. The algorithms proposed in this thesis can find direct application in classifying spatio-temporal spike patterns arriving from the domain of Brain Machine Interfaces (BMI), Tactile sensors, sensory prosthesis, etc. However, the main contribution of this thesis is that it tends to remove the long-standing bias towards using neural networks with high-resolution weights and weight update based learning rules. This thesis shall trigger the usage of neural networks with binary synapses and connection-based learning rules for solving pattern recognition tasks in hardware. While traditional networks had to incorporate sparsity by using lesser number of neurons, our learning rules inherently form sparse networks by making sparse connections between inputs and dendrites. DOCTOR OF PHILOSOPHY (EEE)

Brain-Machine Interfaces (BMIs) have been developed in the past few decades to establish a bridge between brain and external electronics and computing devices. Driven by an increasing demand in health care industry and the rapid development of complementary metal oxide semiconductor (CMOS) and micro-electro-mechanical systems (MEMS) technology, significant progress has been made in the BMIs that interpret the electrical signals of the brain in order to study the brain functions or to control an actuator. The trend is to develop cortex-implantable miniature devices integrating entire system that are bio-compatible and are able to operate chronically and autonomously. This raises significant challenge to various aspects of systems and circuits design of the BMIs due to limited resource and budget. One promising version of these systems is sensing neural extracellular action potentials with an array of up to 100 or more miniature probes implanted into the cortex. To guarantee the quality of the neural signal recorded by these high impedance electrodes, customized integrated circuits (IC) are developed with multiple amplifiers on the same die, achieving on-site signal recording. Since power consumption is one of the key limiting factors of the implanted system, significant effort has been dedicated to reduce the power consumption of the front-end analog and mixed-signal circuits. However, high channel count also yields high data transmission rate, leading to considerable power consumption in wireless transmission circuits. Methods of on-chip data compression are therefore highly desirable in the implanted system. In this thesis, circuits are presented for sensing and processing the neural signals robustly while dissipating minimal power and reducing data rate for enhancing scalability of the designs. The first contribution is the design of a novel signal folding and reconstruction scheme for neural recording applications that exploits the 1/fn characteristics of the neural signals is proposed to reduce the dynamic range in the front-end circuits. The amplified output is ‘folded’ into a predefined range of voltage by using comparison and reset circuits along with the core amplifier. After this output signal is digitized and transmitted, a reconstruction algorithm is applied in the digital domain to recover the amplified signal from the folded waveform. This scheme enables the use of an analog-to-digital convertor with less number of bits for the same effective dynamic range at final output. It, therefore, reduces the transmission data rate of the recording chip. Both of these features allow power and area saving at the system level. Other advantages of the proposed topology are increased reliability due to the removal of pseudo-resistors, less harmonic distortion and low-voltage operation. An analysis of the reconstruction error introduced by this scheme is presented along with a MATLAB-based behaviour model for signal folding amplifier introduced to provide estimates for reconstruction error. Measurement results from two designs in two different CMOS processes are presented to prove the generality of the proposed scheme in neural recording applications. In-vivo testing results on anaesthetized rat are also conducted to show the capability of the proposed neural amplifier to simultaneously record local filed potential and spike. Another emerging trend of BMIs in recent years is to implement neural stimulator with neural recording circuits to build a brain- machine-brain closed loop in the implanted system. These closed-loop BMIs find vast applications in therapies of neurological disorders, neural prosthesis and neuro-scientific research, where certain action potential in the brain tissue are observed as a response to the neural stimulation delivered. One challenge of building the closed-loop BMIs is to record as much of the action potential waveform as possible in the presence of large artifacts introduced by the neural stimulation. These artifacts, much larger than the action potential, usually cause the saturation of the high-gain neural recording amplifier and create a long blind period of tens of milliseconds during and right after the stimulation, in which action potential cannot be properly recorded. Applying the proposed signal folding and reconstruction scheme mentioned above, a proof-of-concept IC is presented in this thesis, targeting simultaneous neural stimulation and recording. The testing results shows that the signal folding scheme creates a feedback loop that prevents the amplifier from saturation by resetting the amplifier even with artifacts at the input, leading to a reduced recovery time from the interference of the stimulation artifacts. This is the second contribution in this thesis. Signal processing circuits can also be integrated with microelectrode array (MEA) to enable real-time on-chip processing and reduce the data transmission rate as well as the power consumption. In the BMIs used in neural prosthesis, one key component is the motor intention decoder that extracts the subjects’ intention of moving from the neural signals recorded in the motor cortex of the brain. A hardware-friendly motor intention decoding algorithm based on the Extreme Machine Learning (ELM) and its mixed-signal CMOS implementation is presented in this thesis as the final contribution. ELM is a single hidden-layer neural network, in which input weights are randomly assigned and remain unchanged in training. Only output weights are trained in a one-time manner, leading to a very fast training progress and reduced computing efforts. This neural network is realized in a mixed-signal architecture, in which random weights are implemented by exploiting transistor random mismatch in the CMOS process, while output weights are implemented in digital domain for robustness and programmability. The results of decoding neural signal data (recorded in previously conducted animal experiments) with the proposed algorithm are shown and analyzed. In conclusion, BMIs with multiple electrodes implanted in the cortex have experienced fast development in recent years. Next generation BMI will possibly integrate up to one thousand micro-electrodes with circuit components including neural recording, signal processing as well as sensory feedback, leading to a better performance and possibly more applications. In the BMI for neural prosthesis, for instance, better control accuracy and robustness can be obtained with more intra-cortical recording and feedback. Types of prosthesis can also be extended from, for instance, upper limb to bipedal. In this great interdisciplinary endeavor, power consumption and robustness of the electronics system will always be a limiting factor to the practical use of the devices. In this thesis, some problems of the front-end signal amplifying circuit of intra-cortical BMIs have been addressed and low-power solutions have been proposed. Architectural solutions to enhance scalability and reducing transmission data rate by integrating a movement classifier on-chip is also shown for the first time. DOCTOR OF PHILOSOPHY (EEE)

In this thesis, we proposed a novel low power, compact, current-mode spike detector with feature extractor for real-time neural recording systems where neural spikes or action potentials (AP) are of interest. Such a circuit can enable massive compression of data facilitating wireless transmission. This design can generate a high signal-to-noise ratio (SNR) output by approximating the popularly used nonlinear energy operator (NEO) through standard analog blocks. We show that a low pass filter after the NEO can be used for two functions – (i) estimate and cancel low frequency interference and (ii) estimate threshold for spike detection. The circuit is implemented in a 65 nm CMOS process and occupies 200 μm x 150 μm of chip area. Operating from a 0.7 V power supply, it consumes about 30 nW of static power and 7 nW of dynamic power for 100 Hz input spike rate making it the lowest power consuming spike detector reported so far. The feature extractor could be utilized to extract some features from the raw waveform that have enough information to discriminate between different shapes of recorded spike waveforms. The spike sorting was performed by our proposed hardware extreme learning machine system (ELM) which is a low power neuromorphic machine learner that can perform the local processing in smart sensors while dissipating very low power. The proposed circuit utilizes device mismatch prevalent in today's VLSI process to perform a significant part of the computation while a digital back end enables precision in the final output. The particular machine learning algorithm we use is extreme learning machine (ELM). Mismatch in silicon spiking neurons and synapses are used to perform the vector-matrix multiplication that forms the first stage of this classifier and is the most computationally intensive. System simulations and measurement have been conducted to evaluate the dependence of performance (in a classification and a regression task) on analog and digital parameters like weight resolution, maximum spike frequency etc. It is shown that the proposed implementation is more energy efficient as opposed to custom digital implementations for a classification task. In order to verify its function, some real-world bench mark binary classification datesets have been employed in the measurement showing that the performance of our design is comparable with recent publications and software simulations of other machine learning system. This system was implemented in a 0.35 μm CMOS process which can operate from 0.8 V to 3.3 V power supply with a lowest classification energy 0.2 nJ/op, maximum classification speed 564 MMAC/s. DOCTOR OF PHILOSOPHY (EEE)

The proliferation in use of data-intensive statistical models and algorithms have given a push to the brain-inspired computing, commonly known as Neuromorphic computing. With the increased research interest in neuromorphic computing, neuromorphic chip, a dedicated hardware for realizing neural networks (NN), is gaining popularity. However, the challenge is to design an efficient neuromorphic chip in terms of area density, power consumption and scalability, which can incorporate huge number of neurons similar to what is found in the human brain. In this thesis, an automated technique for mapping any feed-forward deep neural network onto the neuromorphic chip is discussed, where mapping refers to the generation of connectivity list based on the interrelation of neurons in adjacent neural network layers and assigning those neurons to specific addresses in neuromorphic core. Furthermore, it acts as a simulation tool for debugging computations performed on the neuromorphic chip during inferencing. Together the configuration becomes Mapping and Debugging (MaD) framework[1]. MaD framework is quite general in usage and can also be used for very popular IBM TrueNorth chip. This paper illustrates the MaD framework in detail, considering some optimizations while mapping. A classification task on MNIST and CIFAR-10 datasets are considered for test case implementation of MaD framework. Master of Science (Green Electronics)

One of the major areas of research by neurobiologists is long term synaptic modification or plasticity of synapses. Synapses are the interconnections between neurons. Each synapse is associated with a weight quantity, which determines the amplitude of output excitatory postsynaptic current (EPSC) pulse from the respective synapse to the interconnected neuron. Neurons on the other hand are the basic computational unit. It integrates all the incoming current pulses from different synapses and fires a spike, if the integration reaches a threshold. Neurons and synapses are the major units of a biological neural network that are typically included in computational models; however, recently there has been an increasing focus on studying the role of astrocytes [1, 2] and may be a part of future large scale models. It is generally believed that the ability to learn and execute difficult tasks in human brain is mediated by synapses. Likewise in artificial spiking neural networks (SNNs), synapses play a major role in the ability to carry out signal processing, classification, computations etc. Basically synapses play a fundamental role in learning through activity dependent modification of their efficacies. The mathematical model under which synapses modify their weights are termed as synaptic plasticity rule. Recently a learning rule known as spike timing dependent plasticity (STDP) that modifies weights based on the timing of presynaptic and postsynaptic spikes become very popular. The most commonly used rule posits weight change based on time difference between one presynaptic spike and one postsynaptic spike and is hence termed doublet STDP (D-STDP). Potentiation occurs when a postsynaptic spike succeeds a presynaptic spike; otherwise depression happens. However, D-STDP could not reproduce results of many biological experiments; a triplet STDP (T-STDP) that considers triplets of spikes as the fundamental unit has been proposed recently to explain these observations. Computationally T-STDP has advantages like replicating rate based plasticity experiments and detecting third order input correlations. As these rules are being proposed by neurobiologists, we as engineers try to implement them in silicon in order to employ them in complex real world applications. We first propose a method to robustly perform doublet STDP rule in a single floating-gate (FG) transistor synapse. The experimental STDP plot of a FG synapse (change in weight against Δt = tpost - tpre) from previous study shows a depression instead of potentiation at some range of positive values of Δt. To ameliorate this STDP graph of a FG synapse, a minimum hardware overhead solution is proposed. The measurement results from a FG synapse fabricated in AMS 0.35 m CMOS process design are presented to justify the claim. Next, we propose a modification to the basic FG synapse to implement a more sophisticated and bio-realistic rule - triplet STDP (T-STDP). Compared to the previous work, here we propose a method to localize the effect of potentiation and depression on a FG synapse. The spike triplet affects the setting of drain voltage–we present a single pulse and a double pulse drain voltage method to obtain the desired dependence of weight on spike timing. We present a mathematical procedure to calculate the parameters of the drain voltage pulse to obtain results matched to the original theoretical T-STDP rule. We also show measurement results from a FG synapse fabricated in TSMC 0.35 um CMOS process in comparison with the biological experimental observations for (1) original doublet protocol, (2) two protocols of spike triplets, (3) frequency effects of pairing protocol, (4) quadruplet experiments and (5) replication of BCM rule. Possible VLSI implementation of drain voltage waveform generator circuits are also presented with simulation results. Finally, we showcase the computational advantages of T-STDP model apart from the experimental advantages compared to D-STDP model i.e. detecting third order input correlations and faster convergence of synaptic weights. A classic STDP experiment is chosen and implemented using both D-STDP model and T-STDP model in MATLAB. MATLAB simulations prove the faster convergence of synaptic weights in the case of T-STDP model. To understand the performance of a silicon neural network with integrate and fire neurons and the proposed FG synapses, we have performed SPICE simulations of such a system with a behavioural model of the FG device. The third order correlation model is simulated in SPICE and the results are matched with MATLAB simulations to lay the foundation for future silicon implementations. In future, the work described in this thesis can be extended to make software simulations of larger neural networks with multiple neurons and synapses following the FG based T-STDP learning rules. VLSI implementations of the same may also be fabricated using low-power subthreshold analog techniques. Further, these models may be used to classify realistic spiking image datasets such as the one described in [3]. Doctor of Philosophy (EEE)

There is a huge need for embedded machine learning for portable devices and smart sensors to power the next generation of Internet of Things (IoT). Implementation of neural networks involve large number of arithmetic and memory operations. Realization of the arithmetic blocks with conventional digital circuits will inherit a trade-off between accuracy of calculation and area required. On the other hand, existing analog building blocks for neural networks suffer from inaccuracies related to process variation and large power consumption. Moreover, the efficiency of computation-memory interface is degrading since memory bandwidth increment is poor compared to computation throughput growth in CMOS technology. Though the recent large scale neuromorphic circuits have used localized random access memory for reducing memory operations, this local memory size will not be scalable with increasing size of datasets. Here, we explore novel CMOS and post-CMOS circuits to realize ultra-low power neuromorphic circuit by co-design of algorithm and hardware. The solutions also overcome the issue of increasing bandwidth gap between memory operations and computation. First, a deep neural network with 2 convolution layers and 2 fully connected layers, is chosen and tuned for hardware implementation. The network has few tunable parameters (_ 40000) and is 40 times faster in training than usual deep neural networks with 4 layers. We propose a compact, single transistor element for realizing the connections inside the neural network- called ’synapse’. These synapses perform the computations involved by virtue of mismatch inherent in their fabrication. We use a current mirror array with n-input lines and m output lines, to perform ’n x m’ Multiply and Accumulation operation. The resultant neuromorphic circuit can emulate multi-layered artificial vision system. A circuit fabricated in 0.35_m CMOS process is characterized and a behavioral model is simulated for the deep neural network. Here, the learning is done offline. The inputs to the network may vary according to environmental conditions, for which we need an adaptive neural network. Hence we propose a second solution where the neuromorphic circuit can adapt it’s parameters in real time. With the advent of novel nanoscale devices with physical properties well matched to neural network enabling computations at energies much lower than CMOS, the research also focuses on use of a post-CMOS spintronic device-a Domain-Wall magnet for obtaining a low power spike timing dependent plastic (STDP) synapse for online learning. The spin-mode signals are injected across small potential (_ 50mV) through multiple layers of ferromagnetic and non-magnetic layers. Here we discuss the implementation of a spiking neural network with synapses which can be trained according to STDP learning rule. A detailed study with the help of device circuit co-simulation is done. Possible use of this synapse in online, real time learning spiking neural networks is also illustrated in this thesis. Master of Engineering

Epilepsy is a chronic neurological disorder affecting approximately 1% of the world’s population, which predisposes those affecting to experiencing recurrent seizures. Despite advances in currently available treatments like anti-epileptic drugs and epilepsy surgery, 25% of the patients continue to have disabling seizures. These unpredictable and medically intractable seizures make an epileptic patient susceptible to high risk of sustaining physical injuries. A reliable real-time seizure detection/prediction system that can drive an antiepileptic device or alert the patient/caregiver about the coming seizure would provide a better quality of life for epileptic patients. Our research work discusses the design of a wearable smart sensor for real-time, patient-specific epileptic seizure detection through the continuous monitoring of non-invasive EEG. In this thesis, we are proposing a smart sensor architecture for epileptic seizure detection. We first present a novel patient specific epileptic seizure detection algorithm, which employs individual Extreme Learning Machine (ELM) classifiers at each EEG electrode/channel to classify the feature vectors extracted from each EEG channel to seizure or non-seizure. Classification outputs from individual EEG channels are categorized at a master classifier to detect the seizure onset. Spectral energy in different frequency bands of EEG signal is used as a feature vector. This algorithm has the advantage of using low dimensional feature space for classification reducing the complexity of higher dimensional classification with a single classifier. Also it provides flexibility to choose the electrodes required to make the seizure prediction system for a particular patient during training which can reduce the amount of data used for classification, increasing training speed and performance of the classifier. The proposed algorithm is validated using 109 hours of seizure EEG data of three patients with 19 seizures, and we achieved sensitivity, specificity and latency of 100%, 16 (false alarms per hour) and 3.6 seconds respectively. We also do a system simulation for different methodologies of feature vector extraction to obtain specifications for hardware implementation of the algorithm. We also propose a hardware architecture for the algorithm implementation in analog integrated circuits. A smart sensor IC designed in AMS 0.35um CMOS for real time EEG acquisition from a scalp EEG channel electrode, feature vector extraction and ELM classification for on-chip seizure onset detection using low power analog integrated circuit topologies is presented. The novelty of this design compared to existing architectures is the use of an on-chip spiking neuron based ELM classifier. ELM possesses similar classification capabilities as a support vector machine (SVM), but requires less nodes for classification. Also ELM requires random weights in the first stage which can be obtained from the inherent threshold voltage variations of transistors. The mismatch inherent in analog VLSI circuits, which is seen as a disadvantage in most of the analog designs, is thus exploited in ELM hardware implementation. Simulation results show the integration of signal processing and classification at the sensor node itself can reduce the power consumption by 75% compared to existing seizure detector architectures. Local processing for different EEG pattern recognition/classification at the sensor node itself can also be used in prompt feedback applications like Brain to Computer Interface (BCI) applications. On-chip data reduction and low power operation makes this approach suitable for wearable EEG applications like long term EEG recordings for clinical diagnosis. Master of Engineering

In this thesis, we describe a methodical approach for reducing errors due to mismatch in neuron circuits. We chose the neuron’s current-frequency (f-i) curve as the desired output and use a sensitivity analysis to determine which transistors contribute most significantly to its variation. This allows us to identify the most critical transistors that need to be matched. For the special case in which floating-gate (FG) transistors are used to reduce this mismatch, we propose a method to further reduce the number of FG devices to be used in the circuit resulting in a corresponding reduction in ‘calibration’ time. In addition to reducing mismatch between neurons, the usage of FG devices allows the user to independently set the parameters of each neuron. Since the calibration is based on f-i curve, it can be obtained through address-event representation (AER) circuits that are included in the neuron array for normal functionality. We use one example of commonly used integrate and fire neuron to illustrate this mismatch correction procedure. The method presented allows the corrected neurons to compute both rate codes and spike time codes in a mismatch resilient fashion. We have fabricated a chip containing three different type neuron arrays, synaptic circuits, and input/output AER interfacing circuits. It occupies 2.5mmx5.5mm area using VIS 0.35um technology. The chip receives and generates data in AER format, which is asynchronous and digital. However, its internal operation is based on analog low-current circuit techniques. MASTER OF ENGINEERING (EEE)