384 results on '"Laxmi, Vijay"'
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352. On Designing Testable Reversible Circuits Using Gate Duplication
353. A Low-Power Wideband High Dynamic Range Single-Stage Variable Gain Amplifier
354. A Methodology for Early and Accurate Analysis of Inrush and Latency Tradeoffs during Power-Domain Wakeup
355. On-Chip Dilution from Multiple Concentrations of a Sample Fluid Using Digital Microfluidics
356. Architectural Level Sub-threshold Leakage Power Estimation of SRAM Arrays with its Peripherals
357. A Novel Design Methodology for High Tuning Linearity and Wide Tuning Range Ring Voltage Controlled Oscillator
358. CPK Based IO AC Timing Closure to Reduce Yield Loss and Test Time
359. Variation Robust Subthreshold SRAM Design with Ultra Low Power Consumption
360. Modeling of High Frequency Out-of-Plane Single Axis MEMS Capacitive Accelerometer
361. Optimization of Underlap FinFETs and Its SRAM Performance Projections Using High-k Spacers
362. Energy Efficient Array Initialization Using Loop Unrolling with Partial Gray Code Sequence
363. Performance Analysis of Subthreshold 32-Bit Kogge-Stone Adder for Worst-Case-Delay and Power in Sub-micron Technology
364. CMOS ASIC Design of a High Performance Digital Fuzzy Processor That Can Compute on Arbitrary Membership Functions
365. A Cache-Aware Strategy for H.264 Decoding on Multi-processor Architectures
366. Design and Analysis of a Novel Noise Cancelling Topology for Common Gate UWB LNAs
367. Congestion Balancing Global Router
368. Analysis of Crosstalk Deviation for Bundled MWCNT with Process Induced Height and Width Variations
369. Random-LRU: A Replacement Policy for Chip Multiprocessors
370. Convex Optimization of Energy and Delay Using Logical Effort Method in Deep Sub-micron Technology
371. A Combined CMOS Reference Circuit with Supply and Temperature Compensation
372. Process Aware Ultra-High-Speed Hybrid Sensing Technique for Low Power Near-Threshold SRAM
373. Impact of Fin Width and Graded Channel Doping on the Performance of 22nm SOI FinFET
374. An Efficient RF Energy Harvester with Tuned Matching Circuit
375. A Modified Gate Replacement Algorithm for Leakage Reduction Using Dual-Tox in CMOS VLSI Circuits
376. An Improved g m /I D Methodology for Ultra-Low-Power Nano-Scale CMOS OTA Design
377. Design and Simulation of Bulk Micromachined Accelerometer for Avionics Application
378. A Dual Material Double-Layer Gate Stack Junctionless Transistor for Enhanced Analog Performance
379. Characterization of Logical Effort for Improved Delay
380. Preemptive Test Scheduling for Network-on-Chip Using Particle Swarm Optimization
381. Pre-Silicon NBTI Delay-Aware Modeling of Network-on-Chip Router Microarchitecture.
382. Recent advances in two-dimensional perovskite materials for light-emitting diodes.
383. Meta-QTL and ortho analysis unravels the genetic architecture and key candidate genes for cold tolerance at seedling stage in rice.
384. Pulsed Carrier Gas Assisted High-Quality Synthetic 3 R -Phase Sword-like MoS 2 : A Versatile Optoelectronic Material.
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