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Over the last decade, lasers have been gradually employed for Si wafer dicing to replace blade dicing. Laser dicing has the potential to replace blade dicing as the future generation ultrathin wafer singulation method as it enables higher cutting speed, lower damage, and smaller kerf width but various technical challenges still remain to be resolved. In this article, laser ablation and dicing of Si wafers are reviewed in terms of the physics of laser-material interaction based on nanosecond, picosecond, and femtosecond pulse durations. The effects of various laser settings, dicing process parameters, and material factors on ablation rate, ablation precision and quality, and die fracture strength are discussed in detail. With the increasing usage of Cu stabilization layer on the backside of ultrathin Si wafers, we also review laser-material interaction in Cu and elaborate on recent findings on the effects of laser dicing through Si and Cu simultaneously on the microstructural and fracture strength properties of the die. Various approaches to improve the ablation rate, ablation quality, and die fracture strength are discussed.

In eukaryotes, small RNAs (sRNAs) play critical roles in multiple biological processes. Dicer endonucleases are a central part of sRNA biogenesis. In plants, DICER-LIKE PROTEIN 3 (DCL3) produces 24-nucleotide (nt) small interfering RNAs (siRNAs) that determine the specificity of the RNA-directed DNA methylation pathway. Here, we determined the structure of a DCL3–pre-siRNA complex in an active dicing-competent state. The 5′-phosphorylated A1 of the guide strand and the 1-nt 3′ overhang of the complementary strand are specifically recognized by a positively charged pocket and an aromatic cap, respectively. The 24-nt siRNA length dependence relies on the separation between the 5′-phosphorylated end of the guide RNA and dual cleavage sites formed by the paired ribonuclease III domains. These structural studies, complemented by functional data, provide insight into the dicing principle for Dicers in general.

Purpose Si-based micro electro mechanical systems (MEMS) magnetometer does not require specialized magnetic materials avoiding magnetic hysteresis, ease in fabrication and low power consumption. It can be fabricated using the same processes used for gyroscope and accelerometer fabrication. The paper reports the dicing mechanism for the released MEMS xylophone magnetic sensor fabricated using wafer bonding technology and its characterization in ambient pressure and under vacuum conditions. The purpose of this paper is to dice the wafer bonded Si-magnetometer in a cost-effective way without the use of laser dicing and test it for Lorentz force transduction. Design/methodology/approach A xylophone bar MEMS magnetometer using Lorentz force transduction is developed. The fabricated MEMS-based xylophone bars in literature are approximately 500 µm. The present work shows the released structure (L = 592 µm) fabricated by anodic bonding technique using conducting Si as the structural layer and tested for Lorentz force transduction. The microstructures fabricated at the wafer level are released. Dicing these released structures using conventional diamond blade dicing may damage the structures and reduce the yield. To avoid the problem, positive photoresist S1813 was filled before dicing. The dicing of the wafer, filled with photoresist and later removal of photoresist post dicing, is proposed. Findings The devices realized are stiction free and straight. The dynamic measurements are done using laser Doppler vibrometer to verify the released structure and test its functionality for Lorentz force transduction. The magnetic field is applied using a permanent magnet and Helmholtz coil. Two sensors with quality factors 70 and 238 are tested with resonant frequency 112.38 kHz and 114.38 kHz, respectively. The sensor D2, with Q as 238, shows a mechanical sensitivity of 500 pm/Gauss and theoretical Brownian noise-limited resolution of 53 nT/vHz. Originality/value The methodology and the study will help develop Lorentz force–based MEMS magnetometers such that stiction-free structures are released using wet etch after the mechanical dicing.

Semiconductor Companies and Industries soar high as the trend for electronic gadgets and devices increases. Transition from “manual” to “fully automatic” application is one of the advantages why consumer adapt to changes and prefer electronic devices as one of daily answers. Individuals who admire these electronic devices often ask how they are made. As we look inside each device, we can notice interconnected microchips commonly called IC (Integrated Circuit). These are specially prepared silicon wafers where integrated circuit are developed. Commonly, each device is composed of numerous microchips depending on the design and functionality IC production is processed from “front-end” to “back-end” assembly. Front-end assembly includes wafer fabrication where electrical circuitry is prepared and integrated to every single silicon wafers. Back-end assembly covers processing the wafer by cutting into smaller individual and independent components called “dice”. Each dice will be placed into Leadframe, bonded with wires prior encapsulating with mold compounds. After molding, each IC will be cut through a process called singulation. Afterwards, all molded units are subjected for functional testing. Dice is central to each IC; it is where miniature transistor, resistor and capacitor are integrated to form complex small circuitry in microchips. Pre-assembly (Pre-assy) stations have the first hand prior to all succeeding stations. Live wafers are primary direct materials processed in these stations. Robust work instruction and parameter must be practiced during handling and processing to avoid gross rejection and possible work-related defects. The paper is all about the challenges to resolve and improved the backside chippings in 280um wafer thickness in mechanical dicing saw. The conventional Mechanical dicing process induce a lot of mechanical stress and vibration during the cutting process which oftentimes lead to backside chipping and die crack issues. However, backside chippings can mitigate with proper selection of parameter settings and understand the silicon wafer properties.

The present study was performed to understand the interfacial reaction between Al/Ti bi-layered films and 4H–SiC with various surface orientations and the preferential growth orientation of Ti3SiC2 crystals. To this end, n-type 4H–SiC crystals oriented to the (0001), (1 1 ‾ 00), and (11 2 ‾ 0) surfaces were prepared. The (0001) and (11 2 ‾ 0) surfaces of the p-type 4H–SiC were composed of commercially available p-type 4H–SiC wafers; these surfaces were tilted by 8° from (0001) towards [11 2 ‾ 0] by the dicing and polishing of the wafers. Using the same method, another surface orientation was achieved wherein the surface was tilted by 30° from (11 2 ‾ 0) towards [0001]. Further, Al/Ti bi-layered films were deposited on each SiC substrate, using the radio-frequency magnetron sputtering method, which was followed by the stepwise annealing. The microstructures were examined by X-ray diffractometry and transmission electron microscopy. The Ti3SiC2 phase grew epitaxially in the [11 2 ‾ 0]SiC orientation on the (0001) surface of 4H–SiC. Ti3SiC2 phase did not grow uniformly on the other SiC surfaces that were oriented to (1 1 ‾ 00) or (11 2 ‾ 0). The Ti3SiC2 phase growth was columnar and parallel to (0001)SiC in the [11 2 ‾ 0]SiC orientation on the SiC surface tilted by 30° from (11 2 ‾ 0) towards [0001]. The electrical characteristics of p-type 4H–SiC contact films measured before and after annealing revealed that the characteristics of Al/Ti/(11 2 ‾ 0)4H–SiC were improved after annealing.

A novel solid-liquid inter-diffusion (SLID) bonding process is developed allowing to use thin layers of the Au-Sn material in wafer-level microelectromechanical systems (MEMS) packaging while providing a good bonding strength. The bond material layers are designed to have a robust bond material configuration and a metallic bond with a high re-melting temperature, which is an important advantage of SLID bonding or with its alternative name, transient liquid phase (TLP) bonding. The liquid phase in SLID bonding is the gold-rich eutectic liquid of the Au-Sn material system, where the bonding temperature is selected to be 320 °C for a reliable bonding. The average shear strength of the bonds is measured to be 38± 1.8 MPa. The hermeticity of the package is tested with the He-Leak test according to MIL-STD 883, which yields a leak value lower than $0.1 \times 10^{-9}\,\, atm.cm^{\textit {3}}/s$ . The vacuum inside the package without a getter is calculated as 2.5 mbar after cap wafer thinning. The vacuum level is well preserved after post-processes such as annealing at 400 °C and the dicing process. These results verify that thin layers of Au-Sn materials can be used reliably with the SLID or TLP bonding technique using the new approach proposed in this study. [2020-0353]

Previous studies on nanosecond and picosecond laser dicing have shown that the Si die sidewall microstructures and fracture strengths are significantly different when dicing simultaneously through Si and a Cu backside layer, in contrast to dicing solely through Si. This work systematically investigated the effect of femtosecond laser dicing on the fracture strength and sidewall microstructure of 20 μm Si dies with 0−30 μm Cu backside layer. Using an improved three-point bending (3PB) test method, the intrinsic fracture strengths of the die sidewall were measured. The die types with Cu backside show an average of 46.5 % higher backside characteristic fracture strength, but an average of 6.6 % lower frontside characteristic fracture strength, compared to the die type without Cu backside. Fractographic analysis by scanning electron microscopy was carried out to determine the fracture initiation behaviour in the 3PB test samples. The microstructures, phases, and defects at the sidewall were characterized by transmission electron microscopy, and their effect on fracture strength is discussed. Based on the observed microstructural features, some suggestions in relation to the femtosecond laser processing parameters are made to improve the die sidewall frontside and backside fracture strengths, in comparison to previous results from nanosecond and picosecond laser dicing.

Vertical Si nanowire (SiNW) gas sensor with a top porous electrode (TPE) has been reported as a highly sensitive, small footprint, and mass-producible gas sensor platform. In this article, a monolithic fabrication process for a vertical SiNW gas sensor using glancing angle deposition (GLAD) was proposed as a simple, low-cost, and large-area fabrication method, and the performance of the fabricated vertical SiNW gas sensor was evaluated via relative humidity measurement. The 1,000 nm length vertical SiNWs were uniformly fabricated on a 4-inch silicon wafer via GLAD at an oblique angle of 85° and a substrate rotation speed of 5 rpm. A Cu TPE was also fabricated via sequential GLAD without substrate rotation to realize the wafer-level vertical gas sensor from which multiple 2 × 2 cm2 vertical SiNW gas sensors were obtained by dicing. To optimize the Cu TPE fabrication process, the effects of oblique angle and deposition thickness on the conductivity and porosity of the TPE were examined; subsequently, an oblique angle of 65° and a thickness of 100 nm were selected as the optimum conditions when considering humidity measurement sensitivity.

Liquid cell transmission electron microscopy (LCTEM) enables imaging of dynamic processes in liquid with high spatial and temporal resolution. The widely used liquid cell (LC) consists of two stacking microchips with a thin wet sample sandwiched between them. The vertically overlapped electron-transparent membrane windows on the microchips provide passage for the electron beam. However, microchips with imprecise dimensions usually cause poor alignment of the windows and difficulty in acquiring high-quality images. In this study, we developed a new and efficient microchip fabrication process for LCTEM with a large viewing area (180 µm × 40 µm) and evaluated the resultant LC. The new positioning reference marks on the surface of the Si wafer dramatically improve the precision of dicing the wafer, making it possible to accurately align the windows on two stacking microchips. The precise alignment led to a liquid thickness of 125.6 nm close to the edge of the viewing area. The performance of our LC was demonstrated by in situ transmission electron microscopy imaging of the dynamic motions of 2-nm Pt particles. This versatile and cost-effective microchip production method can be used to fabricate other types of microchips for in situ electron microscopy.

In this paper, we present the development of a high-speed dual-beam stealth laser dicing (D-SLD) method for processing semiconductor wafers based on electrically tunable lenses (ETLs). An SLD system utilizes a laser beam to dice a wafer by inducing interior defects without modifying the surface characteristics of a wafer, thereby presenting significant advantages over conventional dicing methods, e.g., blade dicing or laser ablation. Currently, the throughput of SLD is limited by the serial scanning process; in addition, wafer misalignment and the warpage effects together deteriorate the dicing quality and yield and demand high-cost multi-axis precision stages. To address the issue, we parallelize the dicing process by splitting the laser focus into two foci, where the laser intensity at different depths are automatically adjusted to achieve optimal dicing condition. By combining the height sensor and ETLs, each laser focus, i.e., laser scan lines, can be rapidly controlled axially to compensate the wafer curvature and misalignment errors in real time, leading to substantially improved precision (kerf width

Direct wafer bonding is getting a standard and essential process in high density 3D integration devices. In this study, we investigated impact of direct bonding interface and extremely thinned Si on dicing and thinning processes. By comparing single wafer and direct bonded wafer having extreme thinned Si on top, bigger frontside chippings are observed after dicing for the case of direct bonded wafer. However, cross-sectional images unveil that the initiated point of the chipping is at the interface between SiCN and SiO2, not at the bonding interface. It indicates that direct bonding interface and 5 μm Si are not the root-cause of the chippings. For the backside thinning process, comprehensive analysis including atomic scale vacancy measurement/observation and macro level roughness/morphology analysis are executed. The major impact on die strength was given by macro level roughness. Despite having bigger chipping on bonded wafer, higher die strength is obtained from bonded wafer. It might be due to the stress buffering caused by bonding interface.

In this work, we demonstrate an edge coupler (EC) for the coupling between the single mode fiber (SMF) and the silicon photonic waveguide. High coupling efficiency can be achieved by using arrayed waveguides at 1550 nm with an un-patterned cladding. With such a design, the light will be “pulled” to the top cladding, avoid the using of a cantilever structure. Compared to the conventional inverse taper spot size converter, the widths for the arrayed waveguides are the same, thus it is not critical to determine the position of the end facet for dicing/polishing. We fabricated the proposed structure with only one-step lithography following by a dry etching process. The measured coupling loss is around 1.7 dB/facet, which agrees well with the simulations.

In the present work, we report design, fabrication and testing of a novel DC MEMS switch incorporating a self-encapsulated and recessed micro-cantilever beam. Wafer level anodic bonding with press-on contacts between silicon and glass is used innovatively to secure the recessed cantilever beam from one side. The cantilever is made of single crystal silicon in a recessed cavity whereas actuating electrode and signal lines are formed on corning glass. Anodic bonding provides “press on contacts” between silicon and glass plate and also secures the cantilever beam in the recessed cavity in silicon. The signal lines and pull-in electrode are formed on the glass plate using aluminium metallization while the cantilever has a gold pad at its tip. The anodic bonding provides three major advantages (i) it encapsulates the fragile beam and thus protects it from damage during dicing and packaging process (ii) it provides press-on contact between signal lines on glass plate and bonding pads on silicon (iii) it makes the beam optically visible. The devices were simulated using COMSOL multiphysics software and the results were compared with experimentally measured values. The cantilever based switch operates at low actuation voltage (average ~ 12 V) indicating that it can be used for power electronic circuits and various other applications.

Dicing of semiconductor chips constitutes an important procedure in the processing of integrated circuits, which poses a high-precision and high-speed stability requirements for dicing saw. In this study, the optimization of motion accuracy and position accuracy of dual-axis dicing saw (DDS) is studied and an overall control scheme of the DDS is designed. A programmable multi-axis controller (PMAC) is selected as the main control module and the servo motor is adopted as the linear axis drive element. The positioning algorithm of servo control system is analyzed. The position deviations are studied under different proportional gains, integral time constants, and speed feedforward gains. The high-precision contact and non-contact positioning method of the machine tool is developed. Positioning error of each linear axis is compensated using positioning error compensation module of PMAC. The dicing test results demonstrate that the improved control system could be used for high-precision and high-speed stability dicing of semiconductor chips.

The adhesion between metal and polymer layer was studied using four-point bending tests. It was shown that as the annealing temperature increased, oxidation binding increased, which decreased adhesion and reduced the $G_{c}$ value. A new four-point bending test sample prepared using the stealth dicing method with a 100% success rate was proposed for the first time. With samples prepared with stealth dicing, the region where crack extension occurred was smaller after the stress test. Less crack extension generated less loading on the samples. Owing to the coefficient of thermal expansion (CTE) mismatch after increasing the temperature in a highly accelerated stress test (HAST), a void formed in stealth dicing was made close to the interface between the silicon layer and the polymer layer after the stress test, and less crack extension occurred compared with samples kept at room temperature. The smaller loading force guarantees much more stable measurement with a higher success rate after the stress tests. The stealth dicing method can be applied to other structures, such as redistribution layers (RDLs).

Silicon wafers are a key component in integrated circuits which comprised of various electronic components that are arranged to perform a specific function. Wafer dicing is a mechanical process of removing material from a wafer by synthetic diamonds as abrasive particles. Chipping along the cut line crucial to the wafer dicing operation has been identified by semiconductor manufacturers as a relevant area for improvement. The purposed of this study is to characterize the effect of dicing operation on the optical silicon wafer coating material. The effect of the blade wear and silicon wafer kerf width will be analyzed in this work

This paper presents the fabrication of a silicon neural probe using low-cost microfabrication technologies, such as thin-films deposition, blade dicing, and photolithography. The metal stack that forms the 9 microelectrodes of 50 × 50 µm2 area, the tracks and the pads were made of Ti and Pt, while the passivation stack was SiO2 and Si3N4. The fabricated probe was characterized using electrochemical impedance spectroscopy, before and after deposition of poly(3,4-ethylene-dioxythiophene) (PEDOT) on Pt microelectrodes. The electrochemical deposition of PEDOT, a conductive polymer, reduced the impedance of the Pt microelectrodes. The neural probe with PEDOT was used for in vivo electrophysiological acute recordings in an adult rat. The extracellular recordings were filtered to obtain the spike and local field potential (LFP) data, using Butterworth bandpass filters of 400–6000 Hz and 0.1–300 Hz, respectively. The results obtained with the fabricated neural probe validated its functionality, comparing with the signals acquired with a commercial neural probe, and the viability of the fabrication process, which avoids high–cost and complex etching processes., s ANI supports this work through the Brain Lighting project by FEDER funds through Portugal 2020, COMPETE 2020 with the reference POCI-01-0247-FEDER-003416. This work is also supported by FCT with CMEMS-UMinho Strategic Project, reference UIDB/04436/2020, the project Infrastructures Micro&- NanoFabs@PT, reference NORTE-01-0145-FEDER-022090, POR Norte, Portugal 2020 and by the project OpticalBrain, reference PTDC/CTM-REF/28406/2017, by FEDER funds through the COM PETE 2020 - Programa Operacional Competitividade e Interna cionalizac¸a˜o (POCI). The authors acknowledge also FCT CEECIND grants, Bial Foundation Grants 207/14 and 037/18 to JO; Northern Portugal Regional Operational Programme (NORTE 2020), under the Portugal 2020 Partnership Agreement, through the European Regional Development Fund (FEDER) (NORTE-01-0145-FEDER-000013); FEDER Funds, through the Competitiveness Factors Operational Programme (COMPETE), and The National Fund, through the FCT (POCI-01-0145-FEDER-007038). The authors also thank to N. A. P. de Vasconcelos from ICVS-University of Minho for the implemen tation of the setup for the in vivo recordings.

In this work, the isocyanate terminated castor oil based urethane oligomer (CO-IPDI) was prepared by the reaction of castor oil and isophorone diisocyanate (IPDI) without adding any organic solvent...

The main objective of this article is to establish which of the many dicing tapes used in the semiconductor industry would be most suitable for use in plasma dicing. Tape design over the past 40 years has continually evolved through advancements in both dicing technologies and the incessant revision of integrated circuit packaging. Die singulation has traditionally been accomplished using a diamond saw, laser-based technology, or a combination of both. The stress on dicing tape was, therefore, limited to fatigue through the physical nature of saw dicing or heat energies induced during laser dicing. These processes do not expose dicing tape to either a high vacuum or a variety of plasma chemistries. This investigative work is a continuation of studies examining the dicing tape behavior when used in plasma dicing. Results show that polyolefin (PO) UV tape with low-to-medium adhesion strength exhibits the greatest resilience under harsh plasma etch conditions and that efficient photoinitiated cross linking (or curing) of the adhesive is triggered if directly exposed to the photonic energies present in a pure SF6 plasma or full plasma dicing process. However, the postplasma dice, post-UV cure adhesive strength can still be minimized if the tape manufacturers recommended time limitations between which the tape mount, plasma dice, and die pickup process are adhered to.

Spatial zigzag evolution of cracks in moving sapphire wafer was observed after irradiation with sequences of picosecond laser pulses (bursts). The Gaussian beam was tightly focused inside the sapphire. The spatial position of laser initiated cracks moved in vertical and horizontal directions when a wafer was translated at a controllable speed perpendicular to the beam propagation direction. The cracking plane consisting of the periodically repeating inclined modifications and cracks was observed. The period of modifications and the inclination angle had a linear dependence on the wafer translation speed. The model of spatial zigzag crack evolution was created and the physical origin of modification growth at a measured speed of 1.3 ± 0.1 m s−1 is discussed. The zigzag cracking was applied for ultrafast stealth dicing and cleavage of the sapphire: dicing speed 300 mm s−1, wafer thickness 430 μm, laser power 5.5 W, repetition rate 100 kHz, sub-pulse duration 9 ps, the temporal distance between sub-pulses in burst 26.7 ns, and the number of sub-pulses 13.

Laser-based fabrication, including the ultrashort laser ablation and the subsequent CO2 polishing steps, is a very attractive tool for the complex 2.5D surface structuring, which could be applied for the fabrication of compact optical elements. However, as an alternative to conventional optics, these elements require validation, especially for high power applications, such as material processing. In this contribution, we comprehensively investigate all-laser-fabricated axicons from fused silica. We demonstrate that these elements allow the generation of high-quality Bessel-like optical beam with a long non-diffractive length and could be efficiently applied for 1 mm-thick glass dicing. Furthermore, we show that the asymmetry of the generated intensity pattern could be controlled via axicon tilt operation, which allows generating elongated modifications with the dominant transverse crack propagation direction. As a result, the higher dicing speed with better dicing quality and easier separation is achieved.

An advanced CMOS-compatible 300- $\text{mm}$ -wafer silicon-photonics platform is introduced that consists of a silicon layer with eight doping masks, two silicon-nitride layers, three metal and via layers, a dicing trench for smooth edge-coupled facets, and a gain-film trench that enables interaction between the gain material and waveguide layers. The platform was used to demonstrate an electrically-steerable integrated optical phased array powered by an on-chip erbium-doped laser. Lasing with a single-mode output, $30\,\text{dB}$ side-mode-suppression ratio, and $\text{40 mW}$ lasing threshold was shown, and one-dimensional beam steering with a $\text{0.85}^\circ \times \text{0.20}^\circ$ full-width at half-maximum and $\text{30}^\circ /\text{W}$ electrical steering efficiency was demonstrated. This system represents the first demonstration of a rare-earth-doped laser monolithically-integrated with an active CMOS-compatible silicon-on-insulator photonics system.

To show the technical feasibility of high-frequency and broadband anti-reflection (AR) coating for silicon optics in millimeter wavelengths, we fabricated a prototype of the four-layer sub-wavelength structure (SWS) using a combination of deep reactive ion etching (DRIE) and dicing processes. We also fabricated a three-layer SWS using a multi-layer DRIE technique. The described processes allow to obtain physical prototypes that are close enough to those designed that their simulated reflectances are slightly worse than expected. The simulations of the obtained three- and four-layer prototype showed the averaged reflectances of 5.2 % at 150–450 GHz and 3.7 % at 100–450 GHz, while the designed SWSs showed 1.6 % and 2.0 %, respectively.

Ultra-thin dicing blade is usually used to achieve a high precision cutting in semiconductor back-end packaging and assembly. Lots of interactional parameters involving in dicing blade preparation and cutting process bring difficulties to high cutting qualities and good working life of dicing blade. In order to address these problems, this study prepared three kinds of dicing blades and characterized the cutting properties of three dicing blades. It first proposed the abrasive exposure coefficient and tool deviation coefficient to provide parameters for the cutting force model. Then the experimental apparatus was set up to verify the proposed cutting force model. And a series of parameters including feed rate, spindle current, edge chipping coefficient, tool wear amount and grinding performance are used to characterize the comprehensive performance of prepared dicing blades. Finally, the edge morphology was observed under 3D microscope to analysis the hardness of different dicing blades. The theoretical and experimental results indicate that the proposed cutting force model can reflect actual cutting process. There is an inverse proportional function between the shedding of abrasive particles and the hardness of the matrix. The cutting performance of dicing blades is very dependent on the material of workpiece. C-dicing blades presents outstanding comprehensive effects with small chips and good self-sharpening properties.

Bonding of Indium phosphide (InP)-based electronic device and Silicon Carbide (SiC) heat spreader is beneficial to thermal management. In this study, InP/SiC structure was demonstrated using surface activated direct bonding at room temperature. The bond quality was evaluated by dicing testing and tensile testing.

SiC wafers, due to their hardness and brittleness, suffer from a low feed rate and a high failure rate during the dicing process. In this study, a novel dual laser beam asynchronous dicing method (DBAD) is proposed to improve the cutting quality of SiC wafers, where a pulsed laser is firstly used to introduce several layers of micro-cracks inside the wafer, along the designed dicing line, then a continuous wave (CW) laser is used to generate thermal stress around cracks, and, finally, the wafer is separated. A finite-element (FE) model was applied to analyze the behavior of CW laser heating and the evolution of the thermal stress field. Through experiments, SiC samples, with a thickness of 200 μm, were cut and analyzed, and the effect of the changing of continuous laser power on the DBAD system was also studied. According to the simulation and experiment results, the effectiveness of the DBAD method is certified. There is no more edge breakage because of the absence of the mechanical breaking process compared with traditional stealth dicing. The novel method can be adapted to the cutting of hard-brittle materials. Specifically for materials thinner than 200 μm, the breaking process in the traditional SiC dicing process can be omitted. It is indicated that the dual laser beam asynchronous dicing method has a great engineering potential for future SiC wafer dicing applications.

In the field of high brightness LED, the requirements of miniaturization, output and yield are urgent. At the same time, low k dielectric layers are more and more widely applied in integrated circuit filed, in order to solve the problem of crosstalk and stray capacitance. Laser grooving technology is developed and be seen as an ideal solution for high brightness LED wafer and low-k wafer dicing. Because the chips dicing by non-contact laser grooving technology always have fewer defects than traditional blade sawing technology, such as surface chipping, backside chipping, metal peeling, inside cracks, and delamination. In this paper, two water-soluble adhesives containing different light absorbents are used in laser dicing process. Both adhesives have excellent absorption of special wave length light, and perfect wetting ability with substrates. In the LED wafers UV laser dicing, adhesive named LGP1020 can achieve a good dicing protective efficacy and no crack formed. The low-k wafer protected by LGP2020 after green laser grooving, chips are all in perfect condition. And the protective adhesive would not to be serious carbonized which difficult to clean, even if the power of the green light laser up to 7W. Experiment results show that both adhesives have a perfect protective effect and a widely usage range of laser power.

Wafer sawing is one of the back-end technologies of advanced packaging. Higher quality and narrower saw street can improve the density of die in one wafer, thus reduce the wafer cost. In this semiconductor industry, there are different wafer dicing methods, blade dicing, laser dicing, stealth dicing and plasma dicing. Plasma dicing gives the best chipping performance, almost zero chipping defect, but it requires high running cost. Laser dicing uses laser ablation to separate units, however, Heat Affect Zone (HAZ) on the sidewall is incurred, which will then lower the die strength. The conventional wafer dicing method, blade dicing, it induces mechanical stress that leads to chipping. The advantage of this technology is mature, low cost comparing with other methods, and it is still the most widely used method in this semiconductor industry. It is believed that with a process optimization, blade dicing is the best option among all. In this paper, we focus on replacing the plasma dicing technology with blade dicing in order to further reduce the processing costs. Result shows: (a) For sidewall chipping, slower feed rate and lower blade height Z1, chipping will be better. (b) For backside chipping, slower spindle speed Z2 and feed rate, lower blade height of Z1, backside reject rate will be decrease. (c) The backside and sidewall chipping size are within the quality specification range through process optimization. (d) All topside chipping are inspected by Automated Optical Inspection (AOI) and meet the standards (>99.8%). (e) Fly die issue can be solved by baking the wafer before sawing.

The drive for smaller size and thickness has created new package assembly process challenges. Stacked die packages are increasing in interest due to the resultant smaller package and increased functionality. The requirements for a stacked package is a thinner wafer that enables more die to be stacked in a package. The die are bonded using Die Attach Film (DAF) that is laminated on the back of a wafer prior to singulation. The singulation of DAF laminated wafers with wafer thickness

Static and dynamic strain sensing is required in high-temperature (HT), harsh-environments (HE) for industrial, aerospace, and energy sector applications to ensure equipment and process safety, reduce the cost of operation and maintenance, and increase process efficiency. Challenges that arise in HT HE sensing applications include device mounting, packaging, integrity, and stability in HT HE conditions. In previously reported work, static and dynamic strain surface acoustic wave resonator (SAWR) sensors were fabricated on langasite (LGS) and mounted on Inconel 625 strain beams for wireless testing up to 400°C. In this work, it has been identified that after subjecting the mounted SAWR strain sensor to thermal cycling between 100°C and 425°C, the measured sensitivity to dynamic strain decreased by 73% due to cracking at the adhesive/LGS interface, further deteriorating after additional thermal cycles. Strain modeling of the mounted LGS sensor chip up to 400°C revealed the existence of concentrated strain at the borders of the LGS chip. Microcracks caused by dicing make the chip boarders the most susceptible location for cracks to initiate when the sensor is subjected to thermal stress. In an attempt to mitigate the high strain at the LGS chip borders due to heating, adhesive shaping is proposed in this work. Simulations indicate a strain reduction of 50% at the border is achieved using both circular and triangular adhesive shapes, while also reducing the maximum strain over the entire adhesive/LGS interface by around 30%. The technique is thus promising for improving the integrity, reliability, and stability of static and dynamic strain sensors, particularly while operating under HT HE with several hundred-degree Celsius temperature excursions.

The laser stealth dicing system is a unique wafer processing system to enable high-throughput and debris-free wafer dicing. In the laser stealth dicing system, a focused pulsed laser forms a modification layer and cracks inside a silicon wafer. During pulsed laser radiation and wafer scanning, cracks formed in the previous shot interfere with a focusing laser pulse on a defocus plane. As a result, a part of interacted laser beam scatters, generating back-side splash defects on the device layer. An asymmetric beam shaping of defocused spot becomes necessary to minimize the splash defects. At the same time, the focused spot should maintain sufficiently small focused spot size to generate a modified layer inside the silicon wafer. This paper presents a concept of an innovative focusing spot shaping with an asymmetrical pupil phase filter which is individually optimized for both defocused and focused spots. We optimized the phase filter to generate a threedimensionally- asymmetrical focused spot which deforms defocused spot with a near diffraction-limited focal spot size. The through-focus spot shaping technique is enable to minimize splash defects and improve the yield of the laser wafer dicing process.

In the process of chip wafer dicing, it is necessary to manually check the relative position of the cut mark and the cutting path in real time in order to adjust the cutting disc in time. During the process, the instability of manual calibration will affect production efficiency. Therefore, this paper proposes an improved U-Net convolutional neural network to locate the cutting path. It improves the network's ability to extract image features and generalization capabilities by adding the RFB receptive field module proposed in the target detection task to the U-Net encoder. On the image segmentation effect of the wafer cutting path, the network RFB-UNet designed in this paper improves 2% on the indicators of MIoU and FWIoU. It is verified that the RFB is a module that can improve the existing network in the task of semantic segmentation. Besides, this paper constructs a dataset for image segmentation of the wafer cutting path.