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Abstract: The progress of industrial microelectronic technologies has already overtaken the 130nm CMOS generation that is currently the focus of IC designers for new front-end chips in LHC upgrades and other detector applications. In a broader time span, sub-100nm CMOS processes may become appealing for the design of very compact front-end systems with advanced integrated functionalities. This is especially true in the case of pixel detectors, both for monolithic devices (MAPS) and for hybrid implementations where a high resistivity sensor is connected to a CMOS readout chip. Technologies beyond the 100nm frontier have peculiar features, such as the evolution of the device gate material to reduce tunneling currents through the thin dielectric. These new physical device parameters may impact on functional properties such as noise and radiation hardness. On the basis of experimental data relevant to commercial devices, this work studies potential advantages and challenges associated to the design of low-noise and rad-hard analog circuits in these aggressively scaled technologies. [Copyright &y& Elsevier]