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The entanglement of the momentum of light with its spin at interfaces or inside structured media, known as the photonic spin‐Hall effect, holds great promise for various applications, such as beam splitting, focusing, and polarization detection. However, the photonic spin‐Hall effect remains unexplored in the field of logic operation. In this work, the photonic spin‐Hall effect of spoof surface plasmon polaritons (SSPPs) in programmable metamaterial is demonstrated. Moreover, photonic spin‐Hall logic devices based on programmable spoof plasmonic metamaterial are designed, enabling the control of energy flow through the utilization of both spin and digital coding, with examples including SSPPs logic gates such as the "AND" gate, the "NIMPLY" gate (A AND NOT B), the "OR" gate, and the "NOT" gate. The findings introduce the combination of digital coding metamaterial with the photonic spin Hall effect, which offers a powerful and flexible platform for controlling electromagnetic waves in information processing. [ABSTRACT FROM AUTHOR]

Hybrid magnetic tunnel junction (MTJ)/CMOS circuits based on the computation-in-memory (CIM) architecture are contemplated as the future generation of digital integrated circuits. It overcomes the limitations of von-Neumann architecture by offering solutions to problems such as memory wall and standby power dissipation. In this work, we have developed hybrid logic gates, such as AND/NAND, OR/NOR, and XOR/XNOR, for CIM architecture by integrating three terminal spin-Hall effect assisted spin transfer torque (SHE + STT) MTJs with standard CMOS. To write the MTJs an auto-write-stopping (AWS) circuit is adopted, whereas to perform the logic operations and produce the corresponding outputs, an improved sense amplifier circuit (ISA) is employed. All the hybrid logic gates are investigated for key performance indicators such as power, delay, device count, and power delay product (PDP). The results are compared with their conventional counterparts. The comparison reveals that the ISA + AWS-based hybrid gates dissipate 50.52% lower total power. The worst-case read delay of ISA + AWS hybrid AND/NAND, OR/NOR, and XOR/XNOR gates are 27.41%, 13.4%, and 21.28% lower. Meanwhile, the reduction of read PDP (write PDP) is 47.64% (37.09%), 25.78% (36.29%), and 39.31% (35.48%) observed with ISA + AWS hybrid AND/NAND, OR/NOR, and XOR/XNOR gates in comparison with the conventional counterparts. Hence the ISA + AWS gates are superior in terms of total power dissipation, worst read delay, and read/write PDP. Further, we have conducted Monte-Carlo simulations on all the logic circuits to study the parameter variations during fabrication. [ABSTRACT FROM AUTHOR]