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In this paper, we designed and implemented an intermodule connection architecture, which is required for the development of modules for a multifunctional robot. The proposed and implemented architecture is a dual bus architecture characterized by the fact that a composite blackboard and publish/subscribe service for realizing flat relationships among modules and the dynamic switching of information flows by the modules themselves can be compatible with tight integration and a guarantee of scalability. Through an implementation of conversational tasks, which used speech, acoustic, and image information in an integrated manner, it is confirmed that a tightly integrated system can be developed in a short period. © 2004 Wiley Periodicals, Inc. Syst Comp Jpn, 35(8): 54–65, 2004; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/scj.10585 [ABSTRACT FROM AUTHOR]

The authors have developed a communications architecture called RHiNET that is capable of high-performance parallel processing by interconnecting PCs and WSs. RHiNET uses not only computers concentrated in one place but also computers used for daily business within buildings and within floors for parallel processing. Networks used by RHiNET should have high effective bandwidths and small latencies for high-efficiency computing, as well as link lengths for connecting the computers within buildings and floors and a free topology. The former requirements are not satisfied sufficiently by the conventional LANs, while the latter is not satisfied by SANs which are used in cluster systems. RHiNET satisfies both conditions by using a switch having a large memory capacity. In this paper, the architecture and implementation of the RHiNET/SW1 switch used by RHiNET networks are discussed. A scheme called virtual cache is used in RHiNET/SW1 such that a large-capacity packet buffer is installed by SRAM outside the switch ASIC. In addition, the performance of the switch is evaluated by a simulator. © 2001 Scripta Technica, Syst Comp Jpn, 32(14): 24–33, 2001 [ABSTRACT FROM AUTHOR]

A distributed architecture that is suitable for a one-chip processor carrying out feedback control by integration of microactuators and sensors is presented. According to this architecture, a highly functional processor can be realized with a minimal number of transistors. A verification prototype is fabricated with PLD (Programmable Logic Device) IC, and running of a shape recognition algorithm for objects is successful. © 2000 Scripta Technica, Electron Comm Jpn Pt 2, 83(7): 48–55, 2000 [ABSTRACT FROM AUTHOR]

For more than a decade NEC dominated the Japanese PC market with its PC-98 architecture, which was incompatible both with its major Japanese rivals and the global PC standard. However, NEC was powerless to prevent the introduction of Japanese versions of Windows 3.1 and 95 that ran on its competitors' architectures as well as on the PC-98, unifying the Japanese PC market and creating a common set of application programming interfaces for all Intel-based Japanese PCs. The introduction of Windows rendered obsolete the large DOS-based software library that had provided strong positive externalities for the NEC architecture. Absent those advantages, the market share of the PC-98 standard fell from 60% to 33% in five years, and NEC finally abandoned the PC-98 in favor of the global standard. An examination of the unusual rise and fall of the PC-98 shows how victory in a standards competition can be negated by the introduction of a new architectural layer that spans two or more previously incompatible architectures. [ABSTRACT FROM AUTHOR]

Flexibility, extensibility and reliability of a computer network are efficiently achieved by a design with hierarchical architecture. In an actual network system the network design should be implemented by modules corresponding to the layers of the hierarchical architecture in order to real- ize Its inherent advantages. Generally, in highly modularized software the problem of overhead in transferring data between modules has to be solved. This paper presents a method of network software design which is easily implemented by a highly modularized software structure and describes implementation of the architecture through separate communication control and data processing in an operating system. These presentations are made by introducing the methods employed in constructing a local computer network called the S & T net. The methods presented in this paper can be applied generally to the design and realization of network software. [ABSTRACT FROM AUTHOR]

The current Internet, which was designed over 40 years ago, is facing unprecedented challenges in many aspects, especially in the commercial context. The emerging demands for security, mobility, content distribution, etc. are hard to be met by incremental changes through ad-hoc patches. New clean-slate architecture designs based on new design principles are expected to address these challenges. In this survey article, we investigate the key research topics in the area of future Internet architecture. Many ongoing research projects from United States, the European Union, Japan, China, and other places are introduced and discussed. We aim to draw an overall picture of the current research progress on the future Internet architecture. [ABSTRACT FROM PUBLISHER]

The authors describe some methods for developing a high-reliability and large-scale social infrastructure system over the long term with COTS hardware and several software techniques by examining a train traffic control system in Tokyo metropolitan area. [ABSTRACT FROM PUBLISHER]

The article reports on the online version of a draft system architecture for intelligent transportation system (ITS) in Japan. The system architecture was announced to the public in order to solicit comments on the draft. Information on how to access the full text of the draft architecture is mentioned.