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In this article, the bias stress instability (BSI) of multilayered MoS2 field-effect transistors (m-MoS2 FETs) encapsulated in hydrophobic polymers [cyclized transparent optical polymer (CYTOP)] was systematically investigated under the pulse-mode operation. Compared with the dc mode, the threshold voltage shift (Δ Vth) under positive-bias stress was inversely larger than that for negative-bias stress. BSI in the m-MoS2 FETs with CYTOP was negligibly affected by the external oxygen/moisture. Shallow hole traps and electron detrapping effects were strongly identified as the main causes of bias-polarity dependence on Δ Vth in the pulse mode. This can potentially be attributed to the sulfur vacancies in the m-MoS2, which have a short trap lifetime of hundreds of microseconds. During the pulse-mode operation, various parameters, such as duty cycle, timeframe, bias polarity, and electric field strength, were systematically adjusted and experimentally applied to elucidate the origins of the asymmetry of the BSI in pulse mode. Atomic- and energy-band models, as well as recovery time constant extraction, are suggested to support the key mechanism of bias-polarity effects on BSI, which are, nicely, consistent with previous reports. [ABSTRACT FROM AUTHOR]

The realization of high-k/IL/Ge MOS interfaces with thin equivalent oxide thickness (EOT), low interface state density (Dit), and high reliability is strongly needed for realizing Ge metal–oxide–semiconductor field-effect transistors (MOSFETs). In this article, we examine the properties of the slow trap areal density (Δ Nst) and Dit in Al2O3/GeOxNy/n-Ge MOS interfaces formed by atomic layer deposition (ALD) Al2O3 films with plasma post nitridation (PPN) and plasma post oxidation (PPO). Here, the process order and process time of PPN and PPO are systematically changed to optimize the Al2O3/GeOxNy/n-Ge MOS interface properties. It is found that N atoms induced into GeOx can suppress slow electron trapping. An Al2O3/n-Ge structure with 1-min PPN before PPO can reduce Δ Nst by 34% in a weak electric field, whereas PPN after PPO increase Δ Nst. Also, the sufficient time PPO process after PPN can decrease Dit to a similar level as that at the Al2O3/GeOx/n-Ge MOS interfaces. The temperature dependence of electron trapping properties is also experimentally evaluated. The slow electron trapping is expected to be more suppressed for the GeOxNy interfaces at real device operation temperature. [ABSTRACT FROM AUTHOR]

The influence of ${V}_{\text {GS}}/{V}_{\text {DS}}$ condition on the current stress (CS) instability in amorphous InZnO thin-film transistors (TFTs) with the self-aligned top-gate structure is comprehensively analyzed and quantitatively validated by consolidating: 1) the ${I}$ – ${V}$ and ${C}$ – ${V}$ characteristics; 2) the extraction of density of states; 3) the decomposition of threshold voltage shift ($\Delta {V} _{T}$); and 4) the computer-aided design simulation. It has been found that in a high ${V}_{\text {GS}}$ and low ${V}_{\text {DS}}$ CS condition, electron trapping into the gate insulator globally occurs. However, these effects are combined with a local electron trapping into gate insulator in the source region and the generated peroxide defects in the drain region under a high ${V}_{\text {DS}}$ and low ${V}_{\text {GS}}$ CS condition. The peroxide formation that is followed by the donor generation is clearly distinguished by the activation energy of 0.49 eV from the oxygen vacancies ionization which has been widely modeled for explaining the donor creation in amorphous oxide semiconductor TFTs. [ABSTRACT FROM AUTHOR]