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This article presents a detailed investigation of the impact of mechanical strain on transition metal dichalcogenide (TMD) material-based tunneling field-effect transistor (TFET). First, the impact of mechanical strain on material parameters of MoSe2 is calculated using the first principle of density functional theory (DFT) under meta-generalized gradient approximation (MGGA). The device performance of the TMD TFET has been studied by solving the self-consistent 3-D Poisson and Schrodinger equations in nonequilibrium Green’s function (NEGF) framework. The results demonstrate that both ION and IOFF increase with uniaxial tensile strain, however the change in ION/IOFF ratio remains small. This strain-dependent performance change in TMD TFET has been utilized to design an ultrasensitive strain sensor. The device shows a sensitivity (Δ IDS/IDS) of 3.61 for a strain of 2%. Due to the high sensitivity to the strain, these results show the potential of using MoSe2 TFET as a flexible strain sensor. Furthermore, the strained TFET is analyzed for backend circuit performance. It is observed that the speed and energy efficiency of ten-stage inverter chain based on controlled strain improve substantially in comparison to unstrained TFETs. [ABSTRACT FROM AUTHOR]

In this article, the bias stress instability (BSI) of multilayered MoS2 field-effect transistors (m-MoS2 FETs) encapsulated in hydrophobic polymers [cyclized transparent optical polymer (CYTOP)] was systematically investigated under the pulse-mode operation. Compared with the dc mode, the threshold voltage shift (Δ Vth) under positive-bias stress was inversely larger than that for negative-bias stress. BSI in the m-MoS2 FETs with CYTOP was negligibly affected by the external oxygen/moisture. Shallow hole traps and electron detrapping effects were strongly identified as the main causes of bias-polarity dependence on Δ Vth in the pulse mode. This can potentially be attributed to the sulfur vacancies in the m-MoS2, which have a short trap lifetime of hundreds of microseconds. During the pulse-mode operation, various parameters, such as duty cycle, timeframe, bias polarity, and electric field strength, were systematically adjusted and experimentally applied to elucidate the origins of the asymmetry of the BSI in pulse mode. Atomic- and energy-band models, as well as recovery time constant extraction, are suggested to support the key mechanism of bias-polarity effects on BSI, which are, nicely, consistent with previous reports. [ABSTRACT FROM AUTHOR]

The realization of high-k/IL/Ge MOS interfaces with thin equivalent oxide thickness (EOT), low interface state density (Dit), and high reliability is strongly needed for realizing Ge metal–oxide–semiconductor field-effect transistors (MOSFETs). In this article, we examine the properties of the slow trap areal density (Δ Nst) and Dit in Al2O3/GeOxNy/n-Ge MOS interfaces formed by atomic layer deposition (ALD) Al2O3 films with plasma post nitridation (PPN) and plasma post oxidation (PPO). Here, the process order and process time of PPN and PPO are systematically changed to optimize the Al2O3/GeOxNy/n-Ge MOS interface properties. It is found that N atoms induced into GeOx can suppress slow electron trapping. An Al2O3/n-Ge structure with 1-min PPN before PPO can reduce Δ Nst by 34% in a weak electric field, whereas PPN after PPO increase Δ Nst. Also, the sufficient time PPO process after PPN can decrease Dit to a similar level as that at the Al2O3/GeOx/n-Ge MOS interfaces. The temperature dependence of electron trapping properties is also experimentally evaluated. The slow electron trapping is expected to be more suppressed for the GeOxNy interfaces at real device operation temperature. [ABSTRACT FROM AUTHOR]

A 2-D electrothermal model of delta-doped beta-gallium oxide (β-Ga2O3) metal–semiconductor field-effect transistor (MESFET) is developed by using TCAD Sentaurus to investigate its electrical and thermal characteristics. The temperature and electric field-dependent electron mobility model is incorporated to predict I–V characteristics of the FET, which are in good agreement with the measured I–V characteristics. We investigated the effect of bias voltages on an electric field, a current path, a volumetric heat generation profile, and a peak temperature at a given total heat dissipation. The peak temperature is observed to be significantly different at the same power dissipation but different bias conditions, e.g., the peak temperature is ~9 K higher when the drain-to-source voltage (Vds) = 25 V and the gate-to-source voltage (Vgs) = −6 V compared with Vds = 8.3 V and Vgs = 2 V at the total power dissipation of 1.16 W/mm. This difference is attributed to the change in the electron Joule heating profile with the applied bias voltage. The effects of the location of the delta-doping layer, the gate–drain spacing, and the source–drain spacing are investigated to guide a future device fabrication. The variation in these parameters mainly affects electrical characteristics such as ON-resistance, saturation current, threshold voltage, and so on. The thermal characteristics, such as peak temperature, temperature profile, and so on, are not significantly affected at a low-power dissipation. [ABSTRACT FROM AUTHOR]

In this article, we present an analysis of the gate degradation induced by long-term forward gate stress in GaN-based power HEMTs with p-type gate, controlled by a Schottky metal-retracted/p-GaN junction. In particular, time-dependent gate breakdown and threshold voltage instability are investigated as function of different geometries, gate biases, and temperatures. The introduction of a gate metal retraction (GMR) process step improves the device lifetime because it suppresses the onset of the leakage current flow occurring at the gate edges for relatively high gate voltage. However, biasing GMR p-GaN HEMT at ${V}_{\text {G}} > {8}$ V and T > 80 °C, a new degradation mechanism shows up, possibly altering the lifetime even at low ${V}_{\text {G}}$ operation. Main results in this article demonstrate that although at high ${V}_{\text {G}}$ and high $T$ , a localized degradation effect ascribed to the device isolation region is responsible for time-dependent gate breakdown, thanks to GMR higher operating voltages compatible with ten-year continuous operation is attained. Finally, the longer device lifetime at moderate ${V}_{\text {G}}$ values brought by GMR allows evaluating the threshold voltage instability for long stress times (≈112 h) at relatively high ${V}_{\text {G}}$ and high T, leading to the observation of a saturation of the long-term positive threshold voltage shift and providing additional information about the underlying physical degradation mechanisms. Overall, the saturated 0.65-V $\Delta {V}_{\text {TH}}$ under worst-case condition (${V}_{\text {G}} = {7}$ V at 150 °C, i.e., corresponding to ten-year lifetime) reveals a reliable and fairly stable technology with respect to forward gate stress. [ABSTRACT FROM AUTHOR]

Self-heating in fully depleted silicon-on-insulator (FDSOI) metal–oxide–semiconductor field-effect transistors (MOSFETs) is experimentally studied using the gate resistance thermometry technique, in a wide temperature range from 300 down to 4.2 K. We demonstrate that below 160 K, the channel temperature increase ($\Delta {T}$) due to self-heating starts to deviate significantly from the linear variation with the dissipated power, leading to an apparent power dependent thermal resistance. This power dependence is interpreted in terms of temperature dependent thermal conductivity. The thermal resistance dependence on the active device temperature (${T}_{\text {Device}}$) indicates that the former one is mainly driven by the thermal conductivity of the oxide layer. Moreover, based on this dependence we reconstructed the channel temperature increase for each dissipated power and ambient temperature, and we found that the calculated values were in a good agreement with the experimental ones. Results indicate that even at low temperatures, thermal resistance does not depend significantly on the silicon channel thickness (ranging from 7 up to 24 nm), whereas the buried-oxide thinning (145 and 25 nm) strongly reduces the magnitude of the thermal resistance. Finally, this paper intends to fill the gap of experimental data concerning self-heating in advanced FDSOI transistors at low temperatures, revealing limitations and perspectives that should be taken into account for future work. [ABSTRACT FROM AUTHOR]