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The time resolution of active pixel sensors whose timestamp mechanism is based on time-to-digital converters is critically linked to the accuracy in the distribution of the master clock signal that latches the timestamp values across the detector. The clock distribution network (CDN) that delivers the master clock signal must compensate process–voltage–temperature variations to reduce static time errors (skew) and minimize the power supply bounce to prevent dynamic time errors (jitter). To achieve sub-100-ps time resolution within pixel detectors and thus enable a step forward in multiple imaging applications, the network latencies must be adjusted in steps well below that value. Power consumption must be kept as low as possible. In this work, a self-regulated CDN that fulfills these requirements is presented for the FastICpix single-photon detector aiming at a 65-nm process. A 40-MHz master clock is distributed to 64 × 64 pixels over an area of 2.4 × 2.4 cm2 using digital delay-locked loops, achieving clock leaf skew below 20 ps with a power consumption of 26 mW. Guidelines are provided to adapt the system to arbitrary chip area and pixel pitch values, yielding a versatile design with very fine time resolution. [ABSTRACT FROM AUTHOR]