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High-performance germanium (Ge) lateral PIN photodetector (PD) arrays for short wave infrared (SWIR) imaging based on Ge-on-insulator (GOI) platform was proposed and demonstrated. The high-quality GOI platform with top-Ge layer thickness of 1.25 μ m and threading dislocation density of less than 105 cm−2 was prepared by using bonding and smart-cut technology. P -type and N -type regions with centrosymmetric racetrack shapes were introduced to lower the sidewall electric field and suppress the surface leakage current of the PD. Benefiting from the high-quality of the GOI platform and the unique design of lateral active regions, a low dark current of 2 nA under −1 V with outstanding rectification ratio of 2.1 × 106 were obtained at room temperature. Through constructing a vertical resonant cavity by SiO2 passivation layer and the Si/SiO2 substrate, the responsivity at 1550 nm was enhanced to 0.46 A W−1 with a high specific detectivity of 3.09 × 1010cm·Hz1/2 ·W−1 under −1 V. Ultimately, SWIR imaging was demonstrated by a Ge lateral PIN PD line array with 1 × 8 pixels under zero bias at room temperature. The results indicate that the proposed lateral Ge PD structure holds great application potential in the field of SWIR imaging. [ABSTRACT FROM AUTHOR]

[Display omitted] • Bonding interface is modified to a homogenous one with an epitaxial layer. • Epitaxial layer constrains the defects, disperses and reduces the heterogenous mismatch stress. • Epitaxial layer is doped to reduce the carrier recombination leakage current in this defect-rich layer. In the realm of optoelectronic integration, silicon-based Ge bonding has attracted great attention due to its advantages in short-wave infrared response and low cost. However, owing to the inherent lattice mismatch and thermal mismatch between Ge and Si, the bonded Ge-Si heterogenous interfaces encountered problems of thermal instability and high interface states. Herein, an approach of separating the bonding interface from the heterogenous interface is proposed through inserting a Ge epitaxial layer (GeEL) between the Si substrate and Ge film. This separation modifies the bonding interface to a homogenous one, alleviating the massive mismatch stress and achieving film relaxation, enhancing bonding stability in all aspects. Moreover, during 850 °C annealing, GeEL is doped via diffusion hence realizes electric filed modulation, inhibiting the carrier recombination leakage current and trap assisted tunneling in this defect-rich layer. A Ge-Si heterogenous PIN diode prepared by this bonding method has achieved a remarkable low dark current density (1.33 mA/cm2), a low ideality factor (1.11), and a high on–off ratio (1 0 6), confirming the outstanding quality of the bonded heterojunction. This work provides great prospects for higher performance, larger scale and multi-functional Si-based heterogenous material device applications. [ABSTRACT FROM AUTHOR]

We report a comparison of the Ge/SOI wafer bonding by amorphous Ge (a-Ge) and polycrystalline Ge (poly-Ge) interlayers. The Ge layer exfoliation and high-temperature annealing is used to fabricate high-quality SOI-based Ge film. The crystalline state evolution, bubble evolution, and dislocation evolution at the wafer-bonded interface are investigated. The related elimination mechanisms of bubbles and dislocations are revealed. Besides, the repairing of the point defects in the exfoliated Ge film stemmed from the H ion implantation is also demonstrated. For the a-Ge wafer bonding, when the SOI-based exfoliated Ge film is annealed at high temperature to repair the point defects, the bubbles and dislocations form at the bonded interface due to the lattice mismatch and lacking of gas transport channel ascribed to the crystallization of a-Ge (single-crystal Ge). However, for the poly-Ge wafer bonding, the poly-Ge layer not only can serve as a perfect lattice blocking layer due to its inconsistent crystal orientation, but can act as a perfect gas transporter to absorb bubbles thanks to its porous structure. The bubbles and TDs can be eliminated at high temperature during the repairing of the point defects, which in turn improves the Ge film quality. • Ge/SOI bonding with semiconductor interlayer is proposed to fabricate SOI-based Ge film. • poly-Ge interlayer is an excellent gas transporter to eliminate the bubbles. • The lattices of Ge/Si is isolated by poly-Ge, eliminating the dislocation nucleation. • The point defects in H+-implanted Ge film are repaired after high-temperature annealing. • Above three results lead to the improvement of the Ge film quality at high temperature. [ABSTRACT FROM AUTHOR]