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In this paper, we have demonstrated a plasma activated low-temperature die-level oxide-oxide direct bonding with advanced wafer dicing technologies. This evaluation used blanket 300-mm silicon wafers. $1\ \mu\mathrm{m}$ Tetraethyl orthosilicate (TEOS) oxide was deposited by plasma-enhanced chemical vapor deposition (PECVD) directly on the silicon (Si) wafer surface, followed by chemical mechanical planarization (CMP). Atomic Force Microscopy (AFM) was used to examine the roughness of the wafer surface before dicing and it showed $\mathrm{R}_{\mathrm{a}}$ . Several dicing technologies such as diamond blade dicing, step-cut blade dicing, bevel blade dicing, and stealth laser dicing were evaluated for this integration scheme. In the end, diamond blade dicing has the most compatibility with many materials, but it led to large chipping on the edges of the die. Stealth laser dicing achieves edge chipping of less than $2\ \mu\mathrm{m}$ , which is the least amount of damage among of all dicing methods tested in this study. In the bonding test, the 10 mm square silicon die was bonded to a 35-mm square silicon substrate. Both silicon die and substrate are of thickness $760\ \mu\mathrm{m}$ . Prior to direct oxide-oxide bonding, both silicon die, and substrate went through a two-step cleaning process. The detailed process of the plasma activated die-level direct bonding is discussed.

Understanding and simulating 3D doping performed by Plasma Immersion Ion Implantation on FinFETs or on deep trenches for flash memories or power devices applications is a key topic to optimize process parameters and to forecast effect of form factor evolution requested by technology scaling. In this work, we developed a model based on the following strategy.1-Calculation of angle and energy distribution of ions and neutrals reaching wafer surface as function of PIII process parameters (TRIM Monte Carlo simulation in gases)2-Calculation of local ion distributions (quantity, angle and energy distribution) along the top, walls and bottom of Fins or trenches based on simple geometrical model with shadowing effect.3-Calculation of local in depth dopant distribution on all points of the structure based on TRIM Monte-Carlo simulation4-Recalculation of mean concentration profile and comparison with 1.5D SIMS.Effect of main process parameters (plasma density and pressure) is shown as well as geometrical parameters of doped structures (aspect ratio, tapering angle). After having compared the model to experimental data, impact of geometrical changes due to technology scaling is discussed (fin pitch for Finfet application, form factor for trench doping applications)

Self-aligned contact (SAC) is required for 7 nm node to reduce susceptibility of contact-to-gate short failures. This requires forming a SAC cap on metal-recessed gate. The SAC cap formation is usually achieved by removing nitride on the field by planarization techniques such CMP (chemical mechanical polishing) or GCIB (gas cluster ion beam) processes. Significant gate stack height variation can be observed lot-to-lot and wafer-to-wafer due to accumulated variations from multiple steps, including several CMP steps, before the SAC cap module, especially during early research and development prior to full optimization of the steps before the SAC cap module. GCIB potentially offers a method by which the early development stage variation due to CMP steps can be reduced, allowing integration and device learning during the early stages of a program. This study shows a comparison of SAC cap formation by CMP only vs. GCIB with integrated metrology enabled location specific processing. By using GCIB with feed-forward scatterometry measurements taken from a 2D measurement pad we have been able to significantly improve both lot-to-lot and wafer-to-wafer variation on early development wafers. This has led to improvement in within wafer SAC cap thickness non-uniformity, wafer to wafer and lot to lot device yield for gate-contact over a CMP-only process flow.

For high-volume production of 3D-stacked chips with through-silicon-vias (TSVs), wafer-scale bonding offers lower production cost compared with bump bond technology and is promising for interconnect pitches smaller than 5 µ using available tooling. Prior work has presented wafer-scale integration with tungsten TSV for low-power applications. This paper reports the first use of low-temperature oxide bonding and copper TSV to stack high performance cache cores manufactured in 45 nm Silicon On Insulator-Complementary Metal Oxide Semiconductor (SOI-CMOS) embedded DRAM (EDRAM) having 12 to 13 copper wiring levels per strata and upto 11000 TSVs at 13 µm pitch for power and signal delivery. The wafers are thinned to 13 µm using grind polish and etch. TSVs are defined post bonding and thinning using conventional alignment techniques. Up to four additional metal levels are formed post bonding and TSV definition. A key feature of this process is its compatibility with the existing high performance POWER7™ EDRAM core requiring neither modification of the existing CMOS fabrication process nor re-design since the TSV RC characteristic is similar to typical 100–200 µm length wiring load enabling 3D macro-to-macro signaling without additional buffering Hardware measurements show no significant impact on device drive and off-current. Functional test at wafer level confirms 2.1 GHz 3D stacked EDRAM operation.

This paper provides a comparison of bonding process technologies for chip and wafer level 3D integration (3Di). We discuss bonding methods and comparison of the reflow furnace, thermo-compression, Cavity ALignment Method (CALM) for chip level bonding, and oxide bonding for 300 mm wafer level 3Di. For chip 3Di, challenges related to maintaining thin die and laminate co-planarity were overcome. Stacking of large thin Si die with 22 nm CMOS devices was achieved. The size of the die was more than 600 mm 2 . Also, 300 mm 3Di wafer stacking with 45 nm CMOS devices was demonstrated. Wafers thinned to 10 μm with Cu through-silicon-via (TSV) interconnections were formed after bonding to another device wafer. In either chip or wafer level 3Di, testing results show no loss of integrity due to the bonding technologies.

For high-volume production of 3D-stacked chips with through-silicon-via (TSVs), wafer-scale bonding offers lower production cost compared with bump bond technology [1][2][3] and is promising for interconnect pitch

300mm Si wafer-scale oxide fusion bonding and mechanical/wet etch assisted wafer thinning processes were combined with a TSV-last 3D integration strategy to fabricate electrical open/short yield learning on through-wafer electrical TSV test chains.

In this work, Ru and RuO2 films have been investigated for potential applications in emerging CMOS gate electrode and memory capacitor bottom electrode applications. Films were deposited on SiO2 using chemical vapor deposition (CVD) and low power plasma assisted CVD (PACVD) in a 200-mm wafer deposition cluster tool using a metal beta-diketonate precursor [Bis (2,2,6,6-tetramethyl-3,5-heptanedionato) (1,5-cyclooctadiene) ruthenium (II)]. Hydrogen and oxygen were employed as the reactive gases to deposit, respectively, Ru and RuO2, over a wafer temperature range from 320°C to 480°C. The resulting film properties were analyzed using cross-sectional scanning electron microscopy (CS-SEM), four point resistance probe, x-ray photoelectron spectroscopy (XPS), Rutherford backscattering spectrometry (RBS) and x-ray diffraction (XRD). Both Ru and RuO2 films could be deposited with minimal carbon concentration (∼5 at. %). The purity of the films was also reflected in the as-deposited resistivity of the films, which was as low as 47 μΩ-cm, and was strongly dependent on processing conditions. In order to assess thermal stability, the films were subsequently annealed in forming gas and oxygen ambients for 60 min at 650°C. It was observed that, generally speaking, CVD RuO2 films were stable, with respect to resistivity, in oxidizing ambients, while annealing in a reducing ambient resulted in significant film densification and reduction of the film resistivities to as low as 43 μΩ-cm. Ru films demonstrated good adhesion after anneals in oxidizing, but not in reducing ambients.