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5.2-GHz all-digital frequency synthesizer implemented proposed reference spur reducing with the tsmc 0.18 µm CMOS technology is proposed. It can be used for radar equipped applications and radar-communication control. It provides one ration frequency ranged from 4.68 GHz to 5.36 GHz for the local oscillator in RF frontend circuits. Adopting a phase detector that only delivers phase error raw data when phase error is investigated and reduces the updating frequency for DCO handling code achieves a decreased reference spur. Since an all-digital phase-locked loop is designed, the prototype not only optimized the chip dimensions, but also precludes the influence of process shrinks and has the advantage of noise immunity. The elements of novelties of this article are low phase noise and low power consumption. With 1.8 V supply voltage and locking at 5.22 GHz, measured results find that the output signal power is −8.03 dBm, the phase noise is −110.74 dBc/Hz at 1 MHz offset frequency and the power dissipation is 16.2 mW, while the die dimensions are 0.901 × 0.935 mm2. [ABSTRACT FROM AUTHOR]

ABSTRACT A 2.4-GHz integer-N frequency synthesizer is implemented in TSMC 0.18-μm CMOS process. This article proposes a charge pump (CP) linearization technique and uses a current-switching differential Colpitts VCO to lower the phase noise and an averaged varactor circuit to increase the linearity of the VCO tuning range. A three phase sample-hold-reset loop filter that isolates the CP output node from the VCO tuning node, which improves synthesizer spur performance, minimizes phase noise and reduces on-chip capacitors area. At 1.8 V supply voltage, measured results of the proposed prototype achieves a wide tuning range from 2.24 to 2.42 GHz, corresponding to 7.7%, a phase noise of −114.76 dBc/Hz at 1 MHz offset frequency from 2.4 GHz, a power consumption of 13.6 mW and an output power of −8.43 dBm. Including pads, the chip area only occupies 0.849 (0.899 × 0.944) mm2. © 2014 Wiley Periodicals, Inc. Microwave Opt Technol Lett 56:2591-2598, 2014 [ABSTRACT FROM AUTHOR]

A fully integrated, 5.6 GHz low-phase noise Colpitts quadrature voltage-controlled oscillator (VCO/QVCO) is presented. This QVCO is a complementary cross-coupled voltage-controlled Colpitts oscillator with a three-bit switched capacitor array parallel to the inductor to form LC-resonant tank and was implemented in TSMC 0.18 μm CMOS technology with 1.8 V supply voltage. Without buffer circuits, measured results achieve a tunable frequency range from 4.81 to 5.75 GHz, corresponding to 17.8%, a phase noise of −121 dBc/Hz at 1 MHz offset frequency from 5.64 GHz, while the QVCO draws 3.8 mA current and 6.84 mW consumption, respectively. Including pads, the chip area is 1.046 mm2 (1.35 × 0.775 mm2). The output power is −10.04 dBm with 50-Ω termination at the frequency of 5.64 GHz, and the calculated figure of merit is −187.7 dBc/Hz. © 2013 Wiley Periodicals, Inc. Microwave Opt Technol Lett 55:1490-1493, 2013; View this article online at wileyonlinelibrary.com. DOI 10.1002/mop.27629 [ABSTRACT FROM AUTHOR]

This paper proposes a novel Gm-C loop filter instead of a conventional passive loop filter used in a phase-locked loop. The innovative advantage of the proposed architecture is tunable loop filter bandwidth and hence the process variations of passive elements of resistance R and capacitance C can be overcome and the chip area is greatly reduced. Furthermore, the MASH 1-1-1 sigma-delta (ΣΔ) modulator is adopted for performing the fractional division number and hence improves the phase noise as well. Measured results show that the locked phase noise is -114:1 dBc/Hz with lower Gm-C bandwidth and -111:7 dBm/C with higher Gm-C bandwidth at 1 MHz offset from carrier of 5.68 GHz. Including pads and built-in Gm-C filter, the chip area of the proposed frequency synthesizer is 1.06 mm2. The output power is -8:69 dBm at 5.68 GHz and consumes 56 mW with an off-chip buffer from 1.8-V supply voltage. [ABSTRACT FROM AUTHOR]