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In this research, we present a low phase noise (PN) and wide tuning range 175 GHz inductors and capacitors (LC) voltage-controlled oscillator (VCO) based on a differential Colpitts oscillator that was designed using a 0.13 μm bipolar complementary metal oxide semiconductor (BiCMOS) and simulated. The square of the tank Q-factor and the square of the oscillation amplitude were both maximized to reduce PN. With an extensive examination of parasitic, mathematical analysis of load impedances, and implementation of differential design, the PN was reduced, and the output power was enhanced. Using a supply voltage of 1.6 V, the VCO consumes 41.9 mA, resulting in a total power usage of 67 mW to prevent undesirable PN deterioration, an inter-stage LC filter at the VCO-buffer interface increases the swing at the buffer input. To make a better output, a buffer is used to isolate the load from the VCO core. In addition, the VCO has a high linearity and the overall, the VCO presented in this study demonstrates excellent performance and has the potential to be used in a wide range of applications that require a high-performance, low-power VCO.

A GaAs Colpitts voltage controlled oscillator with low phase noise is presented in this brief. Firstly, the ${g} _{\mathrm{ m}}$ -boosting technique realized by an inductor located at the emitter of heterojunction bipolar transistor is applied to relax the oscillation start-up requirements and speed up the oscillation. Moreover, a Collector-Emitter cross-coupling capacitor is adopted to improve the loaded quality factor and oscillation amplitude of the tank by reducing the transformer ratio, which improves the phase noise in turn. Finally, in proof of the concept, a voltage controlled oscillator prototype is fabricated and designed in 2- ${\mu }\text{m}$ GaAs HBT process. The measured results demonstrate a phase noise of −137.44 dBc/Hz at 1MHz offset with figure of merit of −192dBc/Hz and a tuning frequency bandwidth from 3.25 to 3.4GHz. Compared with the conventional Colpitts voltage controlled oscillator, the phase noise of the proposed voltage controlled oscillator with ${g} _{\mathrm{ m}}$ -boosting and Collector- Emitter cross-coupling techniques has been improved 6.67 dB.

This article describes a wideband low-noise frequency synthesizer implemented in 0.13- $\mu \text{m}$ SiGe BiCMOS process for 5G millimeter-wave applications. To extend the frequency range while reducing the phase noise, a fundamental voltage-controlled oscillator (VCO) array including four Colpitts VCO cores with switchable bias circuits is adopted in the proposed frequency synthesizer. A ring-oscillator-based injection locked frequency divider is utilized as the wideband divide-by-2 prescaler, and its bandwidth is optimized based on a new injection-locked behavior model. This fabricated frequency synthesizer can be locked in a range from 23 to 36.8 GHz (46.2%) by a 100-MHz step. It achieves a phase noise of −94.7 dBc/Hz at the 1-MHz offset and an output power of −3.5 dBm measured at 36.8 GHz. The chip consumes 360.6 mW from 3.3 and 1.8 V supplies and has an area of $2.7\times3.1$ mm2.

This paper presents a novel co-optimization configuration to simultaneously improve phase noise and FoM in order to solve the long-existing issue of excellent phase noise and mediocre FoM in the light of GaAs technologies. Considering traditional GaAs based Colpitts/class-C VCOs, a first step is taken with the introduction of noise shifting structure while a second step is carried out with the presentation of Darlington pair. Afterwards, a detailed outline of pros and cons of five VCO topologies, including Colpitts/class-C/noise shifting (NS) Colpitts/noise shifting class-C/noise shifting Darlington-based (NSDB) class-C VCO, is given in theory and in practice while respective start-up conditions and capacitive feedback factors are derived mathematically. It can be found that iterative phase noise and FoM improvement is achieved in GaAs based VCOs above in a gradual manner. Furthermore, the output power is stabilized with a simple trick of two-stage Darlington-based topology and thus, the power-hungry buffer is avoided. Ultimately, three VCOs out of the five are fabricated in GaAs technologies while their specifications are thoroughly compared with previous research. The fabricated Colpitts VCO demonstrates a frequency tuning range of 3.59–3.69 GHz with a current consumption of 11.2 mA@5 V supply, a phase noise of − 130.1 to − 129.1 dBc/Hz at 1 MHz offset from the carrier and the output power is around − 5 to − 5.1 dBm. The fabricated noise shifting Colpitts VCO demonstrates a frequency tuning range of 3.58–3.67 GHz with a current consumption of 10.8 mA@5 V supply, a phase noise of − 132.4 to − 130.2 dBc/Hz at 1 MHz offset from the carrier and the output power is around − 2.5 to − 3.5 dBm. The fabricated Darlington-based class-C VCO demonstrates a frequency tuning range of 2.76–2.91 GHz with a current consumption of 9.5 mA@5 V supply, a phase noise of − 138.6 to − 135.9 dBc/Hz at 1 MHz offset from the carrier and the output power is around − 3.06 to − 4.18 dBm. To the best of the authors’ expertise, the proposed Darlington-based class-C VCO achieves both exceptional phase noise and FoM, which far outweigh that of existing GaAs ones.

This letter presents a negative conductance ( $G_{m}$ )- and swing-enhanced Colpitts voltage-controlled oscillator (VCO) based on optimization of the capacitance ratio. In the proposed VCO structure, a current source typically used in conventional VCOs is replaced with an inductor to increase the output voltage swing. A current-reuse configuration is also adopted to decrease power consumption. Theoretical analyses and simulations show that the devised VCO with an optimized capacitance ratio exhibits enhanced $G_{m}$ and swing when compared to a conventional VCO. Measurements revealed a phase noise of −129.67 dBc/Hz at a 1-MHz offset frequency from the 2.2-GHz carrier, while power consumption was 2.2 mW from a 1.2-V supply voltage. This resulted in a figure-of-merit of −193.1 dBc/Hz. The proposed device was implemented using a 65-nm CMOS process.

This study presents a new low-power and low-phase noise Colpitts quadrature voltage-controlled oscillator (QVCO). The proposed QVCO contains two differential Colpitts voltage-controlled oscillators (VCOs) that use gain-boosting technique to enhance the negative transconductance and relax start-up condition. Both switching and tail transistors are configured in class-C to improve impulse sensitivity function and phase noise performance of the circuit via better noise modulation function. In addition, flicker noise would be reduced because of the switched-biasing mechanism of tail transistors. Phase noise analysis shows that changing the bias voltage of switching as well as tail transistors can improve the phase noise performance of the core VCO with overlap reduction of the transistors active time. Consequently, due to no extra noisy elements for coupling and class-C biasing of all transistors, low-phase noise quadrature signals are generated. To verify the performance of the proposed technique, post-layout simulation is performed in Taiwan Semiconductor Manufacturing Company (TSMC) of 0.18 μm Radio Frequency-Complementary Metal-Oxide- Semiconductor (RF-CMOS) process at a supply voltage of 1.2 V. Post-layout simulation results show that the phase noise of the proposed QVCO is −120.6 dBc/Hz at 1 MHz offset from 5.73 GHz operation frequency. The total power consumption of the QVCO is 3.1 mW and the tuning range is from 5 to 5.73 GHz.

Nowadays, terahertz and sub-terahertz frequencies are experiencing a significant interest from both academic and industrial world, since they offer a wide and unused spectrum available for different applications, as high-throughput communications, efficient imaging systems and medical uses. In this work an innovative sub-THz voltage-controlled oscillator (VCO) realized with a 130-nm SiGe process is proposed and described in detail. The technology is the SG13G2 bipolar-complementary-metal-oxide-semiconductor (BiCMOS) provided by IHP foundry. The signal source is conceived for high-resolution THz imaging camera; at design level it has been defined with a push-push architecture and adopts an oscillator core based on a Colpitts topology. State-of-the-art performance has been obtained thanks to the proposed design choices that are uncommon at these frequencies, as for instance, the VCO output taken from the common base node, the use of varactors in anti-series connection and the possibility to define a double output at different harmonic frequencies. These, as well as other innovative expedients, allow to simplify the integration at system level and to achieve compact sizes, very low power consumption and almost constant output power level over the full tuning bandwidth. A relative tuning range of about 5.5% has been obtained around a central frequency of 330 GHz, while the output power is about − 8 dBm with a maximum variation of 0.4 dB. Also the phase noise of − 110 dBc/Hz at 10 MHz offset is very promising. Measurements over different chip samples demonstrate the robustness of the proposed solution and the reliability of the design.

A wide-band push–push common-collector Colpitts voltage-controlled oscillator (VCO) using impedance peaking network and gain enhancing technique is proposed in this work. The impedance peaking network is introduced to increase the coupling factor of the differential inductor in the inductor capacitor (LC) tank without sacrificing the quality factor. The impedance peaking technique could guarantee the push–push VCO unconditionally oscillating in a differential mode without degrading the phase noise performance. The gain enhancing technique employs an LC resonator in series with the emitter degeneration resistor in the common-collector amplifier in the VCO core to improve the VCO oscillating amplitude and then improve the phase noise performance. The proposed VCO oscillates at around 20 GHz with >10.5% frequency tuning range from 18.9 to 21.4 GHz across temperature from −40 to 125°C. The measured phase noise is lower than −107 dBc/Hz at 1 MHz offset across the entire working temperature (−40 125°C). The whole VCO dissipates 45 mA under 3.3 V power supply, and the typical figure of merit is around −177.92.

In this letter, an improved balanced Colpitts voltage-controlled oscillator (VCO) with a collector–emitter cross-coupled capacitors is presented. The proposed Colpitts structure can introduce a more robust oscillation startup condition. The noise-shifting technique is used to enhance the loaded quality factor of the tank, which improves the phase noise in turn. In addition, three-bit switches composed of enhancement-mode high-electron mobility transistors (E-HEMTs) are utilized to expand the tuning range and reconfigurability of the proposed VCO. In proof of the concept, a VCO prototype is fabricated in a GaAs BiHEMT [enhancement- and depletion-mode high-electron mobility transistor (E/D-PHEMT)] process. The measured results demonstrate the best phase noise of −139.46 dBc/Hz at 1-MHz offset. To the best of our knowledge, this is the lowest phase noise among the reported ones fabricated on-chip with a similar frequency band, and it achieves a wide tuning frequency bandwidth of 21% (2.65–3.27 GHz) with peak figure of merit (FoM) of −192.26 dB and FOMT of −198.8 dB.

This article proposes a low voltage, optimized tuning range and phase noise voltage-controlled oscillator (VCO) adopting colpitts architecture and using gm boosting technique for 5.8 GHz applications. Measured consequences of the Colpitts VCO circuit exhibit the tuning range of 5.29 to 6.07 GHz as well as phase noise of -123.4 dBc/Hz at 1 MHz frequency offset and product power of -6.67dBm under 5.73 GHz. The power consumption of the core circuit is 4.7mW from supply voltage of 1V. The proposed overall chip (die size = 0.6 x 0.6 mm2) is fabricated in tsmc 0.18μm CMOS 1P6M process.

This paper presents a W-band push-push VCO design and implementation in 90-nm CMOS technology, which is expected to be used for a 94-GHz RF transceiver. The proposed VCO adopts a differential Colpitts topology with the drain to source (DS) feedback operating at fundamental frequency. This VCO is biased by a current-switching transistor pair with dynamic forward-body biasing technique. Thus, the negative conductance of VCO can be enhanced for reliable start-up. A greater W-band signal can be obtained by a g m -boosted doubler. In addition, the current-reuse technique realizes low power design. The center frequency of proposed VCO is 90.1 GHz with the tuning range of 2.24 %. This VCO provides the highest frequency of 91.11 GHz and the corresponding output power of -0.2 dBm. The VCO consumes 25.43 mW from a 1.8-V supply and exhibits the phase noise of -109.22 dBc/Hz and FOM of -174.3 at 10 MHz offset.

A low voltage, and phase noise Colpitts voltage-controlled oscillator (VCO) with even harmonic mixer and balun for 5.8-GHz-band application is proposed and implemented in tsmc 0.18-um CMOS process. The proposed VCO has two main features; 1.0 V low supply voltage, and using two single-ended complementary Colpitts LC circuits. Measured results achieve tuning range of 5.17 to 5.97 GHz, corresponding to 14.6%, phase noise of -117.57dBc/Hz at 1 MHz offset from 5.8 GHz while the tuned control voltage is adjustable from 0 to 1.0V and output power of -8.97 dBm at 50$- \Omega$ termination. The power consumption of core circuit is 3.58 mW and the VCO chip dimension including pads is 0.40 (0.71x0.56)mm2. The proposed even harmonic mixer with four phase local oscillator switching mixer adopts a conversion power gain of 0.98 to 5.76 dB, LO power of -9dBm, input $\mathrm{P}_{{\mathrm {1dB}}}$ of -12 to- 17 dBm, IIP3 of -10.7 to 0.16 dBm, LO-RF isolation of 34 dB, respectively.

This paper describes a 22-to-36.8 GHz low phase noise Colpitts voltage-controlled oscillator (VCO) array using 0.13-μm SiGe BiCMOS technology. The VCO array consists of four Colpitts VCO cores and three millimeter-wave (MMW) selectors. In the VCO core, in order to achieve the best phase noise and power consumption trade-off, an optimization method based on symbolic expressions is presented. In a further research, a switchable bias current technique is proposed to achieve lower phase noise. The MMW selectors are designed to select the desired VCO core and cover the whole frequency band with sufficient output power. The fabricated VCO array features a wide tuning range of 50.3%, low phase noise between −100.7 dBc/Hz and −95.3 dBc/Hz at 1 MHz offset and high output power of 4.5 dBm, which results in the FOMT between −183.2 dBc/Hz and −177.8 dBc/Hz.

A Colpitts voltage-controlled oscillator (VCO) is presented for low-power and low-phase-noise applications. The current efficiency of the proposed VCO is improved through ${g} _{{m}}$ -enhanced and current-reuse techniques. In addition, a clover-shaped inductor is employed to mitigate electromagnetic interference (EMI) effects. The VCO is implemented in a 0.18- ${ \mu }\text{m}$ CMOS process and is shown to operate at frequencies of 2.34 to 2.55 GHz with a tuning range of 8.6%. The prototype has a power dissipation of 1.4 mW and achieves a phase noise of −122.85 dBc/Hz at a 1 MHz frequency offset.

This paper presents an architecture for differential Colpitts voltage-controlled oscillators (VCOs) in complementary metal–oxide–semiconductor (CMOS) that utilizes three design techniques to extend the tuning range (TR) of the VCO, while maintaining a low phase noise (PN) and a low power consumption. First, a switched-capacitor bank based on a variable capacitive feedback technique is introduced to achieve a wide TR with a minimal PN degradation. Second, a $G_{m}$ -boosting technique using interstage inductors is employed to lower the power consumption and relax VCO startup issues. Third, a dynamic forward-body self-biased technique is used to further reduce the power consumption and PN of the proposed structure. As a proof of concept, a 26.3-GHz differential Colpitts VCO is designed and fabricated in a 65-nm CMOS process. Based on the measurement results, the VCO achieves a PN of −122.1 dBc/Hz at 10-MHz offset from the center frequency, and a TR of 20%. The circuit consumes 2.3 mW from a 1-V supply and excluding the pads occupies a 0.22 mm2 of silicon area. Compared to the recently published CMOS VCOs within the same frequency range, the proposed VCO simultaneously achieves a wide TR, low power dissipation, and low PN, resulting in a figure of merit (FOM) and FOM incorporating the TR (FOM $_{T}$ ) of −187 and −193 dBc/Hz at 10-MHz offset from the center frequency, respectively.

This work presents the design of a new low-voltage Colpitts LC quadrature voltage controlled oscillator (LC-QVCO). The proposed QVCO consists of two identical differential Colpitts VCOs in which gm-boosting techniques are employed to improve the start-up condition of oscillation. The QVCO is designed based on the first-harmonics coupling with the mechanism of “in-phase anti-phase” manner. To give more insight into the performance of the proposed QVCO, the behavior of the core VCOs are investigated. In addition, the proposed QVCO is theoretically analyzed to show that the output voltages of the circuit are in quadrature. The QVCO operates at 4.8 GHz with the phase noise of −117 dBc/Hz at 1 MHz offset frequency. Finally, as a proof of concept, the prototype circuits of the proposed VCO and some popular Colpitts VCOs are fabricated at the frequency of about 1.11 MHz to validate the theoretical results. The measurement results are summarized to demonstrate the main features of the proposed oscillator.

A balanced Colpitts voltage controlled oscillator (VCO) topology with its two implementations in a GaAs heterojunction bipolar transistor (HBT) process is introduced in this paper. A detailed analysis of phase noise, originating from the work by Hajimiri and Lee, is given, which depicts a specific outline of the phase noise generation mechanisms in GaAs HBT based harmonic oscillators including LC cross coupled/Colpitts/class C VCOs. In addition, phase noise expressions for HBT based VCOs are derived, compared and act as an optimization tool in oscillator designs. The theoretical analysis of phase noise is authenticated with two balanced Colpitts VCOs with their respective center oscillation frequencies of 850 MHz and 1670 MHz, which are fabricated in a 2 µm GaAs HBT H20HL process. Measurement results show a phase noise of − 139 dBc/Hz at 1 MHz offset from an 850 MHz carrier and a phase noise of − 134 dBc/Hz or less at 1 MHz offset from a 1700 MHz carrier. The output power variation is less than 0.5 dBm over the tuning range. A relatively good match between numerical simulation and measurements is observed.

This article presents a low phase noise voltage-controlled oscillator (VCO) adopting optimization colpitts with gm boosting techniques. The excellent performance of the VCO core adopts a phase noise of −123.4 dBc/Hz at 1MHz offset frequency and output power of −6.67dBm from a 5.73 GHz carrier with a 4.7mW power consumption, achieving in an excellent FOM of −191.84 dBc/Hz and displayed by FOMT of −194.61 dBc/Hz. The proposed folded-current mirror mixer produces a conversion power gain of −3 ∼ 0.8 dB, input P1dB of −6 ∼ −4 dBm, IIP3 of −1.4 ∼ 1.8 dBm, LO-RF isolation of 30 dB, respectively. The overall prototypes of colpitts oscillators with folded-current mirror mixer have been fabricated in tsmc $\mathrm{0.18}\mu\mathrm{m}$ CMOS 1P6M process and implemented from supply voltage of 1V.

Growing importance of wireless communication systems forces reduction of power consumption of the designed integrated circuits. The paper focuses on minimization of power consumption in a digitally controlled oscillator (DCO) that can be employed as oscillator in GPS/Galileo receiver. The new hybrid architecture of DCO combines good phase noise performance of a Colpitts oscillator and relaxed startup conditions of a cross-coupled differential pair oscillator. The proposed new DCO generates a quadrature signal in a current reused frequency divider. Such solution allows of the dissipated power to be reduced. The DCO has been implemented in 110 nm CMOS technology. It generates output signal in frequency range from 1.52 GHz to 1.6 GHz and consumes 1.1 mW from 1.5 V supply voltage. The measured phase noise equals −116 dBc/Hz at 1 MHz offset from 1.575 GHz output signal.

A 31.4-39.9GHz mmWave PLL synthesizer for FMCW radar applications is proposed that consists of a complementary Colpitts-assisted class-B/C VCO, a programmable quadratic-curved charge pump, and a digital chirp-code generator. The complementary Colpitts oscillator is employed to supply more negative resistance around 40GHz. The charge pump produces quadratic-curved current to keep loop bandwidth constant. The fractional-N PLL synthesizer achieves locking range of 31.4-39.9GHz, a minimum FM rms error of 160 kHz, a high-speed chirp rate of 50μs, and a maximum FM modulation bandwidth of 8.5 GHz. The PLL implemented by using 65nm CMOS process accomplishes phase noise of -89dBc/Hz at 1MHz offset from 33.9GHz and consumes 60mW.

A new fully integrated CMOS voltage-controlled oscillator (VCO) is presented. The VCO is composed of cross-coupled Colpitts negative resistance cell in shunt with a parallel-tunerd LC resonator and was implemented in 90 nm CMOS technology. The negative resistance cell uses bias-free pMOS tail for low-phase noise design. With the supply voltage of1.15 V, the VCO is tunable from 18 GHz to 20.25 GHz while the tuning voltage varies from 0V to 1.4 V. The phase noise of the VCO operating at 18 GHz is -117.34 dBc/Hz at 1 MHz offset, while the VCO draws 7.07 mA and uses 8.13 mW consumption.

This paper presents a high efficiency gate inductive feedback Colpitts Voltage Controlled Oscillator (VCO) operating near 90 GHz. It includes multi-way transformers at the load, which helps to enhance the DC-to-RF efficiency with boosted impedance and extended voltage swing through drain-buffer and drain-source magnetic couplings. The proposed VCO is fabricated in a 65-nm CMOS process, and showed an oscillation frequency tuning range of 87.5-92.0 GHz (4.5 GHz). Over the frequency range, the output power and the dc power consumption exhibited values of −2.8 −1.7 dBm and 6-22.5 mW, respectively. The peak DC-to-RF efficiency was 9.4 %, and the corresponding phase noise was −107.4 dBc/Hz at 10-MHz offset. The lowest phase noise at the optimum bias condition was −116.7 dB/Hz at 10-MHz offset. The chip size is 400 ⨯ 300 μm2 excluding DC and RF pads.

This paper presents an 86-97 GHz transmitter (TX) using a wideband voltage-controlled oscillator (VCO) operating in 21.5-26 GHz range and frequency quadrupler (FQ) fabricated in SiGe BiCMOS technology. The VCO implements a self-buffered common-collector Colpitts topology with binary-weighted varactor ladder for low VCO gain ( $K_{VCO}$ ) and wide tuning range. Use of high-Q passive components and low-noise heterojunction bipolar transistors (HBT) results in worst-case phase noise of -92.8 dBc/Hz at 1MHz offset from the carrier. The VCO is loaded by a low-loss transformer that splitts the signal between frequency prescaling and multiplying blocks. The prescaler comprise three divide-by-two circuits (DTC) based on D flip-flops (D-FF) providing adequate feedback signal for an external phase-locked loop (PLL). The multiplying section consists of two cascaded Gilbert-cell frequency doublers driving a W-band power amplifier (PA). The TX achieves 0.2dBm output power at 92GHz and more than -2.8dBm in 86-97 GHz range consuming 60mA from 3.3V supply. The chip occupies 0.755 mm2 silicon area.

A customized structure of the Colpitts VCO for the 5G millimeter band is presented in this paper, this structure has a very low phase noise level compared to other structures published in the literature. Simulation results show that our VCO has a tuning range of 1.69 GHz around 28 GHz, an output power of 3.3 dBm and a phase noise around -123.2dBc/Hz at 1 MHz offset frequency from carrier. The VCO is designed in MMIC technology using the pHEMT transistor of PH15 process from UMS foundry.

In this chapter, we present a 300-GHz frequency synthesizer incorporating a triple-push VCO with a Colpitts-based active varactor (CAV) and a frequency divider with three-phase injection [24]. The synthesizer, implemented in 90-nm SiGe Bipolar complementary-metal-oxide-semiconductor (BiCMOS) with half of 240/315 GHz, achieves 7.9% of locking range (280.32-303.36 GHz) and generates -14 dBm of output power at 290 GHz. Based on the measurement result, the frequency -scaled phase noise of the 294.9-GHz signal is -77.8 dBc/Hz (-82.5 dBc/Hz) at the 100 -kHz (1 MHz) offset.

This paper presents and compares two inherently different LC-VCO architectures for the down-conversion in a offset-PLL. The cross-coupled VCO architecture, which is unpopular in mmW SiGe applications, is compared to the commonly used Colpitts architecture. The two VCOs are fabricated with a supply voltage of 3.3 V in a modern 130 nm SiGe BiCMOS technology with HBTs offering an $f_{\mathrm{T}}$ of 250 GHz and $f_{\max}$ of 370 GHz. For easier characterization and stabilization in a PLL the same static divide-by-4 chain is added to both VCO chips. The main purpose of this work is the integration of a VCO as a downconverter for a offset-PLL with good phase noise and low power consumption at the same time. At an offset of 1 MHz the Colpitts VCO achieves a phase noise of −108 dBc/Hz at 56 GHz and the cross-coupled VCO achieves a phase noise of −100 dBc/Hz at 68 GHz, respectively. Relative frequency tuning ranges (rFTR) of 26% for the Colpitts type and 43.7% for the cross-coupled VCO are reached.

This paper presents two D-band frequency quadruplers (FQs) employing different circuit techniques. First FQ is a 129–171-GHz stacked Gilbert-cell multiplier using a bootstrapping technique, which improves the bandwidth and the conversion gain with respect to the conventional topology. Stacked architecture enables current reuse for the second frequency doubler resulting in a compact and energy-efficient design. The circuit reaches 3-dB bandwidth of 42 GHz, which is the highest among similar reported quadruplers. It achieves 2.2-dBm saturated output power, 5-dB peak conversion gain, and 1.7% peak DC-to-RF efficiency. The stacked FQ occupies 0.08 mm2 and consumes 22.7 mA from 4.4-V supply. Second presented circuit is a transformer-based injection-locked FQ (T-ILFQ) employing an E-band push–push voltage-controlled oscillator (PP-VCO). The VCO is a self-buffered common-collector Colpitts oscillator with a transformer formed on emitter inductors. Proposed configuration does not reduce the tuning range of the VCO, thus providing wide locking range and high sensitivity with respect to the injected signal. The T-ILFQ achieves 21.1% locking range, which is the highest among other reported injection-locked frequency multipliers. The peak output power is −4 dBm and the input sensitivity reaches −22 dBm. The circuit occupies 0.09 mm2 and consumes 14.8 mA from 3.3-V supply.

In this work, a new differential topology of Colpitts VCO with an enhanced transconductance is presented. The proposed circuit is consisted of an NMOS and a PMOS differential Colpitts cores configured as complementary, and also an LC resonator. The VCO is designed to oscillate at 5 GHz which consumes 1.11 VA from 1.4 V supply voltage. In addition, a modified version of the proposed VCO is designed for lower power applications. This circuit employs new positive feedbacks to enhance the VCO’s transconductance and reduce the supply voltage. The modified VCO operates with 1.1 V power supply while dissipating 1 mW. To investigate the performance of the proposed circuits, the transconductance of them are theoretically analyzed. Also, two new quadrature VCOs (QVCOs) are presented which are realized by two identical latter proposed Colpitts VCOs. A linear analysis is presented to confirm that the first oscillator can generate outputs with 90° phase differences. The proposed circuits are designed in 0.18-μm RF-CMOS technology. Finally, prototype circuits of the proposed VCOs are fabricated to validate the theoretical results. The measurement results are summarized to demonstrate the main features of the proposed oscillators.

The implementation of wideband mm-wave radars for automotive applications necessitates wideband, fast, and precise linear frequency modulation generation. In this paper, we propose to use dual-loop phase-locked loop (PLL) architecture for this task. The frequency modulation dynamics are analyzed for this architecture. The results are employed to implement a SiGe BiCMOS fully integrated 75–83 GHz frequency-modulated continuous-wave synthesizer. Performance enhancements were achieved by utilizing the bulk-drain parasitic variable capacitance of P-channel transistors, embedded in a gm-boosted Colpitts VCO, for frequency control. This mechanism together with the dual-loop PLL architecture provides low loop bandwidth variation over the whole output frequency range, −97 dBc/Hz phase noise at 1-MHz offset, and maximal modulation rate of 100 GHz/ms.

This paper studies a new dual-band CMOS class-C voltage-controlled oscillator (VCO). The oscillator consists of a dual-resonance LC resonator in shunt with two pairs of capacitive cross-coupled nMOSFETs. The proposed oscillator has been implemented with the TSMC 0.18 μm CMOS technology, and it shows a frequency tuning range with two frequency bands and a small tuning hysteresis is measured. The oscillator can generate differential signals at 2.4 GHz and 6.9 GHz and it also can generate concurrent frequency oscillation while the circuit is biased around the bias with frequency tuning hysteresis. With the supply voltage of VDD = 1.1 V, the VCO-core current and power consumption of the oscillator are 2.90 mA and 3.19 mW, respectively. The die area of the class-C oscillator is 0.9 × 0.97 mm2. Overvoltage stress is applied to the oscillator, measurement indicates the concurrent oscillation is sensitive to overvoltage stress.

In this work, a new configuration of differential drain-to-source Colpitts LC voltage controlled oscillator (VCO) is proposed for low voltage applications. The circuit employs two capacitors in a cross-coupled positive feedback to separate the gate biasing of switching transistors from their drain dc voltages. This technique provides lower overdrive voltage for switching transistors which reduces the needing supply voltage. Besides, another positive feedback is imposed in this configuration which decreases the required transconductance for start-up oscillation. Also, a new quadrature VCO (QVCO) is presented by realizing two identical prior proposed Colpitts VCOs. The coupling technique used in the proposed QVCO improves the phase noise performance of the circuit. A linear analysis is presented to confirm that the oscillator can generate outputs with 90° phase difference. Additionally, the Monte Carlo (MC) simulation is performed to estimate the accuracy of the proposed circuit performance under various device mismatches.

This paper proposes a Class E/F $_3$ tuned power oscillator based on the Class E/F $_3$ amplifier. The oscillator has a feedback-loop circuit and starts the oscillation in automatic. In addition, the oscillator achieves zero-voltage switching and zero-voltage derivative switching; therefore, the switching losses are reduced under high oscillation frequency. Moreover, the third harmonic tuned by providing a third harmonic series resonant circuit reduces the switch voltage stress of the mosfet sufficiently. The oscillator was designed, built and tested using an IRFR120Z power mosfet . Under the condition of the input voltage 6.003 V, following results were shown: the measured oscillation frequency was 801.6 kHz, the output power was 0.9075 W, and the power conversion efficiency was 86.24%.

In this work, two new LC injection-locked frequency dividers (ILFDs) based on voltage-controlled oscillator are proposed. One of the proposed circuits is a divide-by-2 and the other is a divide-by-...

A 50 GHz cross-coupled differential-pair oscillator with a high-Q active inductor in the LC tank has been designed and fabricated in 65 nm bulk complementary metal-oxide semiconductor (CMOS) technology. The principle of operation is explained and a complete theoretical study is carried out. The analytical expressions for the open loop transfer function, oscillation frequency, start-up condition, tank impedance, and phase noise are derived. The results of the analytical study are compared with those obtained by SpectreRF simulations in the Cadence design environment. Measurement results of the stand-alone mm-wave active inductor show an equivalent inductance of 133 pH with a quality factor exceeding 400 at 50 GHz, demonstrating experimentally the implementation of high-Q active inductors operating at the millimeter waves in CMOS technology. The measurement results of the oscillator show a phase noise of −85 dBc/Hz at 1 MHz frequency offset from the carrier when the active inductor is switched off and −91 dBc/Hz when it is switched on, leading to a phased noise reduction of 6 dB.

In this paper, we propose a method to broaden a tuning range of a CMOS LC-tank oscillator without sacrificing its area. The extra tuning range is achieved by forcing a strongly coupled transformer-based tank into a common-mode resonance at a much higher frequency than in its main differential-mode oscillation. The oscillator employs separate active circuits to excite each mode but it shares the same tank, which largely dominates the core area but is on par with similar single-core designs. The tank is forced in common-mode oscillation by two injection locked Colpitts oscillators at the transformer's primary winding, while a two-port structure provides differential-mode oscillation. An analysis is also presented to compare the phase noise performance of the dual-core oscillator in common-mode and differential-mode excitations. A prototype implemented in digital 40-nm CMOS verifies the dual-mode oscillation and occupies only 0.12 mm2 and measures 56% tuning range.

In this brief, a cross-coupled oscillator is analyzed based on the two-port network theory and the $Y$ - parameter model for a transistor. Contrary to the previous works, the proposed analysis shows that LC cross-coupled oscillators have an additional and higher pure imaginary natural frequency at which the circuit cannot oscillate. The analysis investigates the sufficient condition at which the circuit is able to oscillate at this higher frequency. For the oscillation at the higher frequency mode, we propose adding an extra stage and making a three-stage ring oscillator. The equations obtained from this analysis indicate that the oscillation start-up condition depends on the oscillation frequency. Hence, increasing the speed of the oscillator does not satisfy the start-up condition of oscillators. Our analysis shows that the maximum frequency, in which the circuit stops oscillation in the ring oscillator, is higher than the cross-coupled oscillator and this maximum frequency is very close to the maximum frequency of the transistor.

This paper presents a low-power, highly-integrated D-Band transceiver chip realized in a 0.13 µm SiGe BiCMOS technology. The integration level includes three receiver (RX) channels, one transmitter (TX) channel, local oscillator (LO) signal generation and distribution network, frequency dividers and serial peripheral interface (SPI) for digital reconfigurability. The receiver achieves a peak gain of 14 dB at 118 GHz, while the transmitter achieves an output power of −6 dBm at 118 GHz. The VCO is realized in a push-push Colpitts topology. Additionally, its output is multiplied by two using a frequency doubler. Hence the transmitter output signal is continuously tunable in the frequency range 117 − 126 GHz, while achieving a measured phase noise of − 93.5 dBc /Hz at 1 MHz offset at 120 GHz. The entire transceiver draws 195 mA from a single 1.8 V supply. A single RX channel draws 19 mA, while a single TX consumes 25 mA. The circuit including pads occupies a chip area of only 3.5 mm × 2.75 mm, which is limited only by the separation necessary for isolation between the channels. The transceiver provides a competitive performance and is suitable for continuous-wave radar applications around 120 GHz.

This paper presents a comparative study between Hartley and Colpitts voltage controlled oscillator (VCO) in 5G mm-wave band. Both VCOs are designed using Monolithic Microwave Integrated Circuit (MMIC) technology using PH15 process from UMS foundry. Simulation results showed that Hartley VCO is less efficient than Colpitts VCO; it has a bandwidth of 1.85 GHz, a phase noise about -106.9 dBc/Hz at 1MHz frequency offset and a Figure of merit of -155.78 dBc/Hz, while the Colpitts VCO has a bandwidth of 2.25 GHz, a phase noise of -113.073 dBc/Hz at 1MHz frequency offset and a Figure of merit of -172.89 dBc/Hz.

This paper presents ultra-wideband fundamental VCOs in a automotive qualified production SiGe:C hetero bipolar technology with an f T of 240GHz and f max of 380GHz. The architecture of the VCOs is a fully differential topology based on a merge of the classic Colpitts- and Clapp-topologies. The VCOs are designed for a continuous tuning range to cover one full millimeter-waveguide band. The goal of this particular work is to encompass the full E- and W-Band, respectively. The fabricated chips also integrate the high-frequency part of a divide-by-8 prescaler for stabilization in a PLL also covering the whole W-Band with up to 110 GHz efficiently. Both VCOs facilitate a peak output power of 7dBm in their respective band at the differential output. The phase noise at 1MHz offset is -99dBc/Hz for the E-Band and -93dBc/Hz for the W-Band VCO at center frequency. The continuous tuning range is 31 GHz (40.1%) in the E-Band and 35.4 GHz (38.6%) in the W-Band. The characteristics are only slightly degrading even at 100° C. Only 215mW of power is consumed by the chips from a single 3.3V supply.

Pixels integrating a transmitter and a coherent receiver in an area of half-wavelength square are proposed for terahertz active imaging. 300- and 427-GHz transceiver pixels are demonstrated using a 65-nm CMOS process. The 300-GHz pixel employs a push-push stacked cross-coupled VCO, which doubles as a transmitter and an LO, and a pair of diode-connected NMOS transistors for mixing. The pixel occupies an area of 450×580µm2, and provides −21.3-dBm total radiated power and −79.5-dBm sensitivity for a 1-kHz noise bandwidth at 260GHz. The 426-GHz pixel using a star-type triple-push Colpitts oscillator works as a transmitter and a self-oscillating mixer. The pixel occupies an area of 380×470µm2. The radiated power is −17.9 dBm and the sensitivity is −89.6 dBm for a 1-kHz noise bandwidth. Link-budget analyses suggest that camera-like reflection-mode imaging of targets 5m away should be possible using the pixel and a 4.6cm×4.6cm reflector.

Two wide tuning signal sources operating around 300 GHz, with and without a buffer, have been developed in this work based on a 130-nm silicon-germanium (SiGe) heterojunction bipolar transistor (HBT) technology. The 300-GHz signal source, consisting of a Colpitts voltage-controlled oscillator (VCO) followed by a doubler, shows −2.89 dBm output power around 302 GHz, −81.5 dBc/Hz phase noise at 1-MHz offset, 7.98% tuning range, and 0.96% DC-to-RF efficiency. After placing a differential common-emitter amplifer between the VCO and doubler, it exhibits a little higher operating frequency, from 290.8 to 316.6 GHz, and a better −85.1 dBc/Hz phase noise at 1-MHz offset, but with reduced output power of −5.2 dBm and efficiency of 0.33%. The layout size for each oscillator is $524\times 495\ \mu \mathrm{m}^{2}$ and $524\times 540 \ \mu \mathrm{m}^{2}$ , including DC and RF pads.

This paper describes a bank of four SiGe BiCMOS oscillators tailored to cover the 18.2-29.3 GHz frequency range, needed to tackle the needs of 5G communications. The Colpitts oscillator topology is leveraged to achieve a lower absolute phase noise compared to Class-C oscillators, at the expense of deteriorated figure of merit. Benefiting from the proper technology choice, a careful tank design was carried out to maximize Q, minimize K VCO and phase noise variations. The four oscillators feature state-of-the-art phase noise, ranging from -119.5 dBc/Hz to -116.5 dBc/Hz at 1MHz offset for 18.2 GHz and 29.3 GHz carrier frequency, respectively. For each oscillator the phase noise variation is only

A highly linear and fully-integrated frequency-modulated continuous-wave (FMCW) generator based on a fractional-N phase-locked loop (PLL) that is able to synthesize modulation schemes in 57---64 GHz range is proposed in this paper. The fractional-N PLL employs Colpitts voltage-controlled oscillator (VCO) at 60 GHz with 13.5% tuning range. Automatic amplitude and frequency calibrations are implemented to avoid drifts due to process, voltage and temperature variations and to set the center frequency of the VCO. Five-stage multi-modulus divider is used for division ratio switching, controlled by the sigma-delta ($$\Sigma \Delta$$ΣΔ) modulator MASH 1-1-1. The frequency sweep (chirp) bandwidth and duration are fully programmable via serial peripheral interface allowing up to 16 different chirps in complex modulation scheme. The PLL reference signal is 250 MHz provided by external low-noise signal generator which is also used for digital modules clock. The overall PLL phase noise is lower than ?80 dBc/Hz at 10 kHz offset and the chirp linearity is better than 0.01%. The complete FMCW synthesizer is implemented and verified as a stand-alone chip in a commercially available SiGe HBT 130 nm BiCMOS technology. The total chip area is $$2.04\,\text {mm}^2$$2.04mm2, and the total power consumption is 280 mW.

In this paper a new LC oscillator without tail current source with an impedance transformation block (ITB) has been presented. Using this ITB, the noise generation from active devices is reduced. The cross-coupled transistors remain mostly in the saturation region and prevent decreasing of LC-tank quality factor. Moreover this structure benefits from more relaxed start-up condition as compared to the conventional LC oscillators and preserves its low phase-noise performance even in low voltage operation. This oscillator is designed and simulated in 0.18 µm CMOS process. The simulation results show that the proposed oscillator achieved a phase noise between ź138.5 and ź141.2 dBc/Hz at 3 MHz frequency offset with 23 % tuning range between 4.61 and 5.79 GHz. The corresponding Figure-of-merit in this tuning range is between ź189.1 and ź192.1 dBc/Hz which is among the best reported performance in comparison to the other state of the arts designs.

In this paper, a 7/24-GHz dual-band voltage-controlled oscillator (DVCO) using a current-source switching topology is designed, implemented, and verified in a $0.18\hbox{-}\mu{\text{m}}$ CMOS technology for C -band and K -band radar applications. The low- and high-frequency bands are obtained by the Colpitts mode oscillation and the cross-coupled pairs (CCPs) mode oscillation, respectively. Unlike conventional dual-band VCOs realized by resonator-switching topologies, the proposed VCO is based on the composite Colpitts and CCP architecture to avoid additional losses in the resonator, or lower its power consumption. The fabricated VCO occupies a chip area of $0.95\times0.71\;{\text{mm}}^{2}$ including all testing pads. Measurements show that the VCO operating in the Colpitts mode provides a phase noise of $-112.5{\text{ dBc/Hz}}$ at 1 MHz offset from the 7.4-GHz oscillation frequency under 7.5-mW power consumption. When the VCO is operating in the CCP mode, it provides a phase noise of $-99.9{\text{ dBc/Hz}}$ at 1 MHz offset from the 24-GHz oscillation frequency with 9.7-mW power dissipation. Moreover, the DVCO achieves a high band ratio $(f_{H}/f_{L}=24/7)$ of 3.43. To the authors’ best knowledge, the design features the highest band ratio, low power dissipation, and comparable electrical performances among previously reported DVCOs.

This letter presents a triple-band (TB) oscillator using two 4th order LC resonator to form a 6th order resonator. The TB cross-coupled oscillator two pairs of back-to-back varactors for band switching and it has been implemented with CMOS devices in the TSMC 0.18μm SiGe 3P6M BiCMOS technology. The core power consumption of the high (middle, low)-band core oscillator are 2.25(2.33, 2.58) mA and 1.8(1.86, 2.06) mW, respectively at the dc drain-source bias of 0.8V. The oscillator can generate differential signals in the frequency range of 8.44–8.71GHz, 6.74–6.86GHz, and 4.22–4.47 GHz. © 2015 Wiley Periodicals, Inc. Microwave Opt Technol Lett 58:580–583, 2016