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In this chapter I discuss the value of video and digital microscopy, how an optical signal is converted to an electrical signal using video and digital cameras, and how the signal can be viewed on an analog or digital monitor. I discuss the characteristics of digital CMOS and CCD sensors as well as video tubes in terms of resolution and dynamic range (contrast). This information lets us know how a point in the specimen is converted to a point (pixel) in a video or digital image.

Publisher Summary The main feature of any video device is the screen. The first video or TV screens were cathode ray tubes (CRT) and those are still used in older TV sets and computer monitors. The most commonly used TV and video screen today is the LCD. LCD screens are used in the newer TV sets and in most personal computers. Nothing in electronics has affected us more than the development of television. TV came first and has been working its magic on us for far longer. The impact of television or video on our lives is significant in that one spends more than half our waking hours in front of a TV screen, either watching TV or working with a video monitor on a computer. The social and political impact has been enormous. And, of course, people also interact with the liquid crystal display (LCD) screens on cell phones, laptops, and personal navigation devices. For this reason it helps to understand a little bit about how video works. Video is perhaps one of the most complex segments of electronics, but this chapter makes those fundamentals easy to understand.

Watching video is the most popular way for people to enjoy multimedia contents. However, videos are required to be displayed at different rate because there are many different display devices nowadays. In this chapter, we introduce the background knowledge, applications, and technical details of current multirate video systems. First, we introduce the basic concept and knowledge of the video system. In addition, several examples of multirate video applications are shown. Afterward, we explain the key techniques to achieve these applications from the fundamental frame rate conversion (FRC) and the advanced frame rate up-conversion (FRUC). We also state the motivation of higher frame rate before the FRUC techniques are presented. The general flow diagram of the FRUC techniques is given, and the technical details are then discussed and stated. Moreover, several evaluation methods are explained, and the popular video datasets are shown. In addition to different algorithms, we discuss the requirement and recent researches of hardware implementation for FRUC techniques. Finally, a conclusion and discussion are given.

The wireless video monitoring system contains the video acquisition device,video transmission device,video storage device and VGA display device.In this paper,we use video acquisition device to collect video siganals in real-time.The analog video signal is transmitted by using wireless technology.The video signal is converted to a digital signal by using the dedicated A/D chip. At the same time ,the YCrCb signals will be converted into RGB signals by the format converting module.Then,the digital RGB signals are converted to analog RGB signals through the D/A,and they are finally displayed on the VGA monitor in real-time.The design mainly uses the wireless transmission technology to transmit analog video signals and uses ADV7181 to decode.The controlling system of FPGA deals with the decoded digital signals which will be transmitted to the D/A and the data finally will display in real time.

This paper describes a video signal processing system, based on the research of DirectShow streaming media processing platform, H.264/AVC video coding technology and multi-channel video encoding chip SC8919 which includes H.264 hardware video encoder. This system can compress four channel D1(720*576) size of the image data collected by camera at the rate of 30fps into standard H.264 stream, and upload it to the control room to store and decode broadcast through existed campus Ethernet without additional laying line.

A video display system is designed and implemented based on FPGA.The architecture is composed of three subsystem,which are video capture,video processing and video display subsystem.The video capture subsystem can process YCrCb 4∶2∶2 video data stream which is compatible with the ITU-R BT.656 PAL standard,while the video processing subsystem video image data is stored highly with ping-pong cache technology,and the video image display subsystem can display the image in standard VGA format.The main processing chip of the system is Cyclone Ⅱ family of EP2C70 of Altera,and each functional module are achieved by Verilog HDL.The whole system has achieved good video capture and good display result.

The recent trend of digital convergence requires processing the conventional analog TV decoding digitally. In this paper we propose an implementation of video decoder for fixed rate sampled SECAM video signals. The implementation includes a frequency demodulation method to recover luminance and chrominance signals from the composite signal. The corresponding VLSI chip is fabricated with 0.18 mum technology in order to verify the performance and physical characteristics of the implementation.

Considered Class B digital video channel is a kind of channel with gamut conversion, compression codec and other procedures, the conventional component video test signals are "illegal" and "invalid" when going through the Class B channel. In order to solve this problem, this paper studied the design principles applied to the component video test signals used for Class B digital video channels, and three kinds of standard definition test signals and one kind of high definition test signal used for the Class B digital video channel are designed with the parameters of the GY/T 243-2010 "Standard-definition digital video TV channel technical requirements and methods of measurement", and these signals are implemented based on the Tektronix TG8000 multiformat test signal generator with XML language. Finally, a set of measurement experiments are performed with the test signals implemented in this paper.

This paper presents a comparison of YUV color video formats using the H.264 video compression standard. The goal of this paper is to determine the best color video format for rate-distortion quality. This is a point of interest due to wireless video transmission quality and bandwidth limitations. The results show that for 1080p video, the YUV 4:2:0 video with a chrominance quantization parameter offset of zero is among the best performing color video format in terms of rate-distortion quality for three different levels of compression and two different entropy encodings.

In this paper, we have proposed a security camera system that displays high-definition images by using a sharply outlined display algorithm (SODA), which generates less hardware complexity because of a modified video encoder. While the proposed system uses a charge coupled device (CCD) with a complementary filter that may cause some problems in representing vivid color, we have been able to resolve the problem by mixing two signals, such as those generated by chrominance and luminance processes. In doing so, the system requires the use of a video encoder that converts the CCD's output signals into a composite video baseband signal (CVBS). Moreover, although a video encoder generally operates at 27 MHz the CCD module used in the security camera requires a particular clock frequency. Here, we have proposed that the new video encoder uses a clock to equal the CCD module at a given frequency. In doing so, the system using the encoder reduces hardware complexity and noise. The proposed system is fabricated with a test camera chip that has been manufactured by the MagnaChip 0.25 /spl mu/m CMOS process.

Flicker is one of the artificial distortions of MPEG-2 coded video caused by the display's gamma characteristics and depends on the picture texture. In order to improve the picture quality, we have developed a technique of reducing the flicker by display gamma simulations in the decoded pictures. The effectiveness was confirmed by experiments. The process is less complex, and the implementation of this technique in digital TV receivers is expected to improve the coded picture quality.

Optimally interfacing video switches within consumer video designs is increasingly a challenge. This article looks at two design cases for DVD R/W and LCD TV applications in order to fully understand how to optimise the signal data path to optimise video switch performance.

This paper presents the design of a multi-standard NTSC/PAL video encoder. The encoder converts International Telecommunication Union-Recommendation (ITU-R) BT.601 4:2:2, ITU-R BT.656 or RGB inputs from various video sources into National Television Standards Committee (NTSC) or phase-alternate line (PAL) TV signals in both S-video and composite video baseband signals (CVBS). The encoder adopts multiplier-free structures to reduce hardware complexity. The hardware bit width of programmable digital filters for luminance and chrominance signals, along with other operating blocks, are carefully determined to produce high-quality digital video signals of 1 least significant bit (LSB) error or less. The proposed encoder is experimentally demonstrated by using the Altera APEX20K600EBC652-3 device.

We present the 3D Video Recorder, a system capable of recording, processing, and playing three-dimensional video from multiple points of view. We first record 2D video streams from several synchronized digital video cameras and store pre-processed images to disk. An off-line processing stage converts these images into a time-varying 3D hierarchical point-based data structure and stores this 3D video to disk. We show how we can trade-off 3D video quality with processing performance and devise efficient compression and coding schemes for our novel 3D video representation. A typical sequence is encoded at less than 7 Mbps at a frame rate of 8.5 frames per second. The 3D video player decodes and renders 3D videos from hard-disk in real-time, providing interaction features known from common video cassette recorders, like variable-speed forward and reverse, and slow motion. 3D video playback can be enhanced with novel 3D video effects such as freeze-and-rotate and arbitrary scaling. The player builds upon point-based rendering techniques and is thus capable of rendering high-quality images in real-time. Finally, we demonstrate the 3D Video Recorder on multiple real-life video sequences.

A bidirectional video bus consisting of the low cost LT1190 op amp and the LT1193 video difference amplifier is described.

Several different video circuits that work with composite, RGB and monochrome video are described.

This paper presents a new method for the implementation of an NTSC digital video decoder. This new fully digital architecture uses a phase-locked loop to compensate the unstable video source and an adaptive comb filter to improve the quality of Y/C separation. Simulation results show that it can successfully combat a sinusoidal timing variation of /spl plusmn/2 /spl mu/s for horizontal line lengths within one frame. It can also lock to a 3.58 MHz color subcarrier with frequency variation up to /spl plusmn/500 Hz.

This paper presents a FPGA based video interface conversion system that enables the inter-conversion between digital and analog video. Cyclone IV series EP4CE22F17C chip from Altera Corporation is used as the main video processing chip, and single-chip is used as the information interaction control unit between FPGA and PC. The system is able to encode/decode messages from the PC. Technologies including video decoding/encoding circuits, bus communication protocol, data stream de-interleaving and de-interlacing, color space conversion and the Camera Link timing generator module of FPGA are introduced. The system converts Composite Video Broadcast Signal (CVBS) from the CCD camera into Low Voltage Differential Signaling (LVDS), which will be collected by the video processing unit with Camera Link interface. The processed video signals will then be inputted to system output board and displayed on the monitor.The current experiment shows that it can achieve high-quality video conversion with minimum board size.

This paper presents a high‐definition video display solution based on the FPGA and THS8200. THS8200 is a video decoder chip launched by TI company, this chip has three 10-bit DAC channels which can capture video data in both 4:2:2 and 4:4:4 formats, and its data synchronization can be either through the dedicated synchronization signals HSYNC and VSYNC, or extracted from the embedded video stream synchronization information SAV / EAV code. In this paper, we will utilize the address and control signals generated by FPGA to access to the data‐storage array, and then the FPGA generates the corresponding digital video signals YCbCr. These signals combined with the synchronization signals HSYNC and VSYNC that are also generated by the FPGA act as the input signals of THS8200. In order to meet the bandwidth requirements of the high‐definition TV, we adopt video input in the 4:2:2 format over 2×10-bit interface. THS8200 is needed to be controlled by FPGA with I 2 C bus to set the internal registers, and as a result, it can generate the synchronous signal that is satisfied with the standard SMPTE and transfer the digital video signals YCbCr into analog video signals YPbPr. Hence, the composite analog output signals YPbPr are consist of image data signal and synchronous signal which are superimposed together inside the chip THS8200. The experimental research indicates that the method presented in this paper is a viable solution for high‐definition video display, which conforms to the input requirements of the new high‐definition display devices.

AVS2 is an ongoing standardization effort by Audio Video coding Standard Workgroup of China toward high efficiency coding of multimedia compared to the previous standard (AVS1). AVS2-P2 is the video part for high-definition, ultra-high-definition and three dimensional video contents. Raw video content of 10-bit bit depth has superior visual quality compared to traditional 8-bit counterpart. Thanks to the advance of computing power of hardware, support for video content of 10-bit bit depth is becoming very important in current high resolution video processing applications. We present here a new 10-bit design to AVS2-P2 standard based on our 10-bit encoding proposal [1] on the 48 th AVS2 working group meeting.

Analog video is on the way out, so why study it at all ? Many digital television standards evolved from analog video standards. To have a complete understanding of standards, it is necessary to understand why the choices were made to create standards for today's digital video. Why do we have interlace in the first place and why should it be considered in digital video; what problem did the color difference signal (R-Y and B-Y) solve, and why was it chosen for today's digital system? These and other concepts are briefly discussed in this paper.

We have developed a PVR (personal video recorder) that is capable of simultaneous playback and recording of HD quality MPEG-2 streams for digital TV. It provides viewers with a few enhanced features as well as basic features such as pause, instant replay, skip forward and fast forward/rewind in conventional PVRs for analog TV. This paper describes enhanced and new features that are implemented on our PVR.

Converting the digital video (DV) format for digital video cassette recorders into the MPEG-2 intra coding is performed in the DCT domain to reduce conversion steps. To convert the 4:1:1 to the 4:2:2 chroma. formats and the 2-4-8 DCT mode to the 8-8 DCT mode, a matrix is multiplied by transformed data. Such multiplication enables parallel processing, and the m_quant of the MPEG-2 TM5 rate control is computed in the DCT domain.

A wide variety of video services can benefit from application of a video pixel multiplier (VPM) that locally adds extra pixels for a higher resolution display. These services include standard definition television (SDTV) displayed on a high definition television (HDTV) display, and third generation (3G) wireless mobile video transmission displayed on a higher-resolution display that could be used for fixed and mobile wireless.

Thanks to increased market acceptance of applications such as digital versatile disks (DVDs), HDTV, and digital satellite broadcasting, the MPEG-2 (Moving Picture Experts Group-2) standard is becoming widely used. The MPEG-2 video standard, established in 1934, provides for a high-quality video compression format that, through high bit rates and frame rates, yields high-resolution video images. Emerging multimedia applications, such as digital versatile disk and high-definition television, demand higher quality video than ever before. In response, our MPEG-2 video encoder chip supports multiple profiles and levels.

This paper discusses methods for bit-rate transformation of previously encoded compressed video bitstreams. The proposed high-quality, low complexity bit-rate transformation algorithms are especially suitable for consumer devices such as the Home Media Station-a sophisticated multimedia receiver/decoder/recorder for consumer use.

This paper describes the implementation of a multi-standard video data slicer. It was designed to process data of a variety of services like teletext, closed-caption etc. in multiple video norms like PAL and NTSC. For achieving high performance, the concept is completely digital and contains a self-adjusting equalizer.

Digital video follows the laws of all digital technology; breaking down video imagery into a binary data stream composed of ones and zeros delivered as low-voltage electronic pulses over copper wire or light pulses over fiber optics. Anything that requires digital churning of bits (binary digits) uses microprocessor and stores information in binary “on” and “off” (ones and zeroes). Digital video is a mathematical absolute, using more effective compression techniques to deliver more data, including parameters for redundancy, retries, and quality. Digital video is also somewhat universal because of the proliferation of the Internet. There is a brief discussion on analog versus digital, the image on any monitor or screen, whether the traditional analog cathode-ray tubes (CRT) television or computer monitor, is the accumulation of rectangular dots called pixels (an abbreviated version of picture element). All images, video or static, are measured in pixels. In the analog world, each of these pixels is composed of three-color dots of red, green, and blue. There are three major worldwide analog television standards: the American NTSC color television system, the European PAL, and the French-Former Soviet Union Sequential Couleur avec Memoire (SECAM).

Only very small CCTV systems use the simple camera-monitor concept. Most of the bigger ones, in one way or another, use video switching or processing equipment before the signal is displayed on a monitor. With the introduction of digital video, all switching and processing, even of the analog video signals (certainly after they are digitized), are done over network and network switchers. This chapter may well be outdated within the next couple of years, but there are still existing analog CCTV systems out there, and therefore there was a need to still cover this topic.

In recent years, digital high-definition television is widely used due to the start of digital terrestrial television broadcasting. In addition to such situation, ultra high definition television format such as 4K and 8K has been standardized. On the other hand, high-speed wireless transmission systems using MIMO-OFDM including IEEE 802.11n and 802.11ac wireless LAN standards have become popular. Using such high-speed transmission systems, it is expected that high-definition video sequences can be transmitted without any degradation of quality. Therefore, we are trying to develop such high-quality video transmission systems over a wireless environment by combining lossless video compression algorithms and MIMO-OFDM wireless transmission technology considering both hardware implementation and wireless transmission conditions. In this paper, we evaluate a configuration of lossless video transmission systems. Experimental result shows that video sequences can be transmitted over 22db carrier to noise ratio (CNR) wireless channels with 99.99% pixel restoration rate.

Our two-chip, real time, MPEG-2, simple-profile-at-main-level encoder supports NTSC 4:2:0 video signals with only three external memories. We have developed a compact encoder chip set. The key features of this chip set are a low encoding delay based on a simple profile at main level; wide-range motion estimation, which it performs using a hierarchical search; a flexible, macroblock level pipeline architecture based on RISC CPUs; and three small peripherals with no glue logic: a VRAM, synchronous DRAM, and FIFO DRAM.

A video processing LSI which converts video signals to digital YUV signals in various image formats was successfully developed for a video capture system. This LSI is suitable for PC cameras, camera/recorders and PC video capture boards.

The paper describes the hardware implementation of the video scan converter for the Grand Alliance high definition television (GA-HDTV) system. GA-HDTV supports two basic video formats. One of the two formats is a progressive video and the other is interlaced video. The scan converter system converts between the two GA-HDTV video formats with seamless switching of input video. The paper also describes the treatment of interlaced video that originates from a film sequence (either 24 Hz or 30 Hz) for progressive scan conversion.

In recent years, liquid crystal displays (LCD) have almost completely replaced older technologies such as cathode ray tube (CRT) displays in many industrial, commercial, aerospace, and military applications due to their increased efficiency, decreased weight, and smaller size. Likewise, the technology used to transmit video signals to LCD displays has evolved from analog standards such as the National Television Standards Council's (NTSC) RS-170 standard and the Phase Alternating Line (PAL) standard to higher speed digital standards such as the Digital Visual Interface (DVI) standard, High-Definition Multimedia Interface (HDMI) standard, and low-voltage differential signaling (LVDS) standard. This evolution of video standards has created a need for the test environments and test generation devices used to test video displays to mature as well.

The system is based on TMS320DM642, which is a digital processor chip of TI, as the core and combined with SAA7113 and SAA7121 Chip as the video decoder/encode. The TMS320DM642 chip can solve the problems of large video data transmission and achieve high reliable video monitor systems. In the paper, it represents the structure of DM642 and DSP/BIOS system. It details the design of software module. In the last place, the paper gives the solution for the problems in the design and realizes the design.

3D video technologies such as 3D cameras, displays, and video-processing have become more important for achieving high quality and immersive video services. We propose an H.264 MVC encoder architecture for real-time 3D video distribution and transmission. We also present the first-ever successful development of a full-HDTV real-time MVC encoder.

One of the unresolved problems in providing viable stereoscopic 3D visual services based on terrestrial DTV is to carry additional video while maintaining existing 2D video quality within limited bandwidth. Mitigating this problem, our proposed 3D service incorporates ATSC Non-Real-Time (NRT) transmission scheme in which the additional video stream delivered in advance of use and stored for later consumption. At later time when transmitting an air AV program associating the additional video previously sent, a receiving device is able to play stereoscopic 3D video by combining real time video and the stored additional video synchronously. In this paper, we propose backward compatible system for the 3D NRT service and show that our implementation successfully presents the new stereoscopic 3D visual services based on Terrestrial DTV.

We developed a low-cost system for simultaneous collection and storage of physiological and video signals. The system samples and multiplexes up to 240 low-bandwidth analog channels with a camera video signal, and outputs a standard composite video signal containing analog and video data. The combined signals can be stored on video tape or can be digitized by an inexpensive framegrabber. The circuitry separates horizontal synchronizing pulses from a camera output; the pulses increment a counter that sequentially selects each electrophysiological channel on a sample-and-hold multiplexer. The intensity of each horizontal scan line from the multiplexer output represents the amplitude of one sample of each physiological channel. This signal is then multiplexed with the video signal, such that a portion of each video horizontal line represents the physiological data. The combined output is stored together, providing a means for synchronizing the two signals during analysis. The design allows easy coordination of electrophysiological events with video images from a standard video camera, avoiding the necessity for separate analog to digital circuitry for physiological and video signal storage on computer media, as well as the need for complex synchronization of the data from different media.

For real-time transmission of broadcast-quality video on ATM-based B-ISDN, the intraframe to interframe ratio and the quantizer scale are two key parameters that can be used to control a video source in a network environment. Their impact on the traffic characteristics of the coder provides insights into the cell arrival process for an MPEG source. The authors obtain video source models for coders that utilize a standard algorithm that can be applied to a multitude of video services. The output stream of a video coder, which complies with the Motion Pictures Expert Group (MPEG) coding standard, is studied with an National Television Systems Committee (NTSC) quality video sequence as the input. Because the MPEG video coding algorithm has been proposed for a variety of applications, they also investigate the effect of changing the coding parameters on the statistics of interest. >

The development of a personal computer (PC)-controlled multiple window display card for television is described. A digital encoder card for converting the red, green and blue (RGB) signals from the PC to a composite video signal (CVBS) is designed and developed. This digital encoder card accepts the RGB analog signals from the computer VGA display adaptor card and converts them into a PAL or NTSC format composite video signal. A chroma keying circuitry, to enable an additional video signal to be displayed with the encoded CVBS signal on a television screen in a picture-in-picture format is also included. >

A simultaneous transmission system for dual video signals is developed, which can transmit two video signals through a single analog channel.The system uses an analog bandwidth compression technique and the encoded signal is in the NTSC form. This system divides the two-dimensional division multiplex form.This paper discusses problems of developing and evaluating this equipment for practical use.

In the radio channel, compression is used for transmission of real-time analog video signal and compressed bits can usually be transmitted at a non-constant rate. But standard video can be displayed on TV at a constant rate. It is difficult to decode the intermittent compressed data for real-time video display. In order to solve the problem which rate of video decoding and compressed bits in the radio channel does not match, a method is brought forward. By controlling the data which transmit to the decoder, the real-time sequential video can be displayed. And the method has been used to the system of video transmission. Its reliability and validity can be proved.

This paper presents the design of a high-performance processor used for head-mounted display (HMD) applications targeting stereo video processing. The proposed hardware architecture of the video processor consists of three major parts: an adaptive 3-dimensional (3D) video decoder to accurately decoding the stereo composite video base band signal (CVBS) source, a video source separation module to generate the 3D display effects while maintaining the original field frequencies on both output channels, and a image post-processing module to enhance the display quality. Furthermore, the paper discusses the key design issue on compact hardware structure for SDRAM access, which is ultimately achieved in a single general SDRAM by data clustering and integration. Both FPGA and ASIC implementations are carried out and the results carefully compared showing that the designed video processor for 3D display could produce well immersing feeling with limited costs in effective decreasing the noise, flicker and crosstalk.

In the stereoscopic frame-compatible format, the separate high-definition left and high-definition right views are reduced in resolution and packed to fit within the same video frame as a conventional two-dimensional high-definition signal. This format has been suggested for 3DTV since it does not require additional transmission bandwidth and entails only small changes to the existing broadcasting infrastructure. In some instances, the frame-compatible format might be used to deliver both 2D and 3D services, e.g., for over-the-air television services. In those cases, the video quality of the 2D service is bound to decrease since the 2D signal will have to be generated by up-converting one of the two views. In this study, we investigated such loss by measuring the perceptual image quality of 1080i and 720p up-converted video as compared to that of full resolution original 2D video. The video was encoded with either a MPEG-2 or a H.264/AVC codec at different bit rates and presented for viewing with either no polarized glasses (2D viewing mode) or with polarized glasses (3D viewing mode). The results confirmed a loss of video quality of the 2D video up-converted material. The loss due to the sampling processes inherent to the frame-compatible format was rather small for both 1080i and 720p video formats; the loss became more substantial with encoding, particularly for MPEG-2 encoding. The 3D viewing mode provided higher quality ratings, possibly because the visibility of the degradations was reduced.

In this work, a novel method for color video compression using key-frame based color transfer has been proposed. In this scheme, compression is achieved by discarding the color information of all but few selected frames. These selected frames are either the key frames (frame selected by a key frame selection algorithm) or the Intra coded (I) frames. The partially colored video is compressed using a standard encoder thereby achieving higher compression. In the proposed decoder, a standard decoder first generates the partially colored video sequence from the compressed input. A color transfer algorithm is then used for generating the fully colored video sequence. The complexity of the proposed decoder is close to a standard decoder, allowing its use in wide variety of applications like video broadcasting, video streaming, hand-held devices etc.

We developed a chip set consisting of two analog ICs and two digital LSIs for serial transmission of digital video signals. It includes analog FIR filters as a part of an automatic cable equalizer that allows digital video signals to be transmitted through a coaxial cable. This chip set can transmit and receive composite NTSC/PAL, component 525/625, and wide component 525/625 digital video signals. It also includes multiplexing/demultiplexing functions for 24-bit audio and Error Detection and Handling (EDH) packets. With this chip set total digital broadcasting systems can easily be constructed.

Two channels video signal of the same scenery can be obtained by two CCD synchronous video cameras whose integration times are different: one is longer than another. The CCD video camera with short integration time is used for obtaining bright image information while the one with long integration time is used for obtaining gray image information. The image processing method is to adopt DSP combining the subsection linear weight. Then all the processed image information will be input into a video encoder and come to one channel video image with wild dynamic range. The effect of this way is equate to the dynamic range of CCD image sensor was expanded from 80dB to 106dB and finally come to the purpose of video antiblooming.