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Using full-scale 3-D simulations of 100 000s of devices, enabled by “push-button” cluster technology, we study in detail statistical threshold voltage variability in a state-of-the-art n-channel MOSFET introduced by the combined effect of random discrete dopants (RDDs) and line edge roughness (LER) and demonstrate that the resulting distribution is non-normal. Based on careful statistical analysis of the results, we show how the resulting distribution of VT can be constructed from the distributions arising from the individual simulation of RDD and LER variability. In accomplishing this task, we have deployed computationally efficient statistical enhancement techniques that drastically reduce the computational effort needed to accurately characterize threshold voltage variability under the combined influence of RDD and LER. [ABSTRACT FROM PUBLISHER]

In this paper, we report a 3-D Monte Carlo (MC) simulation methodology that includes complex quantum confinement effects captured through the introduction of robust and efficient density gradient (DG) quantum corrections (QCs), which has been used to introduce “ab initio ” scattering from quantum confinement fluctuations in ultrathin body silicon-on-insulator metal–oxide–semiconductor field-effect transistors (MOSFETs) through the real space trajectories of the particles driven by the DG effective quantum potential and to study the enhanced current variability due to the corresponding transport variations. A “frozen field” approximation, where neither the field nor the QCs are updated, has been used to examine the dependence of mobility on silicon thickness in large self-averaging devices. This approximation, along with the MC simulations that are self-consistent with Poisson's equation, is applied to study the variability of on-current due to random body thickness fluctuations in thin-body MOSFETs at low and high drain biases. [ABSTRACT FROM PUBLISHER]

In this paper, using computationally intensive 3-D simulations in a grid computing environment, we perform a detailed study of line-edge-roughness (LER)-induced threshold voltage variability in contemporary MOSFETs. Statistical ensembles of tens of thousands transistors have been simulated. Our analysis has been predominantly performed on a 35-nm channel-length bulk MOSFET test bed, widely used in previous studies to investigate the impact of different statistical variability sources. Comprehensive data mining and statistical analysis provide information about the shape of the distribution of the device threshold voltage, which is significantly non-Gaussian. Strong nonlinear correlation has been observed between the threshold voltage and the average channel length of the simulated devices. The width dependence of LER-induced threshold voltage variability has also been simulated and analyzed. Additional confirmation of the basic conclusions from the simulation and statistical analysis of the 35-nm test bed transistor is provided by the simulation of a 42-nm physical channel-length bulk LP MOSFET, a 32-nm channel-length thin-body silicon-on-insulator (SOI) MOSFET, and a 22-nm channel-length double-gate (DG) MOSFET. [ABSTRACT FROM PUBLISHER]

In this paper, we examine, in more detail, the strong correlation between the distribution of threshold voltage (VT) and the average channel length (\overlineLC) discovered in Part I of this paper. Based on the results of statistical analysis, we investigate an approach whereby the line-edge-roughness (LER)-induced distribution of VT can be reconstructed based on the convolution of the distribution of \overlineLC and the subdistributions of VT at particular values of \overlineLC. Further analysis demonstrates that the actual shape of the subdistributions has little impact on the accuracy of the reconstruction. This result allows a fast and economical semianalytical approach for the simulation of LER-induced VT variability, based on the nonlinear transformation of the distribution of \overlineLC into the distribution of VT using the channel length dependence of the threshold voltage as a mapping function. The accuracy of the semianalytical approach has been confirmed by comparison with the distributions of VT obtained for a broad range of conventional and novel MOSFETs using comprehensive 3-D simulations. [ABSTRACT FROM PUBLISHER]

The distribution of fractional current change and threshold voltage shift in an ensemble of realistic 35 nm bulk negative-channel metal-oxide-semiconductor field-effect transistors caused by charge trapping on stress-generated defect states at the Si/SiO2 interface is studied using 3-D statistical "atomistic" simulations. The simulations take into account the underlying random discrete dopant distribution in the transistors, which in conjunction with strategically positioned traps could result in rare but dramatic changes in the transistor characteristics. The evolution of threshold voltage distribution as a result of accumulation of trapped charges in the devices due to progressive negative bias temperature instability, positive bias temperature instability, or hot electron degradation is simulated and compared with simple analytical model predictions and recently published experimental measurements to demonstrate the necessity to consider statistical variability in realistic reliability simulations. The magnitude of the degradation in devices of different geometries is also investigated where minimal correlation is found. [ABSTRACT FROM AUTHOR]

Using the Glasgow "atomistic" simulator, we have performed 3-D statistical simulations of random-dopant-induced threshold voltage variation in state-of-the-art 35- and 13-nm bulk MOSFETs consisting of statistical samples of 105 or more microscopically different transistors. Simulation on such an unprecedented scale has been enabled by grid technology, which allows the distribution and the monitoring of very large ensembles on heterogeneous computational grids, as well as the automated handling of large amounts of output data. The results of these simulations show a pronounced asymmetry in the distribution of the MOSFET threshold voltages, which increases with transistor scaling. A comprehensive statistical analysis enabled by the large sample size reveals the origin of this observed asymmetry, provides a detailed insight into the underlying physical processes, and enables the statistical enhancement of simulations of random-dopant-induced threshold voltage variation. [ABSTRACT FROM AUTHOR]

Abstract: Statistical variability and reliability due to random discrete dopants (RDD), gate line edge roughness (LER), metal gate granularity and N/PBIT associated random charge trapping has limited the progressive scaling of bulk planar MOSFETs beyond the 20-nm technology node. In this paper, their impacts on device figures of merit are studied through comprehensive 3-D simulation. It is found that raised drain-bias can exacerbate threshold-voltage fluctuations, mainly due to LER and RDD. Subthreshold slope (SS) variations resulting from each variation source is studied: RDD and LER generate most of the SS variation and are primarily responsible for its skew. Drain induced barrier lowering (DIBL) is examined against each intrinsic variation source, and RDD and LER are found to cause most of the DIBL variability. The correlation of DIBL with threshold-voltage is fully analysed with respect to each source of statistical variability and reliability. Except for LER, all major sources of variability exhibit de-correlation of DIBL against threshold-voltage. [Copyright &y& Elsevier]