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In this work, the time-dependent behaviors of dual-channel amorphous InGaZnO (a-IGZO) thin-film transistors (TFTs) under negative bias illumination stress (NBIS) are systematically discussed. The dual-channel comprised two different IGZO layers fabricated by tuning the oxygen flow during deposition. The presence of heterojunctions enhanced field-effect mobility by 1.5× owing to the confinement of carriers in buried channels because of an energy barrier. However, after long periods of NBIS stress, the degradation of a-IGZO TFTs resulted in the entrapment of photo-generated electron–hole pairs at interface defects. The conduction path migrated to the surface channel. Results from extracting the hysteresis window and utilizing capacitance–voltage measurements have indicated a channel migration phenomenon due to the entrapment of electrons and holes at the surface and buried channel interfaces. [ABSTRACT FROM AUTHOR]

In this study, a novel structural design of the p‐type low‐temperature polycrystalline silicon thin‐film transistors (p‐type LTPS TFTs) applied to the pixel structure of displays is proposed. Compared to the conventional pixel structure of displays, the proposed architecture can achieve the aperture ratio improvement by stacking the switch thin‐film transistor and the storage capacitor in a pixel region to enlarge the active space. Therefore, the demands of high‐resolution characteristics, such as a high aperture ratio, and high pixel densities for high‐end displays or novel technologies, can be satisfied by the adoption of the proposed design concept. Furthermore, the discussion of experimental and simulated results in terms of device physics of the transistor indicates that proposed TFTs possess higher performance and reliability properties. By modulating the geometry of the drain‐connected bottom metal in stacked TFTs, output characteristics and hot carrier phenomenon in devices can be further improved. Time‐dependent transfer characteristics, extracted electrical parameters, and numerical simulation results are performed to support our design. [ABSTRACT FROM AUTHOR]

In this study, the negative bias temperature instability (NBTI) under mechanical strain conditions of low-temperature polycrystalline silicon thin-film transistors (LTPS TFTs) with a stress-release structure was investigated. With both electrical and mechanical stresses simultaneously applied, more significant degradation behaviors will be observed in standard TFT devices because mechanical stress makes it easier to generate strain in Si–H bonds, thus benefiting the process of electrochemical reaction. By employing a stress-release shape in the poly channel, mechanical stress, which mainly accumulates at the width edge of the poly-Si/SiO2 interface, is moved away from the main channel; thus, fewer strained Si–H bonds can participate in the electrochemical reaction compared to the standard structure. Therefore, the degradation of devices under strained NBTI is effectively mitigated, such that the reliability of the devices is enhanced. These observations were obtained using electrical characteristics and extraction of the trap state distribution. [ABSTRACT FROM AUTHOR]

In this study, dual-gate thin-film transistors with low-temperature polysilicon as the active channel layer are thoroughly investigated. Under a large current operation where a high voltage is applied, impact ionization occurs near the drain, generating a large number of electron-hole pairs. Owing to the positive bias applied to the gate and drain, holes accumulate on the backside of the channel, which causes an earlier turn-on in the sub-channel, as is observed in the I-V characteristics of the saturation region. By enlarging the highly doped region between the double gates in the channel, the threshold voltage shift can be completely suppressed, and the leakage current rise can be reduced. The electric field simulation using Silvaco TCAD was consistent with the experimental results. Finally, a series transistor structure is used to measure the impact after the operation condition and further verify the physical model. [ABSTRACT FROM AUTHOR]

Etch-stopper-layer (ESL) structured amorphous InGaZnO thin-film transistors (a-IGZO TFTs) were fabricated in this article. Degradation behavior of the a-IGZO TFTs under hot-carrier stress and illumination (HCIS) was investigated. As HCIS time increases, the transfer curve in the saturation region shifts in the negative direction under the forward-operation mode, whereas it shifts in the positive direction under the reverse-operation mode. The HCIS-induced degradation behavior was attributed to charge trapping in the IGZO/ESL interface. To examine the degradation mechanism, the capacitance–voltage measurements were performed. After applying HCIS, it is found that the gate-to-drain capacitance curve shifts in the positive direction and the gate-to-source capacitance curve exhibits two-stage rises. Technology computer-aided design (TCAD) was used to simulate the electric field distribution during the stress, which also confirmed the proposed mechanism. [ABSTRACT FROM AUTHOR]

The quality and stability of thin-film transistors (TFTs) applied to large-scale displays are crucial to their successful manufacture and commercial applicability. This article introduces a TFT manufacturing process in which the source/drain system is defined by hydrogen doping in the dielectric layer of the top-gate amorphous indium gallium zinc oxide (a-IGZO). A size effect related to this system exists where longer channels allow a greater amount of hydrogen to diffuse into the center of the channel. For shorter channels, this results in a lower energy barrier and a shift in the threshold voltage. A physical mechanism model is proposed to verify the abnormal electrical characteristics caused by hydrogen diffusion into the top-gate a-IGZO. The insights provided by these results can be used to further develop TFTs for use in large-scale display applications. [ABSTRACT FROM AUTHOR]

In this article, the effects of redundant electrode width on stability of inverted staggered via-contact structured amorphous indium gallium zinc oxide thin-film transistors (a-IGZO TFTs) under hot-carrier stress (HCS) were investigated. It is found that devices with a larger redundant electrode width have a severer degradation behavior after HCS. Capacitance–voltage measurements were conducted to study the degradation mechanism and technology computer-aided design (TCAD) simulation was employed to understand the different degradation behaviors. [ABSTRACT FROM AUTHOR]

This article investigates the effects of different gate sizes on the electrical characteristics of top-gate organic thin-film transistors. During electrical measurements, an abnormal phenomenon is observed. For a fixed channel length, the current increases with the increasing gate length. In narrow-gate channel devices, gates are used to control carriers of low current density through the side channel area. However, the wide-gate length devices can effectively reduce contact resistance and control large side channels. In this article, integrated systems engineering–technology computer-aided design (ISE-TCAD) simulations were performed for this device containing an active layer with gate cladding. The strength of the electric field extended to the surrounding channel, and the active layer was affected by the cross-wall electric field. The ON-current, under the action of the electric field, improved as the current density of the side channel increased. [ABSTRACT FROM AUTHOR]

This study investigated the reliability of top-gate p-type organic thin-film transistors in vacuum under positive bias stress-induced and positive bias illumination stress-induced instability degradation. The manufacturing process suggested that sidewall dielectric insulating layers are thin. In addition, a shorter organic gate dielectric sidewall causes a larger electric field. Therefore, sidewall electron traps exhibit parasitic transistor characteristics, and the parasitic channel experiences premature conduction, triggering an abnormal hump phenomenon. The mechanism of degradation is verified through electric field simulation; this mechanism is generated owing to the bias stress of the gate. These observations indicate that organic thin-film transistors should be designed with a suitable sidewall insulation thickness to reduce the influence of the sidewall electric field. [ABSTRACT FROM AUTHOR]

This study investigates short channel (length $< 20~\mu \text{m}$) p-type organic thin-film transistor (OTFT) devices which exhibit off-state leakage in their ID–VG characteristics. This phenomenon is attributed to the fact that when a lower positive gate voltage is applied, gate voltage cannot control the back channel, causing back channel leakage. The behavior of back channel leakage is confirmed by the OTFT saturated-regime drain-current formula multiplied by channel length. For dual gate OTFT devices, a top gate voltage sweep and fixed different bottom gate voltages are applied, which indicates that the conduction path is distributed throughout the entire organic semiconductor (OSC) layer, and the back channel leakage can be suppressed by a positive bottom gate voltage. Finally, using dual gate sweeping for a dual gate OTFT device allows the top and bottom gate voltage to simultaneously control the front and back channels, causing a suppression of the back channel leakage, an improvement in subthreshold swing (SS) from 420 to 200 (mV/decade) and an on current increase from $\textsf {7.8}\times \textsf {10}^{-\textsf {8}}$ to $\textsf {3.3}\times \textsf {10}^{-\textsf {7}}$ A at VG-Vsub-threshold = −8 V for the W/L $=50/20~\mu \text{m}$ device. [ABSTRACT FROM AUTHOR]

High-performance ultraviolet (UV) sensors using amorphous indium gallium zinc oxide thin-film transistors (a-IGZO TFTs) can detect ION/IOFF ratio up to 106 and match the a-IGZO panel process. However, it has a reliability issue under long-term detection. When the top gate length of the dual gate TFT is small, it is twice as reliable as a TFT where the top gate fully covers the device. The electrical properties of the device correspond to the a-IGZO energy band, such that the top gate length was positively related to the underlying energy band diagram. The integrated systems engineering technology computer aided design (ISE-TCAD) electric field simulations show that the etch stop layer (ESL) electric field is weak in the small top gate device. This means that it is difficult for the holes to either be trapped in the ESL or to generate ionized oxygen vacancies. [ABSTRACT FROM AUTHOR]

In order to better understand the reliability issues in top-gate a-InGaZnO (a-IGZO) thin-film transistors, this letter investigates the degradation mechanism of a device under self-heating stress (SHS). After applying hot carrier stress, a negative threshold voltage (${V} _{\text {TH}}$) shift, a hump effect, and normally- ON current degradation were found. COMSOL simulation results of hydrogen diffusion in the source and drain (n+ region) of a-IGZO show that Joule heat was generated in the channel during SHS, which leads to hydrogen diffusion in the central and side channels. The unequal channel thermal effect results in a hump effect in the electrical characteristics, and the self-heating effect becomes more prominent as the channel width increases. To minimize the effects of these abnormal phenomena under high current operation in future display applications, a method of creating structural divisions in the channel width is used to aid overall heat dissipation and reduce the effect of SHS degradation. [ABSTRACT FROM AUTHOR]