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Aggressive technology scaling makes modern advanced SRAMs more and more vulnerable to soft errors such as single-node upsets (SNUs) and double-node upsets (DNUs). This paper proposes two SRAM cells; the first one is called Quadruple Cross-Coupled SRAM (QCCS) and the second one is called Sextuple Cross-Coupled SRAM (SCCS). The QCCS cell comprises four cross-coupled input-split inverters to keep stored values, and provides self-recoverability from SNUs at low cost. To improve reliability, the SCCS cell uses six cross-coupled input-split inverters to construct a large error-interceptive feedback loop and hence robustly keep stored values. The SCCS cell can self-recover from all possible SNUs and one part of DNUs; for remaining DNUs, a node-separation mechanism is used to avoid their occurrence. Simulation results demonstrate the robustness of the proposed cells. Moreover, compared with the state-of-the-art hardened cells, i.e., NASA13T, RHBD12T, We-Quatro, Zhang14T, QUCCE12T, DNUSRM, QCCM10T, QCCM12T, S4P8N, and S8P4N, the QCCS cell reduces read access time by 17%, write access time by 19%, power dissipation by 4% and silicon area overhead by 10% on average, while the SCCS cell reduces read access time by 44% as well as write access time by 13% on average at the cost of moderate increase in power dissipation and silicon area overhead. [ABSTRACT FROM AUTHOR]

To meet the requirements of both high reliability and low power in low-orbit aerospace applications, this article first presents a single-event Double-Upset (SEDU) self-Recoverable and single-event Transient (SET) Pulse Filterable (DURTPF) latch design with low power. The DURTPF latch mainly consists of eight mutually feeding-back C-elements (CEs) and an SET pulse filterable Schmitt-trigger (ST). To make an ST behave not only as a pulse filterable ST but also as an error interceptive CE, an input-split ST is created, leading to an enhanced-version of the DURTPF latch, namely DURTPF-EV. The DURTPF-EV latch mainly consists of seven mutually feeding-back CEs including an input-split ST. Simulation results demonstrate both the SEDU self-recoverability and SET pulse filterability of the proposed latches at the cost of moderate silicon area. Using the clock gating technology, the DURTPF latch reduces power dissipation by about 63% on average compared with the state-of-the-art SEDU self-recoverable latch designs that are not SET-pulse filterable. Moreover, the DURTPF-EV latch is more cost-effective and its reliability is also enhanced, making it more suitable for low power and low-orbit aerospace applications. [ABSTRACT FROM AUTHOR]

With complementary metal oxide semiconductor (CMOS) technology scaling down, radiation induced multiple-node upsets (MNUs) that include double-node-upsets and triple-node upsets (TNUs) are becoming more and more an issue in storage cells used for applications constrained by their environment, such as aerospace applications confronted to radiations. This article presents a novel triple-modular redundancy without voter based high-impedance state (HIS) insensitive and MNU-tolerant latch design, namely TMHIMNT, to ensure both high reliability and low cost. The TMHIMNT latch mainly comprises triple clock-gating (CG) based dual-interlocked-storage-cells (DICEs) and four inverters. Through three internal inverters, the values stored in DICEs converge to a common node feeding an output-level inverter, enabling the TMHIMNT latch to tolerate any possible MNU. Simulation results demonstrate the MNU tolerance of the proposed TMHIMNT latch. Due to the disuse of C-elements, the proposed TMHIMNT latch is insensitive to the HIS, making the latch more reliable for aerospace applications. Moreover, compared with the state-of-the-art TNU hardened latch, due to the use of a high-speed path, CG technologies, and fewer transistors, the proposed TMHIMNT latch can achieve 98% delay, 17% power, and 29% area reductions, respectively. [ABSTRACT FROM AUTHOR]

In nano-scale CMOS technologies, storage cells such as latches are becoming increasingly sensitive to triple-node-upset (TNU) errors caused by harsh radiation effects. In the context of information assurance through redundant design, this article proposes a novel low-cost and TNU on-line self-recoverable latch design which is robust against harsh radiation effects. The latch mainly consists of a series of mutually interlocked 3-input Muller C-elements (CEs) that forms a circular structure. The output of any CE in the latch respectively feeds back to one input of some specified downstream CEs, making the latch completely self-recoverable from any possible TNU, i.e., the latch is completely TNU-resilient. Simulation results demonstrate the complete TNU-resiliency of the proposed latch. In addition, due to the use of fewer transistors and a high-speed path, the proposed latch reduces the delay-power-area product by approximately 91 percent compared with the state-of-the-art TNU hardened latch (TNUHL), which cannot provide a complete TNU-resiliency. [ABSTRACT FROM AUTHOR]

This paper first presents a double-node upset (DNU) protected and sextuple cross-coupled static-random-access memory (SRAM) cell, i.e., SCCS-18T, for aerospace applications. The cell can recover from each possible single-node upsets (SNUs) as well as partial DNUs due to its formed large feedback loop that can retain values and intercept errors. To improve DNU self-recoverability, an enhanced version of the SCCS-18T cell, namely SCCS-18T-EV, is proposed. Due to the new formed structure, the SCCS-18T-EV can recover from more DNUs. Since parallel access transistors are used, the proposed cells have optimized read/write performance. Simulation results demonstrate the node-upset tolerance as well as the optimized operation performance of the proposed SCCS-18T and SCCS-18T-EV cells compared to existing SRAM cells. [ABSTRACT FROM AUTHOR]

To tolerate Double Nodes Upset (DNU) and Triple Nodes Upset (TNU), we propose the DNU Tolerant Latch (DNUL) and TNU Tolerant Latch (TNUL) with low overhead and high stability. Both DNUL and TNUL are composed of the looped Input-Split C-Elements (ISCs) and the C-Elements (CEs) at the output level. Based on the robust blocking ability of the ISCs, the simultaneous upset of all inputs of the CE can be blocked. DNUL and TNUL have low overhead with fewer transistors by utilizing the clock-gating and high-speed path technique. Exhaustive HSPICE simulation shows that, in contrast to previous DNU tolerant latches, DNUL is optimal in terms of delay, power consumption and product of delay and power (PDP), but is suboptimal in terms of area overhead. Compared with all alternative structures, TNUL is the best in terms of delay and PDP. Compared to other TNU tolerant latches, TNUL achieves a suboptimal power consumption and area overhead. Variation analysis shows that DNUL and TNUL are insensitive to variations of process, voltage and temperature (PVT). [ABSTRACT FROM AUTHOR]

Technology scaling of integrated circuits into nanoscale feature sizes has decreased the effectiveness of existing single-node-upset and double-node-upset hardening techniques in harsh radiation environments. This paper proposes a low-power triple-node-upset resilient latch (LP-TNU) based on approximate C-elements and cross-interlocking structure. The proposed LP-TNU achieves TNU resilience based on the filtering feature of C-elements and redundant feedback structure. Extensive simulation results demonstrate the robustness of the proposed latch. The proposed LP-TNU achieves extremely low power consumption because of the clock-gating technique and fewer transistors. Compared with reference latches, the proposed latch is the most robust with the lowest power consumption and power-delay-product. In addition, compared with TNU-resilient latches such as DNUHL, LCTNURL, TNURL, HLTNURL and TNUSH, the proposed LP-TNU achieves a 62.68 % reduction on average in power consumption, 9.54 % reduction on average in delay, 20.75 % reduction on average in area overhead, 69.98 % reduction on average in the area-power-delay product. At the same time, the proposed latch is insensitive to variations of the process, supply voltage, and working temperature. • With technology scaling, integrated circuits in harsh radiation environments are more vulnerable to multiple-node-upset such as double-node-upset and triple-node-upset. • This paper proposes a low-power triple-node-upset resilient latch (LP-TNU) based on approximate C-elements and cross-interlocking structure. • Compared with reference latches, the proposed latch possesses both good robustness and lower powerconsumption, and is less sensitive to PVT variations. [ABSTRACT FROM AUTHOR]