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With quality and reliability requirements moving toward the ppb level, latent defects have become a major bottleneck. This article introduces a new metric, called difference in the distance to mean value (DDtM), that exploits the latent defect information present in measurements of an integrated circuit (IC) carried out under more than one operating condition. The use of this metric improves the latent defect coverage provided by post-processing (PP) techniques at no additional cost. The DDtM tracks, for each measured variable, shift in the distance from the IC’s measured value to the population mean value when the conditions applied to the IC change. To demonstrate the effectiveness of the DDtM metric, two circuits that are part of an industrial mixed-signal IC are used as case studies. The results show that the use of the DDtM metric improves latent defect coverage regardless of the PP technique used, providing up to a 60% improvement in coverage compared to the results obtained using the same measurement data but without DDtM. [ABSTRACT FROM AUTHOR]

Currently, the semiconductor industry requires test escape levels that approach the ppb level for application domains, such as automotive. Such quality levels, however, can only be reached if latent defects are screened out, as they have become the major bottleneck in analog and mixed-signal IC testing. Latent defects can be activated using accelerated aging, but this procedure has several drawbacks. Most notably, activation can move latent defects to the product lifetime that, otherwise, would not even have expressed themselves. Therefore, methods are needed that allow the detection of these defects without using activation. Developing such methods, however, has been hampered by the lack of compact latent defect models that allow simulating circuits affected by this type of defect. This article alleviates this problem by experimentally validating a recently presented compact model for latent defects and establishing the practical range of model values that should be used in simulations. The experiments performed on a 0.35- $\mu \text{m}$ technology consist of characterizing transistors containing latent defects that have been artificially introduced by etching pinholes in their gate. The measurement results corroborate that the drain current in transistors with defects increases with the area and depth of the defect, and that this behavior can be accurately modeled using an effective ${t}_{ox}$ value. [ABSTRACT FROM AUTHOR]