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This brief proposes a novel current output resistor string DAC architecture implemented for a 10-bit resolution. The DAC consists of a 6-bit coarse resistor string DAC followed by a 4-bit multi-input interpolation amplifier, and a voltage to current conversion stage. Use of a multi-input interpolation amplifier with shared resistive load provides accurate fine conversion with reduced resistor count. The current output DAC has high output impedance from the regulated current source architecture. The prototype was fabricated in a 0.18 μm CMOS process technology. The measured integral non-linearity (INL) and differential non-linearity are 0.5 LSB and 0.4 LSB, respectively. The chip consumes static power 0.54 mW at 1.8 V supply and occupies 0.042 mm2 area. [ABSTRACT FROM AUTHOR]

Ionic liquid/ionogel gate dielectrics can provide significant advantages for transistor architectures that utilize high surface area semiconductors and/or nonplanar substrates because of their cleanroom-free, liquid-based processability and their inherently large electrostatic double layer capacitance. These attributes of ionogels have already enabled the facile fabrication of several up-and-coming transistor devices geometries for which a highly conformal interface between the electrolyte gate dielectric and the semiconductor is readily achievable, and remote gating with a nonaligned gate electrode is possible. Further, ionogel gating can improve device performance to maximize current densities at low operating voltages. This Perspective highlights three classes of emerging transistor architectures, namely, vertical transistors, surround gate transistors, and thread/fiber-based transistors, and provides several key examples of instances where ionogel gating has either already enabled or still stands to improve device fabrication and performance. [ABSTRACT FROM AUTHOR]

This paper presents a new inverter-based architecture that implements an asynchronous delta–sigma modulator. Different from the classical architecture, it features an input transconductor that promotes a differential and high input impedance that makes it easier to interface with sensors and other front ends. Furthermore, an inverter-based relaxation oscillator accomplishes the required hysteresis through a charge redistribution process, which exhibits lower time delay than hysteretic comparators, besides saving power from quiescent biasing. The circuit has been implemented in 130-nm CMOS digital process using halo-implanted transistors. In addition, transistors are biased in weak inversion and are implemented using distributed layout to reduce power consumption besides mitigating halo-implants undesired effects. Supplied with 0.25 V, the proposed architecture consumes 20 nW with just −55 dB of third harmonic distortion, making it suitable for wearable biomedical applications where energy consumption, low bandwidth, and moderate resolution are required. [ABSTRACT FROM AUTHOR]

In this paper, we present a single-bit clock-less asynchronous delta–sigma modulator (ADSM) operating at just 0.25 V power supply. Several circuit approaches were employed to enable such low-voltage operation and maintain high performance. One approach involved utilizing bulk-driven transistors in subthreshold region with transconductance-enhancement topology. Another approach was to employ distributed transistor layout structure to mitigate the effect of low output impedance due to halo drain implants employed in today’s digital CMOS process. The ADSM achieved a characteristic center frequency of 630 Hz. It had an effective signal-to-noise-plus-distortion ratio (SNDR) of 58 dB or effective number of bits (ENOB) 9 b and just 28-nW power dissipation. A detailed analytical model capturing the effect of nonidealities of the individual circuit components is also presented for the first time with a close agreement with experimental results. [ABSTRACT FROM AUTHOR]

n ultra low power gm-C filter for low cut-off frequency bio-medical implantable applications is presented in this paper. The design is based on a novel trans-conductance stage operating in the sub-threshold region with a PVT independent fixed replica gm biasing circuit. The significant variation in gm with respect to temperature due to channel length modulation is corrected using a parallel combination of two gm blocks of different value. The circuit performance remains nearly constant for a supply voltage range of 1.1-1.7 V. A general biquad filter has been implemented and simulations show about 1% variation in the 3-dB bandwidth (in the range of few hertz) for a temperature range of −30 to 110°C. The circuit has been implemented using 0.5 μm CMOS technology with a nominal supply voltage of 1.2 V and power consumption for each gm block is 55.3 nW. [ABSTRACT FROM AUTHOR]