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This article introduces a novel vertical doping-less tunnel field-effect transistor (TFET), in which instead of using metal to induce charge plasma in the source region, cladding layer is utilized to engineer the energy bands in this region. The fabrication process flow of this highly scalable TFET is presented in detail. We employ a calibrated numerical simulator to study the switching and analog/RF performance of the proposed device. Moreover, the impact of different structural parameters and parasitic phenomena, such as interface trap charges and quantum confinement, on the device performance are investigated. According to the obtained results, our transistor exhibits desirable analog and digital performance including ${I}_{ \mathrm{\scriptscriptstyle ON}} = 30.02 ~\mu \text{A}/\mu \text{m}$ , ${I}_{ \mathrm{\scriptscriptstyle ON}}/{I}_{ \mathrm{\scriptscriptstyle OFF}}$ ratio of $1.57\times10$ 11 and ${f}_{T} = 89.31$ GHz. [ABSTRACT FROM AUTHOR]

In this article, we introduce a double-gate nanotube tunneling field-effect transistor with high scalability based on the Si/Ge heterostructure. Our device includes two Ge source regions which are covered by the gate metal to facilitate line tunneling in these regions. The tunneling charge carriers flow toward the drain region through two n− Si channel regions. The manufacturing process of the proposed transistor is fully compatible with CMOS technology. The performance of the device is investigated by employing a numerical simulator which is calibrated to experimental data. We achieved a remarkable switching performance including a minimum subthreshold swing (SS) of 10 mV/dec, an ${I} _{ \mathrm{\scriptscriptstyle ON}}/{I} _{ \mathrm{\scriptscriptstyle OFF}}$ ratio of 3.92 $\times 10^{{7}}$ , an ON-state current of 52.19 $\mu \text{A}/\mu \text{m}$ , and a drain-induced barrier lowering of 45 mV/V for the device; moreover, the ambipolar conduction completely vanished. [ABSTRACT FROM AUTHOR]

The emerging demand for high-capacity wireless mobile communication and the advent of the Internet of Things and fifthgeneration communication standards have motivated the development of high-performance transceivers. The power amplifier (PA) is the most critical part in the transmit path and dominates the transceiver's performance, including coverage range, data rate, spectrum compliance, and dc power dissipation. Integration capability and the relatively low cost of complementary?metal-oxide-semiconductor (CMOS) technology, on the other hand, have propelled it into the wireless market. CMOS technology enables complete system-on-chip solutions, resulting in a simple front-end assembly process, straightforward testing, and improved reliability. Today, in addition to the baseband, including the modulator/demodulator circuit, a big portion of the RF front end of the transceiver circuit is implemented in CMOS technology. [ABSTRACT FROM PUBLISHER]

Design and implementation of high-efficiency microwave and mm-wave CMOS silicon-on-insulator (SOI) power amplifiers (PAs) based on a stacked cell approach is presented. Two stacked cell PAs have been implemented in GlobalFoundries 45-nm CMOS SOI technology. The first PA operating at K-band (24–28 GHz) is designed with three stacked triple Cascode cells. Each cell uses three standard transistors with separate layout. At 24 GHz, the K-band PA biased under a supply voltage of 10.8 V measures a maximum linear power gain of 13 dB, a saturated output power P \mathrm {SAT} of 25.3 dBm, a −1-dB output power P 1\mathrm {dB} of 23.8 dBm, and a peak power-added efficiency (PAE) of 20%. The second PA targeted at U-band frequencies is designed with two stacked triple Cascode cells. Transistors in each cell have a combined layout that reduces parasitic capacitances, leading to significant improvement in the PAE at mm-wave frequencies. The U-band PA operates from 42 to 54 GHz. At 46 GHz, and under a supply voltage of 6 V, it measures a saturated output power ( P \mathrm {SAT} ) of 22.4 dBm, a linear gain of 17.4 dB, and an unprecedented peak PAE of 42%. [ABSTRACT FROM PUBLISHER]

A fully integrated broadband power amplifier (PA) is implemented in a standard 45-nm CMOS SOI technology. The PA is designed using a dynamically biased stacked SOI transistor approach, which constructively adds drain–source voltage signals of individual transistors while keeping their gate voltages within source and drain voltage limits. The design overcomes both low gate-oxide breakdown and low source-drain reachthrough voltages of nanoscale CMOS transistors. The number, size, and topology of transistors in the stack are optimized to deliver a relatively high linear output power over a wide range of frequencies. The amplifier under a supply voltage of 4.5 V measures a flat gain of 6 dB with -1-dB bandwidth of 6 to 26.5 GHz (X-band to K-band). At 18 GHz, the PA under a supply voltage of 7.2 V measures a saturated output power (PSAT) of 26.1 dBm (\sim400 mW), a linear output power (P1\ dB) of 22.5 dBm, and a peak power-added efficiency (PAE) of 11%. With a lower power supply voltage of 4.5 V, the PAE increases to more than 20% and stays above 17% with relatively constant PSAT and P1\ dB for several measured frequencies in the range of 6 to 20 GHz. The PA occupies an active chip area of only 0.16 \mm^2. [ABSTRACT FROM AUTHOR]

A wideband radio frequency power amplifier (RF PA) is implemented with a stack of 16 low-breakdown-voltage thin-oxide transistors in a standard 45-nm CMOS SOI technology. A combination of dynamic-biasing and stacking prevents all breakdown mechanisms when the PA operates under large voltage swings and facilitates an output impedance close to 50 \Omega without a need for an output-matching network. Using a post-fabrication process, the conductive Si substrate of the CMOS SOI PA is etched away and replaced by a semi-insulating aluminum nitride (AlN) substrate to reduce the effect of substrate parasitic capacitances and improve the PA's performance. A small-signal gain of 12.2 dB at 1.8 GHz is achieved with a -3-dB bandwidth from 1.5 to 2.6 GHz. For high-reliability operation, the PA is biased with a 15-V power supply and a small transistor current density of 0.2 \mA/\mu\m and delivers a saturated output power (PSAT) of 30.2 dBm and a peak power-added efficiency (PAE) of 23.8%. For a wide range of measured frequencies from 1.5 to 2.4 GHz and under a lower supply voltage of 12 V, PSAT and P1\ dB remain above 27.9 and 24.8 dBm, respectively, with peak PAE above 20%. In terms of output power, efficiency, and linearity, the CMOS PA on AlN substrate outperforms its Si counterpart, while both PAs deliver good power performance despite utilizing thin-oxide low-breakdown-voltage transistors. [ABSTRACT FROM AUTHOR]

A mask programmable technology to implement RF and microwave integrated circuits using an array of standard 90-nm CMOS transistors is presented. Using this technology, three wideband amplifiers with more than 15-dB forward transmission gain operating in different frequency bands inside a 4-22-GHz range are implemented. The amplifiers achieve high gain-band- width prroducts (79-96 GHz) despite their standard multistage designs. These amplifiers are based on an identical transistor array interconnected with application specific coplanar waveguide (CPW) transmission lines and on-chip capacitors and resistors. CPW lines are implemented using a one-metal-layer post-processing technology over a thick Parylene-N (15μm) dielectric layer that enables very low loss lines (~0.6 dB/mm at 20 GHz) and high-performance CMOS amplifiers. The proposed integration approach has the potential for implementing cost-efficient and high-performance RF and microwave circuits with a short turnaround time. [ABSTRACT FROM AUTHOR]

Discusses the design methodology, processing technology and characterization of high-gain heterojunction-bipolar-transistor-based distributed amplifiers. Attenuation compensation; Bit error rate.

A fully-integrated wideband power amplifier (PA) operating in 9–15 GHz range is implemented in a standard 45 nm CMOS SOI technology. The PA is designed with three dynamically-biased stacked Cascode cells (6 stacked transistors) to overcome the low breakdown voltages of nanoscale CMOS transistors. The stacked Cascode cells ensure stable operation and facilitate high gain, and high optimum load impedance, leading to high output power, high efficiency and good linearity characteristics over the entire bandwidth. The unbalanced amplitude and phase of drain-source voltage signals caused by internodal parasitic capacitance are equalized by adjusting the sizing of transistors. With a supply voltage of 4.8 V at 12 GHz, the measured saturated output power and linear power are 22.5 dBm and 19.2 dBm, respectively, while the peak power-added efficiency (PAE) is 19.2%. At a reduced power supply of 3.6 V, the PA achieves peak PAE of 25.7% where the drain efficiency reaches 40.7%. Including its pads, the PA occupies a compact chip area of 0.22 mm^2. [ABSTRACT FROM PUBLISHER]

The low frequency (1/f) noise in single SnO2 nanowire transistors was investigated to access semiconductor-dielectric interface quality. The amplitude of the current noise spectrum (SI) is found to be proportional to Id2 in the transistor operating regime. The extracted Hooge’s constants (αH) are 4.5×10-2 at Vds=0.1 V and 5.1×10-2 at Vds=1 V, which are in general agreement with our prior studies of nanowire/nanotube transistors characterized in ambient conditions. Furthermore, the effects of interface states and contacts on the noise are also discussed. [ABSTRACT FROM AUTHOR]

Single ZnO nanowire (NW) transistors fabricated with self-assembled nanodielectric (SAND) and SiO2 gate insulators were characterized by low-frequency noise and variable temperature current-voltage (I-V) measurements. According to the gate dependence of the noise amplitude, the extracted Hooge’s constants (αH) are ∼3.3×10-2 for SAND-based devices and ∼3.5×10-1 for SiO2-based devices. Temperature-dependent I-V studies show that the hysteresis of the transfer curves and the threshold voltage shifts of SAND-based devices are significantly smaller than those of SiO2-based devices. These results demonstrate the improved SAND/ZnO NW interface quality (lower interface-trap states and defects) in comparison to those fabricated with SiO2. [ABSTRACT FROM AUTHOR]