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Serious agglomeration of ultrathin TiSix employed in source–drain (S–D) ohmic contacts after high-temperature annealing was manifested in previous work. This severely restricts its application in state-of-the-art DRAM peripheral 3-D FinFET transistors. In this work, the effects of hafnium (Hf) interlayer on the thermal stability of ultrathin TiSix in TiSix/n+-Si ohmic contacts were systematically studied. As-prepared ultrathin TiSix and TiSix/n+-Si ohmic contacts with 0-, 1-, 2-, and 3-nm Hf interlayers were characterized by means of specific contact resistivity ($\rho _{\text {c}}$), transmission electron microscopy (TEM), X-ray diffraction (XRD), and X-ray photoelectron spectroscopy (XPS). It is found that compared to the counterparts with 0-, 2-, and 3-nm Hf, the presence of 1-nm Hf interlayer is proven to be effective in enhancing the thermal stability of ultrathin TiSix significantly. With 1-nm Hf, amorphous HfO2, and Hf silicate are readily formed, which hinders the interdiffusion between Ti and Si atoms and resultant agglomeration of ultrathin TiSix films. This is thought to be responsible for such a remarkably enhanced thermal stability of ultrathin TiSix in TiSix/n+-Si ohmic contacts. [ABSTRACT FROM AUTHOR]

In this work, the thermal stability issue of ultrathin Ti-based silicide (TiSix) in prospective dynamic random access memory (DRAM) peripheral 3D FinFET transistors was systematically studied. As-prepared TiSix/n+-Si contacts and ultrathin TiSix films with different annealing temperatures, were characterized by means of specific contact resistivity (ρc), sheet resistance measurement, X-ray diffraction (XRD), transmission electron microscopy (TEM) and energy-dispersive X-ray spectroscopy (EDX). It is shown that the specific contact resistivity (ρc) for TiSix/n+-Si contacts gradually degrades with the increase of annealing temperature in the range 450–900 °C. In addition, it is revealed that though thick TiSi2 is conventionally known as thermal stable silicide, the agglomeration of ultrathin TiSix in the source/drain regions of 3D FinFETs still occurs after DRAM annealing typically at 750 °C for few hours. This agglomeration is thought to be responsible for the deterioration of ρc for TiSix/n+-Si contacts. [ABSTRACT FROM AUTHOR]

This paper presents a method to improve source/drain extension (SDE) ion implantation (I/I) process for sub-20 nm node FinFETs with no extra step in transistor process. Traditionally, SDE I/I process needs a large implant tilt angle and a high dose to obtain a heavy and conformal doping. However, this process leads to implantation shadow effects and Si-fin amorphization. These drawbacks can be removed in our new approach when SDE I/I is modified and moved after S/D epitaxy process (SDE I/I-last). Because of the facet planes of the SiGe layer, the ions are allowed to be implanted with small tilt. This is helpful to avoid shadow effects of implantation and to keep the low defect density in the S/D. As a result, the external resistance (REXTRNL) is not high and the strain relaxation is minor in S/D epitaxy layer. Finally, p-type FinFETs with 25 nm gate length with SDE I/I-last are fabricated. These new FinFETs demonstrate ~ 50% on-state current (ION) improvement compared to those transistors fabricated by traditional method. [ABSTRACT FROM AUTHOR]

In this study, the integration of SiGe selective epitaxy on source/drain regions and high-k and metal gate for 22 nm node bulk pMOS transistors has been presented. Selective SiGe growth (0.35 ≤ × ≤ 0.40) with boron concentration of 1-3 × 10 cm was used to elevate the source/drain. The main focus was optimization of the growth parameters to improve the epitaxial quality where the high-resolution x-ray diffraction (HRXRD) and energy dispersive spectrometer (EDS) measurement data provided the key information about Ge profile in the transistor structure. The induced strain by SiGe layers was directly measured by x-ray on the array of transistors. In these measurements, the boron concentration was determined from the strain compensation of intrinsic and boron-doped SiGe layers. Finally, the characteristic of transistors were measured and discussed showing good device performance. [ABSTRACT FROM AUTHOR]

GeSn alloys have already attracted extensive attention due to their excellent properties and wide-ranging electronic and optoelectronic applications. Both theoretical and experimental results have shown that direct bandgap GeSn alloys are preferable for Si-based, high-efficiency light source applications. For the abovementioned purposes, molecular beam epitaxy (MBE), physical vapour deposition (PVD), and chemical vapor deposition (CVD) technologies have been extensively explored to grow high-quality GeSn alloys. However, CVD is the dominant growth method in the industry, and it is therefore more easily transferred. This review is focused on the recent progress in GeSn CVD growth (including ion implantation, in situ doping technology, and ohmic contacts), GeSn detectors, GeSn lasers, and GeSn transistors. These review results will provide huge advancements for the research and development of high-performance electronic and optoelectronic devices. [ABSTRACT FROM AUTHOR]

The international technology roadmap of semiconductors (ITRS) is approaching the historical end point and we observe that the semiconductor industry is driving complementary metal oxide semiconductor (CMOS) further towards unknown zones. Today's transistors with 3D structure and integrated advanced strain engineering differ radically from the original planar 2D ones due to the scaling down of the gate and source/drain regions according to Moore's law. This article presents a review of new architectures, simulation methods, and process technology for nano-scale transistors on the approach to the end of ITRS technology. The discussions cover innovative methods, challenges and difficulties in device processing, as well as new metrology techniques that may appear in the near future. [ABSTRACT FROM AUTHOR]

When the international technology roadmap of semiconductors (ITRS) started almost five decades ago, the metal oxide effect transistor (MOSFET) as units in integrated circuits (IC) continuously miniaturized. The transistor structure has radically changed from its original planar 2D architecture to today's 3D Fin field-effect transistors (FinFETs) along with new designs for gate and source/drain regions and applying strain engineering. This article presents how the MOSFET structure and process have been changed (or modified) to follow the More Moore strategy. A focus has been on methodologies, challenges, and difficulties when ITRS approaches the end. The discussions extend to new channel materials beyond the Moore era. [ABSTRACT FROM AUTHOR]