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Mechanical computing has garnered significant interest as a supplement to traditional electronic computing, which often grapples with issues like high power consumption, security vulnerabilities, and susceptibility to extreme environmental conditions such as intense heat and radiation. Yet, most research in mechanical computing has been limited to the ad hoc design of simple logic gates and has not fully achieved the implementation of simple arithmetic computation within an electricity‐free framework. Additionally, progress in environmentally adaptive computing, crucial for decentralized intelligence, has also been slow. New ground is broken with the development of a mechanical transistor that synergizes a Kirigami thermomechanical sensor and a bistable actuator, enabling in‐memory computing for combinational and sequential logic. The design stands out by employing modular construction, symmetry breaking, and nonlinear materials, crafting logic gates, and memory units that respond to environmental stimuli through thermal delay. These transistors integrate design and material intelligence to establish nonvolatile memories, essential for logic‐in‐memory, and align thermal transport with mechanical deformation for environmental responsiveness. The mechanical transistor heralds a new age in mechanical computing, proving to be as versatile and vital as the electronic transistor has been in the era of modern computing. [ABSTRACT FROM AUTHOR]

Total ionizing dose (TID) degradation is caused by radiation-induced charge buildup in oxides. Radiation hardening of silicon-on-insulator (SOI) devices with deep submicrometer nodes or nanonodes is mainly concerned with the field oxide and buried oxide. In this article, a back-channel adjustment technique for TID hardening is proposed. The technique is compatible with the 130-nm partially depleted silicon on an insulator (PDSOI) commercial process with no extra effort applied to the design. After testing the key electrical parameters and characterizing the radiation tolerance of the typical T-gate I/O nMOS devices, the results show that the radiation tolerance of the devices can reach more than 1 Mrad(Si) with the back-channel adjustment technique, and electrical performance is comparable to that of commercial process devices. [ABSTRACT FROM AUTHOR]

A special total-ionizing-dose-induced short channel effect in thin-film partially depleted silicon-on-insulator (PDSOI) technology is found. Short devices suffer more significant total-ionizing-dose-induced threshold voltage shift of the front-gate main transistor. The devices under pass-gate (PG) bias show worse threshold voltage shift of the front-gate main transistor than the devices under ON bias, which reveal that the trapped charges in the buried oxide layer are more responsible for these phenomena. Through the simulation of the electric field under PG bias by TCAD, we found that devices with different lengths can be uniformly divided into four regions. Then we combined the partially full depletion model with charge-sharing model and made a qualitative analysis of this effect. On this basis, we proposed a quantitative analysis model. Through this model, we can calculate the threshold voltage shift of the front-gate main transistor through the threshold voltage shift of back-gate main transistor. [ABSTRACT FROM AUTHOR]

Two radiation hardening processes for shallow trench isolation (STI), i.e., Si+ implantation and STI oxide nitridation are investigated, including the impact on nominal electrical characteristics and radiation hardness. The total ionizing dose effects of the nMOS devices are proved to be sensitive to the STI radiation hardening process conditions. There are optimum process conditions to achieve the best effectiveness of radiation hardening. Then, a 130-nm radiation-hardened PDSOI technology has been developed. The radiation hardness is verified by static random access memories with small storage capacities. [ABSTRACT FROM AUTHOR]

The influences of silicon-rich shallow trench isolation (STI) on total ionizing dose (TID) hardening and gate oxide integrity (GOI) in a 130 nm partially depleted silicon-on-insulator (SOI) complementary metal-oxide semiconductor (CMOS) technology are investigated. Radiation-induced charges buildup in STI oxide can invert the parasitic sidewall channel of the n-channel transistor, which will increase the off-state leakage current and decrease the threshold voltage for the main transistor. Compared with the general STI process, the silicon-rich STI process can significantly suppress the increase in leakage current and negative shifts in subthreshold region induced by the total dose radiation, implying TID hardening for STI trench oxide. However, the silicon-rich STI process has a deleterious impact on GOI. It leads to the thin gate oxide thickness at trench corner and lowers the gate oxide breakdown voltage. Issues of gate oxide integrity induced by silicon-rich STI are investigated in this paper, and an optimized process to solve this problem is proposed and examined. Finally, the TID response of the optimized silicon-rich STI process is presented in comparison to the general and silicon-rich STI processes. [ABSTRACT FROM AUTHOR]

Single-event upsets are studied in digital storage cells in 130nm CMOS bulk Si and PDSOI technologies. The sensitivity of SEU to different technologies and hardening approaches is explored by using heavy-ion radiation experiments. Error numbers in D flip-flop chains are used to determine the impact of various cell designs and PDSOI hardening technique on upset sensitivity. Various flip-flops are designed and connected as shift-register chains, and the error numbers induced by irradiation are recorded to examine the effectiveness of the PDSOI technology. It was found that PDSOI technology has better performance in terms of upset robustness versus bulk Si at the 130nm technology node. The same design structure implemented in PDSOI technology has higher SEU threshold LET and much lower saturation cross section due to its full dielectric isolation structure which does not allow the charge generated in the substrate to be collected by the electrically active junctions in the thin top region of the device and reduces the sensitive volume of p-n junctions in the transistor. As shown in the experiment result, NRH_SOI (not radiation hardening SOI) saves about 25% area while having much lower SER versus DICE_Si, which means PDSOI still has obvious advantage at reducing SEU rate, even though its necessary body contact has to consume certain extra area. [ABSTRACT FROM PUBLISHER]

Abstract: A new phenomenon, for the first time, shows that radiation-induced body effect factor decrease in NMOS transistors is presented. The results indicate that body effect factor shift decreases as the total ionizing dose (TID) level increases in NMOS transistors, especially in the narrow-channel ones, which can be considered as one of the radiation-induced narrow-channel effect (RINCE). A first-order model is developed by applying charge conservation principle. Good agreement is obtained by comparing the modeling with experimental results. Finally, some implications to mitigate the RINCE effect are discussed. [Copyright &y& Elsevier]

Abstract: The response of single flash cell in a 180-nm flash technology to total ionizing dose (TID) is studied. The results indicate that the erased cell flips at a dose level of 100krad(Si), whereas the programmed cell does not even at the dose level up to 1Mrad(Si). This asymmetric phenomenon is attributed to the difference between the reference current of the comparator circuit and the intrinsic current of the flash cell. For the first time, we show that the irradiation-induced flash cell drain-current variation does not saturate at the intrinsic value, i.e. the drain current of a device with neutrally charged floating gate. After degrading to the intrinsic state, the read current of the erased cell gradually increases while the programmed cell continues to increase and then slightly drops back. Radiation tolerance comparison of single flash cell, I/O transistors and high-voltage (HV) transistors demonstrates that HV NMOS is most susceptible to ionizing radiation. The radiation tolerance of the circuit level is also evaluated from the elementary devices. [Copyright &y& Elsevier]

Radiation enhanced drain induced barrier lowering (DIBL) effect under different bias conditions was experimentally observed and verified by 3D simulation for deep submicron MOSFETs with shallow trench isolation (STI) oxides. The off-state leakage current increased significantly after total ionizing dose (TID) above 200 krad(Si) for PASS ,OFF and ON bias condition. The irradiated devices exhibited enhanced DIBL effect, that is the off-state leakage current increases with drain voltage and DIBL parameter increases with TID. The oxide trapped charge in the STI sidewall enhances the DIBL by decreasing the drain to gate coupling, enhancing the electric field near the STI corner, and increasing the surface potential of lowly doped substrate along STI sidewall. A simple dipole theory describing the enhanced DIBL phenomenon is introduced. The phenomenon is a result of the electrostatic effect, which concentrates drain field on channel into the source along shallow trench isolation oxide. Effective non-uniform charge distribution is applied in the 3D simulation for the radiation enhanced DIBL effect. Good agreement between experiment and simulation results is demonstrated. [ABSTRACT FROM AUTHOR]

A reverse substrate bias is known to increase the threshold voltage and reduce the off-state leakage current, which is of great interest from a radiation perspective in space applications. In this work, substrate biases during both irradiation and post-irradiation test on the impacts of total ionizing dose effects in a 180 nm CMOS technology are studied. The results indicate that a negative substrate bias during irradiation impairs the radiation hardness while a negative substrate bias during post-irradiation test improves the radiation hardness for nMOS transistors. A simple model is proposed to discuss the net result including the both effects. We find that the substrate bias for radiation hardening does not always work in some special conditions, such as the device with very low body doping and the STI which is very sensitive to the electric field for the buildup of charge. [ABSTRACT FROM AUTHOR]

The effects of total ionizing on a 180-nm CMOS technology are comprehensively studied. Firstly, we show new results on the hump effect which has strong relationship to the STI corner oxide thickness. Secondly, the leakage current degradation in various devices after radiation is investigated. For the intra-device leakage, both body doping concentration and STI corner thickness play very important roles. For the inter-device leakage, due to the low electric field at the STI bottom, it is found to be insensitive to ionizing radiation. Thirdly, a method for extracting the effective threshold voltage of the sidewall parasitic transistor is proposed by studying the leakage output characteristics. Finally, we find that the drain saturation current increases in NMOS transistors after radiation, especially in the narrow-channel ones. [ABSTRACT FROM AUTHOR]

Abstract: Total ionizing dose (TID) response in core, input/output (I/O) and high voltage (HV) transistors for 180nm flash memory technology is comprehensively investigated. Great influence by irradiation is observed for all these transistors, including threshold voltage shift, appearance of subthreshold hump effect and increase of off-state leakage current. Also, we found that the higher the drain voltage, the larger increase of the off-state leakage, which is well known as radiation enhanced drain induced barrier lowering (DIBL) effect. Radiation enhanced DIBL effect leads to worse characteristic degradation of transistor. The HV transistor is the most sensitive parts in flash memory control circuitry. [Copyright &y& Elsevier]

Abstract: The effect of size and substrate bias conditions after irradiation on the total ionizing dose response of high voltage devices for flash memory has been investigated. Different sensitivity of transistors with different gate width was observed, which is well known as the radiation induced narrow channel effect. A charge sharing model was used to explain this effect. The negative substrate bias voltage after irradiation showed considerable impact on the parasitic transistor’s response by suppressing leakage current. [Copyright &y& Elsevier]

In this work, single transistor latch effects induced by total dose irradiation for 0.13 μm partially depleted silicon-on-insulator (PDSOI) n-type metal-oxide-semiconductor field effect transistors (NMOSFETs) were investigated. The front gate transfer characteristics under different bias configurations with forward and reverse gate voltage sweep are characterized to evaluate the latch phenomenon. The results indicate that transmission–gate (TG) bias is the worst case bias for total dose induced latch, and the onset drain voltage required for latchup degrades as the irradiation level increased. Experiments and 2D simulations are performed to analyze the positive trapped charge in the buried oxide (BOX) and its impact on the latch effect. It is demonstrated that the irradiation can enhance the impact ionization and thereby make the device more sensitive to latchup, especially at negative gate voltage. Moreover, the radiation induced coupling effect between the front gate and back gate can make the PDSOI devices in our experiments behave like the fully depleted (FD) ones. [ABSTRACT FROM AUTHOR]

In this paper, a high-performance and highly-stable soft error resistant 12T (HPHS12T) SRAM cell is proposed. Based on polarity reversal design and NMOS stacked structure, the proposed HPHS12T cell can recover from any single event upsets (SEU) induced at all its sensitive nodes and even single event multiple-node-upsets (SEMNU) induced at its internal storage node pair Q-QN, while also having the maximum read static noise margin (RSNM) and write noise margin (WNM), as well as excellent write-ability. Though the HPHS12T cell exhibits a larger static hold power, it has the best overall performance of all the other cells. This is proven by having the highest electrical quality metric (EQM) value, thus making the proposed cell a better choice for space applications. • Since only 2 PMOS transistors are used, the proposed cell mitigates parasitic bipolar effect and provides better soft error tolerance. • Because of its polarity reversal design, the HPHS12T can recover from any SEU induced at any of its sensitive nodes. as well as SEMNU induced at its internal node pair. • Compared to all other considered cells, the HPHS12T cell shows the shortest write delay and largest read static noise margin (RSNM), write noise margin (WNM), and wordline write trip voltage (WWTV). [ABSTRACT FROM AUTHOR]