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Your search keyword '"Ghani T"' showing total 2 results
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2 results on '"Ghani T"'

1. Drive current enhancement in p-type metal–oxide–semiconductor field-effect transistors under shear uniaxial stress.

Author

Shifren, L., Wang, X., Matagne, P., Obradovic, B., Auth, C., Cea, S., Ghani, T., He, J., Hoffman, T., Kotlyar, R., Ma, Z., Mistry, K., Nagisetty, R., Shaheed, R., Stettler, M., Weber, C., and Giles, M. D.

Subjects
METAL oxide semiconductor field-effect transistors, SEMICONDUCTORS, FIELD-effect transistors, TRANSISTORS, CRYSTALS, ELECTRIC conductivity
Abstract

Recent attention has been given to metal–oxide–semiconductor field-effect transistor (MOSFET) device designs that utilize stress to achieve performance gain in both n-type MOSFETs (NMOS) and p-type MOSFETs (PMOS). The physics behind NMOS gain is better understood than that of PMOS gain, which has received less attention. In this letter, we describe the warping phenomena which is responsible for the gain seen in [110] uniaxially stressed PMOS devices on [100] orientated wafers. We also demonstrate that shear uniaxial stress in PMOS is better suited to MOSFET applications than biaxial stress as it is able to maintain gain at high vertical and lateral fields. [ABSTRACT FROM AUTHOR]

Published
2004
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2. A 22nm high performance and low-power CMOS technology featuring fully-depleted tri-gate transistors, self-aligned contacts and high density MIM capacitors.

Author

Auth, C., Allen, C., Blattner, A., Bergstrom, D., Brazier, M., Bost, M., Buehler, M., Chikarmane, V., Ghani, T., Glassman, T., Grover, R., Han, W., Hanken, D., Hattendorf, M., Hentges, P., Heussner, R., Hicks, J., Ingerly, D., Jain, P., and Jaloviar, S.

Abstract

A 22nm generation logic technology is described incorporating fully-depleted tri-gate transistors for the first time. These transistors feature a 3rd-generation high-k + metal-gate technology and a 5th generation of channel strain techniques resulting in the highest drive currents yet reported for NMOS and PMOS. The use of tri-gate transistors provides steep subthreshold slopes (∼70mV/dec) and very low DIBL (∼50mV/V). Self-aligned contacts are implemented to eliminate restrictive contact to gate registration requirements. Interconnects feature 9 metal layers with ultra-low-k dielectrics throughout the interconnect stack. High density MIM capacitors using a hafnium based high-k dielectric are provided. The technology is in high volume manufacturing. [ABSTRACT FROM PUBLISHER]

Published
2012
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