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This study provides a thorough examination of the important intersection of Wireless Sensor Networks (WSNs) with machine learning (ML) for improving security. WSNs play critical roles in a wide range of applications, but their inherent constraints create unique security challenges. To address these problems, numerous ML algorithms have been used to improve WSN security, with a special emphasis on their advantages and disadvantages. Notable difficulties include localisation, coverage, anomaly detection, congestion control, and Quality of Service (QoS), emphasising the need for innovation. This study provides insights into the beneficial potential of ML in bolstering WSN security through a comprehensive review of existing experiments. This study emphasises the need to use ML’s potential while expertly resolving subtle nuances to preserve the integrity and dependability of WSNs in the increasingly interconnected environment.

An adaptive Nesterov quasi-Newton acceleration (an-QNA)-optimized low-noise amplifier (LNA) is proposed in this paper. An optimized single-ended-to-differential two-stage LNA circuit is presented. It includes an improved post-linearization (IPL) technique to enhance the linearity. Traditional methods like conventional quasi-Newton (c-QN) often suffer from slow convergence and the tendency to get trapped in local minima. However, the proposed an-QNA method significantly accelerates the convergence speed. Furthermore, in this paper, modifications have been made to the an-QNA algorithm using a quadratic estimation to guarantee global convergence. The optimized an-QNA-based LNA, using standard 65 nm CMOS technology, achieves a simulated gain of 17.5 dB, a noise figure (NF) of 3.7 dB, and a 1 dB input compression point (IP1dB) of −13.1 dBm. It is also noted that the optimized LNA achieves a measured gain of 12.9 dB and an NF of 4.98 dB, and the IP1dB is −17.8 dB. The optimized LNA has a chip area of 0.67 mm2.

A reformed particle swarm optimization (RPSO)-based up-conversion mixer circuit is proposed for radar application in this paper. In practice, a non-optimized up-conversion mixer suffers from high power consumption, poor linearity, and conversion gain. Therefore, the RPSO algorithm is proposed to optimize the up-conversion mixer. The novelty of the proposed RPSO algorithm is it helps to solve the problem of local optima and premature convergence in traditional particle swarm optimization (TPSO). Furthermore, in the RPSO, a velocity position-based convergence (VPC) and wavelet mutation (WM) strategy are used to enhance RPSO’s swarm diversity. Moreover, this work also features novel circuit configurations based on the two-fold transconductance path (TTP), a technique used to improve linearity. A differential common source (DCS) amplifier is included in the primary transconductance path (PTP) of the TTP. As for the subsidiary transconductance path (STP), the enhanced cross-quad transconductor (ECQT) is implemented within the TTP. A benchmark function verification is conducted to demonstrate the effectiveness of the RPSO algorithm. The proposed RPSO has also been compared with other optimization algorithms such as the genetic algorithm (GA) and the non-dominated sorting genetic algorithm II (NSGA-II). By using RPSO, the proposed optimized mixer achieves a conversion gain (CG) of 2.5 dB (measured). In this study, the proposed mixer achieves a 1 dB compression point (OP1dB) of 4.2 dBm with a high linearity. In the proposed mixer, the noise figure (NF) is approximately 3.1 dB. While the power dissipation of the optimized mixer is 3.24 mW. Additionally, the average time for RPSO to design an up-conversion mixer is 4.535 s. Simulation and measured results demonstrate the excellent performance of the RPSO optimized up-conversion mixer.

The proliferation of radar technology has given rise to a growing demand for advanced, high-performance transmitter front-ends operating in the 24 GHz frequency band. This paper presents a design analysis of a radio frequency (RF) transmitter (TX) front-end operated at a 24 GHz frequency and designed using 65 nm complementary metal-oxide-semiconductor (CMOS) technology for radar applications. The proposed TX front-end design includes the integration of an up-conversion mixer and power amplifier (PA). The up-conversion mixer is a Gilbert cell-based design that translates the 2.4 GHz intermediate frequency (IF) signal and 21.6 GHz local oscillator (LO) signal to the 24 GHz RF output signal. The mixer is designed with a novel technique that includes a duplex transconductance path (DTP) for enhancing the mixer’s linearity. The DTP of the mixer includes a primary transconductance path (PTP) and a secondary transconductance path (STP). The PTP incorporates a common source (CS) amplifier, while the STP incorporates an improved cross-quad transconductor (ICQT). The integrated PA in the TX front-end is a class AB tunable two-stage PA that can be tuned with the help of varactors as a synchronous mode to increase the PA bandwidth or stagger mode to obtain a high gain. The PA is tuned to 24 GHz as a synchronous mode PA for the TX front-end operation. The proposed TX front-end showed an excellent output power of 11.7 dBm and dissipated 7.5 mW from a 1.2 V supply. In addition, the TX front-end achieved a power-added efficiency (PAE) of 47% and 1 dB compression point (OP1dB) of 10.5 dBm. In this case, the output power is 10.5 dBm higher than the linear portion of the response. The methodologies presented herein have the potential to advance the state of the art in 24 GHz radar technology, fostering innovations in fields such as autonomous vehicles, industrial automation, and remote sensing.