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This article explores a single-source UXE-type asymmetrical multilevel inverter for its operation on 13-, 11-, and 9-levels with boosted output voltage. The 13- and 11-level operations require a single voltage sensor to maintain the auxiliary dc link at $V_{\text{dc}}/2$ and produce 1.5 and 1.25 boosting using redundant states and exhibit lower capacitor inrush currents. For the 9-level operation, the topology exhibits self-balancing of the dc-link at $V_{\text{dc}}$ and a boosting of 2. With a conventional pulsewidth modulation (PWM) for the 13-level operation, the inverter can drive a predominantly inductive load of 0.35 lagging at unity modulation index. For the 11-level operation, the levels cease to maintain beyond the modulation of 0.95. Thus, a hybrid PWM is proposed to fully utilize the redundant states for the charging of the switched-capacitors and enhance the inverter active load capability in the 13-level mode by 21% at unity modulation index ($m_a$) and address a 0.8 power factor load at the $m_a$ of 0.9. For the 11-level operation, the levels are maintained at any $m_a$ with the hybrid PWM. The operation of the inverter is also verified for nonlinear load. Further, the 9-level operation with twice boosting and self-balancing is presented. The results are verified on MATLAB/Simulink and validated experimentally. [ABSTRACT FROM AUTHOR]

In this paper, a twelve-band hysteresis control is applied to a recent thirteen-level asymmetrical inverter topology by employing a robust proportional-integral (PI) controller whose parameters are decided online by genetic algorithm (GA). The asymmetrical inverter topology can generate thirteen levels of output voltage incorporating only ten switches and exhibits boosting capability. A 12-band hysteresis current control strategy is applied to ensure the satisfactory operation of the inverter. It is designed to provide a sinusoidal line current at the unity power factor. The tuning of the PI controller is achieved by a nature inspired GA. Comparative analysis of the results obtained after application of the GA and the conventional Ziegler–Nichols method is also performed. The efficacy of the proposed control on WE topology is substantiated in the MATLAB Simulink environment and was further validated through experimental/real-time implementation using DSC TMS320F28379D and Typhoon HIL real-time emulator (Typhoon-HIL-402). [ABSTRACT FROM AUTHOR]

As the applications of power electronic converters increase across multiple domains, so do the associated challenges. With multilevel inverters (MLIs) being one of the key technologies used in renewable systems and electrification, their reliability and fault ride-through capabilities are highly desirable. While using a large number of semiconductor components that are the leading cause of failures in power electronics systems, fault tolerance against switch open-circuit faults is necessary, especially in remote applications with substantial maintenance penalties or safety-critical operation. In this paper, a fault-tolerant asymmetric reduced device count multilevel inverter topology producing an 11-level output under healthy conditions and capable of operating after open-circuit fault in any switch is presented. Nearest-level control (NLC) based Pulse width modulation is implemented and is updated post-fault to continue operation at an acceptable power quality. Reliability analysis of the structure is carried out to assess the benefits of fault tolerance. The topology is compared with various fault-tolerant topologies discussed in the recent literature. Moreover, an artificial intelligence (AI)-based fault detection method is proposed as a machine learning classification problem using decision trees. The fault detection method is successful in detecting fault location with low computational requirements and desirable accuracy. [ABSTRACT FROM AUTHOR]