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In this brief, a negative bias stress (NBS) induced degradation in n-type multigate polycrystalline silicon (poly-Si) thin-film transistor (TFT) is investigated. It is observed that after NBS the transfer characteristic curves shift to the negative gate bias direction and multigate TFTs degrade more than the single-gate TFTs with the same effective channel length. The observed degradation phenomenon is explained with short channel effect that is resulted from the diffusion and distribution of hole carriers in the channel, which are generated in the source/drain depletion region and swept into the channel when the junctions are reversely biased during NBS. Pronounced NBS degradation caused by increased hole carriers in the channel is also verified in NBS experiment with light illumination. [ABSTRACT FROM PUBLISHER]

We have succeeded in developing a hybrid-type temperature sensor using poly-Si thin-film transistors (TFTs) that outputs rectangle waveforms. An advantage of the conventional hybrid-type sensor is that large temperature dependences of off-leakage currents can be utilized, and it simultaneously works in a digital operation tolerant of noises. Additionally, in this paper, by connecting two conventional ones, the sensor becomes able to output rectangle waveforms, which can be easily counted. We confirm the waveform and that the sensor can detect the correct temperature. We think that it is promising to integrate this temperature sensor in some applications using TFTs. [ABSTRACT FROM PUBLISHER]

We developed partial laser anneal silicon (PLAS) thin-film transistor (TFT) of novel low-temperature polycrystalline-silicon (LTPS) technology, which had the mobility of 28.1 cm2/Vs lager than that of mass produced oxide TFT and photo-stability comparable with that of LTPS TFT in bottom gate structure. This innovative technology enables the conversion from an α-Si TFT to a high-mobility TFT most easily and inexpensively. Moreover, there is no limit of substrate size, such as Gen10 and more. Photo-stability of PLAS will be suitable to organic light-emitting diode backplane, high-dynamic range TV, and outdoor IDP. [ABSTRACT FROM AUTHOR]

We report high performance p-type poly-Si thin-film transistors (TFTs) achieved by lateral grain growth of amorphous silicon (a-Si) by using a continuous-wave blue diode laser of wavelength 445 nm. The blue laser beam is efficiently absorbed into the a-Si film, such that full melting and lateral crystallization is achieved in all thicknesses investigated, 50–200 nm. TFTs fabricated with 75-, 100-, and 125-nm-thick poly-Si films laterally grown by the blue laser annealing exhibited field-effect mobility of 108 ± 7, 104 ± 9, and 134 ± 12 cm2/ \textrm V\cdot \textrm s , and subthreshold swing of 210±51, 191±16, and 193±53 mV/decade, respectively, and high ON/OFF current ratio of \sim 10^8 . [ABSTRACT FROM PUBLISHER]

Two-stage degradation of p-type polycrystalline silicon thin-film transistors under dynamic positive bias temperature (PBT) stress is reported for the first time. ON-state current ( \(I_\mathrm{{\scriptstyle ON}}\) ) gradually increases in the first degradation stage while dramatically drops in the second degradation stage, which are, respectively, due to the channel length shortening effect, caused by electrons trapping into the gate oxide, and grain boundary potential barrier buildup, caused by dynamic hot-carrier-induced traps generation. The transition from the first to the second degradation stage is clarified, in which the pulse peak duration plays a key role. Longer pulse peak duration is preferred to suppress the dynamic PBT stress-induced degradation. [ABSTRACT FROM AUTHOR]

A lateral polysilicon Bipolar Charge Plasma Transistor (poly-Si BCPT) on undoped recrystallized polycrystalline silicon which is compatible with the thin-film field effect transistor (TFT) fabrication is reported in this paper. Using calibrated two-dimensional device simulation, the electrical performance of the poly-Si BCPT is evaluated in detail by considering the position of the single grain boundary. Our simulation results demonstrate that the poly-Si BCPT has the potential to realize low-cost thin-film polycrystalline silicon bipolar transistors with large current gain and cut-off frequency making it suitable for a number of applications including the driver circuits of the displays. [ABSTRACT FROM PUBLISHER]

Abstract: The Ni-metal-induced crystallization (MIC) of amorphous Si (α-Si) has been employed to fabricate low-temperature polycrystalline silicon (poly-Si) thin-film transistors (TFTs). Most studies have focused only on reducing Ni contamination because Ni residues cause high leakage current in MIC–TFTs. Also of concern is the source/drain (S/D) series resistance, which degrades the device performance (driving ability) that might vary with the Ni concentration in MIC–TFTs. Improving the driving ability of MIC–TFTs requires a detailed understanding of how Ni residues affect S/D series resistance. This study investigates how Ni concentration affects S/D series resistance by using the transmission line method. The results of this study provide further insight into how Ni concentration and resistance are related. The results show that the S/D series resistance and channel resistance decreased with a reduction in Ni concentration in MIC poly-Si because of better crystalline quality and lower degradation of the donor concentration. This phenomenon was caused by the Ni concentration forming less NiSi2 nucleation sites to generate a large grain size; Ni atoms serve as acceptor-like dopants in silicon, which counteract with the effects of n-type doping, subsequently reducing the donor concentration in the S/D region. [Copyright &y& Elsevier]

A physical-based analytical series resistance (Rs) model is first proposed to accurately evaluate the Rs of polycrystalline silicon thin-film transistors (TFTs). Through carefully analyzing the gate-to-source/drain overlap regions, three underlying physical effects wherein are adequately included, namely the gate (Vg)-induced carrier accumulation, current path spreading, and carrier transport via thermionic emission over grain boundaries. The proposed model can precisely reproduce the Vg dependent Rs behavior and fit the experimental data of both metal-induced lateral crystallized and excimer laser annealed TFTs. Furthermore, an explicit analytical expression of Rs is derived using appropriate approximation, based on which all underlying Rs components and their dependencies on device parameters can be clarified. Finally, feasible approaches of Rs reduction are suggested. [ABSTRACT FROM AUTHOR]

We propose a thermal sensor using poly-Si thin-film transistors (TFTs) with self-aligned and offset gate structures. First, the temperature dependences of the transistor characteristic are compared between the self-aligned and offset TFTs. It is found that both the TFTs have the temperature dependence of the off-leakage current, whereas the off-leakage current of the self-aligned TFT is larger than that of the offset TFT. Next, the self-aligned and offset TFTs are included in a cell circuit to detect the temperature utilizing the off-leakage current, which is composed of a pair of 1-transistor and 1-capacitor. It is found that low and high temperatures can be detected using the self-aligned and offset TFTs, respectively. We think that it is promising to integrate this thermal sensor in certain applications using TFTs. [ABSTRACT FROM PUBLISHER]

N-type junctionless (JL) planar poly-Si thin-film transistors (TFTs), which contain an in situ heavily phosphorous-doped channel with thickness ranging from 8 to 12 nm, were fabricated and characterized. The devices exhibit superior current drive and good control over performance variability. From C– V characterization, the ionized dopant concentration in the channel is determined to be around \2 \times \10^19 \ \cm^-3 and the fixed charge density to be around -6 \times \10^12 \ \cm^-2. The negative fixed charge density is probably related to the segregation of phosphorous species at the oxide/channel interface. We also observed a reverse short-channel effect from the relationship between the threshold voltage and the channel length. One mechanism considering enhanced phosphorous segregation is proposed to explain this finding. [ABSTRACT FROM AUTHOR]

Abstract: We propose a thermal sensor employing a ring oscillator composed of poly-Si thin-film transistors (TFTs). First, temperature dependences of transistor characteristics are compared between n-type TFTs with self-aligned and offset gate structures. It is confirmed that the temperature dependence of the offset TFT is larger. Next, a ring oscillator is composed using the n-type offset TFTs. It is clarified that the temperature can be detected by measuring the oscillation frequency. We think that this kind of thermal sensor is available as a digital device. [Copyright &y& Elsevier]

Abstract: In this paper, we present a comprehensive study on the effects of layout design and re-crystallization temperature on the material and electrical characteristics of polycrystalline silicon thin-film transistors (poly-Si TFTs) with metal-induced lateral crystallized (MILC) nanowire (NW) channels. It is found that the off-state leakage current shows strong dependence on the arrangement of MILC seeding windows, while the number of smaller solid-phase-crystallized (SPC) grains in the channel is reduced by lowering the re-crystallization temperature, thus improving the on-state behavior. Moreover, owing to the spatial confinement for MILC fronts, small cross-section of the NW channel would result in little lateral crystallization, and thus retarding the enhancement in performance of MILC NW devices. [Copyright &y& Elsevier]

Abstract: We have compared transistor characteristics between excimer-laser crystallized (ELC) and solid-phase crystallized (SPC) poly-Si thin-film transistors (TFTs). First, off characteristic and characteristic parameters, such as the subthreshold swing and field-effect mobility, of the ELC TFT are superior to those of the SPC TFT, which indicates that the trap states in the ELC TFT are fewer than those in the SPC TFT. Next, the activation energy (Ea) for the on characteristic of the ELC TFT is larger than that of the SPC TFT, which originates from the difference of the grain structures. Moreover, Ea for the off characteristic of the ELC TFT is much larger than that of the SPC TFT, which is caused by the difference of the trap distribution. [Copyright &y& Elsevier]

We have analyzed the device behavior of a poly-Si thin-film transistor (TFT) with a lightly doped drain (LDD) structure using 2-D device simulation. It is found that the reason that the on current does not fall very much is that the electron channel oozes from the channel region to the LDD region and the electric current paths spread to the entire LDD region. On the other hand, the reason that the off current is effectively reduced is undoubtedly that the electric field at the interface between the channel and LDD regions is weakened. However, it should be noted that the depletion region is formed at the drain edge owing to the “pseudo” space-charge region in the channel region, where the carrier density is much lower than in the other channel region, although the net space-charge does not exist. [ABSTRACT FROM AUTHOR]

The characteristic degradation of p-type poly-Si thin-film transistors is analyzed using a device simulation. An experiment indicates that the drain current increases under the hot-carrier stress as the stress drain bias increases. The device simulation clarifies that this degradation phenomenon can be reproduced by the electron traps at the insulator interface at least in 1 \mu\m from the drain edge, but the electric field is high only in several hundred nanometers in the conventional trap model. This contradiction is dispelled by considering that the pseudo drain edge advances toward the channel region owing to the electron traps, allowing for a high electric field even far from the drain edge in the pseudo drain edge advance model. [ABSTRACT FROM PUBLISHER]

Positive-bias temperature-stress-induced degradation in p-channel poly-Si thin-film transistors is investigated. Two-stage degradation behavior is observed. In the first-stage degradation, on-state current (ION) initially increases associated with a positive threshold voltage (V \rm th) shift and is then followed by a gradual ION decrease. In the second stage, Vth shifts to the negative, and ION significantly degrades. A comprehensive physical model is proposed to clarify the two-stage degradation behavior. The first-stage degradation is attributed to electron trapping and detrapping, whereas the second-stage degradation is dominated by positive charge generation. [ABSTRACT FROM AUTHOR]

Abstract: Ni-metal-induced crystallization (MIC) of amorphous Si (α-Si) has been used to fabricate low-temperature polycrystalline silicon (poly-Si) thin-film transistors (TFTs). However, the leakage current of MIC-TFT is high. In this study, a chemical oxide layer was used to avoid excess of Ni atoms into α-Si layer during MIC process, which was simple and without extra expensive instrument. The minimum leakage current and on/off current ratio were significantly improved. [Copyright &y& Elsevier]

Abstract: Trap densities (D t) in entire bandgaps of poly-Si thin-film transistors (TFTs) fabricated by solid-phase crystallization (SPC) have been extracted by measuring low-frequency capacitance–voltage characteristics and using an extraction algorithm. The extraction algorithm is explained in detail. D t in the upper and lower halves of the bandgap is extracted from n- and p-type TFTs, respectively. It is found that D t is very roughly 1018 cm−3 eV−1 near the midgap and becomes tail states near the conduction and valence bands. As a result, D t is distributed like U shape in the bandgap, but humps appear around the midgap. Moreover, the dependence of D t on process conditions of post annealing has been evaluated. It is found that the hump can be reduced by increasing annealing temperature and time because crystal defects generated during the SPC are extinguished during the post annealing. [Copyright &y& Elsevier]

In this paper, we have proposed a simple and novel way to fabricate poly-Si nanowire (NW)-silicon-oxide-nitride-oxide-silicon (SONOS) devices with various gate configurations. Three types of devices having various gate configurations, such as side gated, \Omega -shaped gated \OmegaG, and gate-all-around (GAA), were successfully fabricated and characterized. The experimental results show that, owing to the superior gate controllability over NW channels, much improved transfer characteristics are achieved with the GAA devices, as compared with the other types of devices. Moreover, GAA devices also exhibit the best memory characteristics among all splits, including the fastest programming/erasing efficiency, largest memory window, and best endurance/retention characteristics, highlighting the potential of such scheme for future SONOS applications. [ABSTRACT FROM PUBLISHER]

We have developed a technique to completely extract trap densities at front- and back-insulator interfaces and grain boundaries in poly-Si thin-film transistors. First, the trap densities at the front- and back-insulator interfaces are extracted from the front and back low-frequency capacitance–voltage characteristics using the Poisson and carrier-density equations. Next, the trap density at the grain boundaries is extracted from a current–voltage characteristic using 2-D device simulation. Particularly, in this paper, actual trap densities are extracted to evaluate oxygen and hydrogen plasma treatments. First, it is found that the energy profiles of these trap densities are quite different. Next, the oxygen plasma treatment has the effect to reduce trap densities but cannot diffuse to the back-insulator interface. Finally, it is concluded that this extraction technique is useful to evaluate film properties, diagnose fabrication processes, and improve transistor characteristics. [ABSTRACT FROM PUBLISHER]

Abstract: Trap densities in poly-Si thin-film transistors fabricated by solid-phase crystallization have been extracted by measuring low-frequency capacitance–voltage characteristics and using a novel extraction algorithm. Moreover, the dependence of the trap densities on temperature and time of post annealing has been evaluated. It is found that the trap densities are flatly distributed and very roughly 1018 cm−3 eV−1 near the midgap and become tail states near the conduction band. Furthermore, the trap densities can be reduced by increasing the temperature and time of the post annealing. This is brought by the extinction of crystal defects generated during the solid-phase crystallization. [ABSTRACT FROM AUTHOR]

In this paper, we characterize and compare the characteristics of a poly-Si nanowire (NW) device with independent double-gated configuration under different operation modes. In the device, the tiny NW channels are surrounded by an inverted-T-shaped gate and a top gate. It is found that the device under double-gate (DG) mode exhibits significantly better performance with respect to the two single-gate (SG) modes, as indicated by a higher current drive than the combined sum of the two SG modes and a smaller subthreshold swing of less than 100 mV/dec. Origins of such improvement have been identified to be due to the elimination of the back-gate effect as well as an enhancement in the effective mobility with the DG operation. [ABSTRACT FROM AUTHOR]

Abstract: In this work, the degradation mechanism of N-channel poly-silicon thin-film transistor (poly-Si TFT) has been investigated under dynamic voltage stress at room temperature. The ON-current of TFT is degraded to as low as 0.3 times of the initial value after 1000s stress. On the other hand, both the sub-threshold swing and threshold voltage kept well during the AC stress. The current crowding effect was rapidly increased with increasing of stress duration. However, comparing the initial and degraded characteristics at rising temperature, namely, 150°C, the ON-current of TFT only decrease to 75% of the initial value after 1000s AC stress. It depicts that creation of effective trap density in tail-states of poly-Si film is responsible for the electrical degradation of poly-Si TFT. At high temperature, electron has enough energy to pass the energy barrier created by ac stress and the degradation is less obvious. [Copyright &y& Elsevier]

Abstract: The novel process of self-aligned fluorine doped oxide (SiOF) spacers on low temperature poly-Si (LTPS) lightly doped drain (LDD) thin film transistors (TFTs) is proposed. A fluorine doped oxide spacers were provided to generate the lower dissociation Si–F bonds adjusted to the interface of the drain which is the largest lateral electric field region for lightly doped drain structure. The stronger Si–F bonds can reduce the bonds broken by impact ionization. It is found that the output characteristics of SiOF spacers TFTs show the superior immunity to kink effect. The degradations in Vth shifting, subthreshold slope, drain current and transconductance of SiOF spacers after DC stress are improved. [Copyright &y& Elsevier]

Positive bias temperature instability in p-channel polycrystalline silicon thin-film transistors is investigated. The stress-induced hump in the subthreshold region is observed and is attributed to the edge transistor along the channel width direction. The electric field at the corner is higher than that at the channel due to thinner gate insulator and larger electric flux density at the corner. The current of edge transistor is independent of the channel width. The electron trapping in the gate insulator via the Fowler-Nordheim tunneling yields the positive voltage shift. As compared to the channel transistor, more trapped electrons at the edge lead to more positive voltage shift and create the hump. The hump is less significant at high temperature due to the thermal excitation of trapped elections via the Frenkel-Poole emission. [ABSTRACT FROM AUTHOR]

Several types of poly-Si nanowire (NW) thin-film transistors (TFTs) with multiple-gated (MG) configuration were demonstrated and characterized. These devices were fabricated with simple methods without resorting to costly lithographic tools and processes. The fabricated trigated devices show a low subthreshold swing (SS) of around 100 mV/dec and on/off current ratio higher than 108. These results clearly indicate the effectiveness of MG scheme in enhancing the device performance. Furthermore, a multiple-channel scheme was demonstrated to further increase the drive current without compromising device performance. Finally, the impact of MG on the variation of NWTFT characteristics is investigated with a clever method that allows the fabrication of test structures with identical NW channel hut different gate configurations. [he results clearly show that the variation could be reduced by increasing the portion of NW channel surface that is modulated by the gate. [ABSTRACT FROM AUTHOR]

Abstract: In this work, it is demonstrated the application of a high k dielectric, as hafnium oxide (HfO2), in poly-Si thin film transistors (TFTs) obtained by metal induced lateral crystallization (MILC). The dielectric layer was deposited at room temperature by sputtering, using argon and oxygen as process gases. As produced TFTs exhibit field effect mobility around 45cm2 V−1 s−1and I on/I off ratio of about 2×105. After annealing in a forming gas atmosphere for about 1h at 200°C, the threshold voltage and the sub-threshold slope are reduced, respectively from 4.8 to 2V and from 1.6 to 1.4V/dec. Nevertheless, by doing so, we notice a reduction on the field effect mobility of about 45% and a decrease of about 2.5 times on the I on/I off ratio. Longer annealing time will not improve the TFT’s performance. [Copyright &y& Elsevier]

Abstract: In this work, we study a polycrystalline silicon thin-film transistor (poly-Si TFT) combined with a silicon–oxide–nitride–oxide–silicon (SONOS) stack gate dielectric and nanowire channels structure for the applications of transistor and nonvolatile memory. The proposed device named with NW SONOS-TFT has superior electrical characteristics of transistor and also can exhibit high program/erase (P/E) efficiency under adequate bias operation. The V th decreases from 2.45 V to 1.76 V and subthreshold swing reduces from 0.57 V/decade to 0.42 V/decade. The programming V th shift is improved from 2.2 V to 3.3 V at 14 V for 1 s and the erasing V th shift is improved from −0.3 V to −1.3 V at −14 V for 1 s. The dramatic improvement can be attributed to the tri-gate structure and corner effect. In addition, the memory device has a promising data retention behavior at 85 °C and a 0.8 V memory window after 5×103 P/E cycles operations. Hence, the NW SONOS-TFT is suitable for application in the future system-on-panel display. [Copyright &y& Elsevier]

By using an aqueous solution of Ni(NO3)2/NH4OH for formation of Ni media on a-Si, disk-like super-large domain metal-induced radially crystallized (S-MIRC) poly-Si was prepared. The process requires no buffer layer deposition on a-Si. The prepared S-MIRC poly-Si has an average domain size of up to 60 lm, highest hole Hall mobility of 27.1 cm² V-1 s-1, and highest electron Hall mobility of 45.6 cm² V-1 s-1. Poly-Si TFT made on super-large-domain S-MIRC poly-Si had high mobility of ~105.8 cm² V-1 s-1, steep sub-threshold slope of ~1.0 V decade-1, high on/off state current ratio of >107 and low threshold voltage of ~ -6.9 V. A simultaneous Ni-collected and induced crystallization model is proposed to explain the growth kinetics of S-MIRC poly-Si. [ABSTRACT FROM AUTHOR]

Abstract: Laser recrystallized low temperature poly-silicon films have attracted attention for their applications in thin-film transistors (TFTs), which are widely used in active matrix displays. The electrical characteristics of the poly-silicon film may vary because of its grain boundaries. In this work, the variation is statistically studied with respect to the threshold voltage and mobility of the TFTs. The threshold voltage and mobility of many closely-located TFTs are measured. These two parameters correspond to the deep states and tail states of the poly-silicon film, respectively. The mutual difference of two threshold voltages exhibits the distribution in a Gaussian–Lorentzian cross product form. On the other hand, the mutual difference of two mobility exhibits the distribution of Lorentzian function. This result directly reflects the local fluctuations and the spatial trends of the deep and tail states in a poly-silicon film. [Copyright &y& Elsevier]

Abstract: The drain current activation energy dependence on the gate voltage is first evaluated from temperature measurements in both low temperature (⩽600°C) polysilicon thin film transistors and in crystalline silicon N-MOSFETs, operating from sub-threshold to above-threshold regions. The noise behaviour of these transistors is then described with a low frequency noise model based on the Meyer–Neldel drain current expression. This model is built on carrier fluctuations at the gate oxide/active layer interface and the corresponding defect density is then deduced. It suggests that these defects close to the interface, causing detrapping/trapping processes of carriers and fluctuations of the flat-band voltage, are mainly responsible for the low frequency noise in the two operating modes. Noise measurements on different N-MOS transistors are confronted to result from the presented model. [Copyright &y& Elsevier]

Polycrystalline silicon thin film transistors (poly-Si TFTs) are used in a wide variety of applications, and will figure prominently in future high-resolution, high-performance flat panel display technology. However, it is very difficult to fabricate high performance poly-Si TFTs at temperatures lower than 300 °C and the substrate temperature of the process is limited to less than 600 °C on glass. This paper describes a high temperature process above 750 °C to obtain poly-Si films. Hydrogenated amorphous silicon (a-Si:H) layer was deposited on a flexible Mo metal substrate and crystallized by rapid thermal annealing for TFT application. The a-Si:H films were crystallized at various temperatures between 750 and 1050 °C. As annealing temperature was increased, the TFT exhibited increased transconductance (gm) and reduced voltage between drain and source (Vds), the threshold voltage (VT). The high temperature annealed poly-Si film illustrated field effect mobility higher than 67 cm2/Vs. We also investigated the types and activation energies of grain boundary trap, which are the function of annealing temperature. The poly-Si TFT showed an improved Ion/Ioff ratio of 106, reduced gate threshold voltage, and an increased field effect mobility by three orders. [Copyright &y& Elsevier]

A simple analytical model for the current–voltage characteristics of a poly-Si thin-film transistor (TFT) using charge sheet analysis has been developed. An effective doping due to the presence of trap levels at grain boundaries and the effect of diffusion current is considered. The model also takes into account the charge sharing factor, necessary to explain the characteristics of a short channel device. The results so obtained for both long- and short-channel lengths were compared with the experimental data and good agreement was found. The transconductance and the drain conductance were also evaluated. [Copyright &y& Elsevier]

Low-temperature polycrystalline Si (LTPS) has been widely used to achieve large-area and high-speed TFT devices. In this regard, the enhancement in the mobility and stability of LTPS TFTs was investigated with the insertion of amorphous silicon (a-Si:H) capping layers at the insulator/poly-Si junction. Prior to capping layer deposition, the polycrystalline Si active region was plasma pre-treated under N 2 O or NH 3 /N 2 O ambience to refine the device characteristics. A high field effect mobility (μ FE) of 90 cm2/Vs with a subthreshold swing (SS) of 1.21 V/dec was obtained from N 2 O treated non-capped LTPS TFT. The inclusion of a-Si:H(n)/a-Si:H(i) stacked capping layer at the gate insulator/poly-Si junction enhanced μ FE to 152 cm2/Vs and decreased the SS to 0.69 V/dec. In contrast, the single capping layer of a-Si:H(i) and a-Si:H(n) showed feeble μ FE improvements. The mechanism behind the μ FE increase for the a-Si:H(n)/a-Si:H(i) stacked capping layer was explained using the atlas TCAD simulator. The grain boundary trap (N trap) density also decreased drastically with the insertion of the capping layer. A low and stable N trap value of 3.8 × 1011 cm−3 was obtained for a-Si:H(n)/a-Si:H(i) stacked capping layer with N 2 O pre-treatment, which may play a major role in enhancing the mobility and can be implemented for next-generation LTPS TFTs. [Display omitted] • Plasma treatment and capping layer techniques are discussed. • Reduction in the grain boundary trap density due to the techniques. • High mobility of 152 cm2/V.s for LTPS TFT device. [ABSTRACT FROM AUTHOR]

A single grain boundary tunnel field effect transistor (TFET) on recrystallized polycrystalline silicon is reported in this letter. By varying the position of the grain boundary (GB) in the channel, the performance of the proposed device is evaluated using calibrated 2-D simulations. Our results show the possibility of realizing low-cost thin-film recrystallized polycrystalline tunnel FETs with low OFF-state current and low subthreshold swing compared with the thin-film transistors. By introducing the source N+ pocket doping, it is also shown that the proposed single GB PNPN TFET exhibits enhanced ON-state current, making it suitable for low power display applications, including the driver circuits. [ABSTRACT FROM AUTHOR]

Highlights: [•] We propose employing a p/i/n-type poly-Si TFT for quasi-static C–V measurement. [•] The electric current smoothly flows through either the n-type or p-type region. [•] Relatively high f can be used to get a quasi-static C–V characteristic for any voltage conditions. [•] This improves the S/N ratio. [•] The C–V characteristics are available for various analyses such as extraction of trap densities. [Copyright &y& Elsevier]

We have evaluated the effects of thermal annealing before formation of gate insulator films (preannealing) and thermal annealing after formation of gate insulator films (postannealing) by extracting trap densities for solid-phase crystallized poly-Si thin-film transistors. It is suggested that the preannealing densifies the poly-Si films and induces additional internal stress after the thermal oxidation of the gate insulator films. On the other hand, the postannealing also relieves the internal stress. These conflicting effects indicate that the order of the thermal annealing is very important to improve device performance. [ABSTRACT FROM AUTHOR]

In this letter, for the first time, we experimentally investigate the radio-frequency (RF) characteristics and low-frequency noise (LFN) of n-type planar junctionless (JL) poly-Si thin-film transistors (TFTs). The fabricated JL devices show remarkable dc performance with good current drive and a high on-current/off-current ratio of \8 \times \10^7. Furthermore, with the implementation of an in situ phosphorus-doped channel architecture and a salicide process, the JL device with a channel length of 0.4 \mu\m exhibits a cutoff frequency (ft) of 3.36 GHz and a maximum oscillation frequency (f\max) around 7.37 GHz at a drain bias of 2 V. As far as LFN is concerned, the JL device shows approximately four orders of magnitude lower drain-current noise power spectral density (Sid) over conventional inversion-mode counterparts. These results demonstrate that the JL poly-Si TFT technique is promising for RF modules implemented in system-on-panel applications. [ABSTRACT FROM PUBLISHER]

We have compared the temperature dependences of the current–voltage characteristics between single drain (SD) and lightly doped drain (LDD) poly-Si thin-film transistors (TFTs). It is found that the temperature dependence of the off-leakage current for the LDD TFT is larger because the electric field at the drain junction is weaker. Moreover, the change of the temperature dependence from low drain voltage (V \rm ds) to high Vds for the LDD TFT is smaller because the main mechanism of the off-leakage current is always phonon-assisted tunneling (PAT), whereas that for the SD TFT shifts from PAT to band-to-band tunneling. [ABSTRACT FROM PUBLISHER]

In this letter, we fabricated and characterized thin-film transistors with a suspended poly-Si nanowire (NW) channel and gate nitride with embedded silicon nanocrystals (Si NCs). The embedded Si NCs increase the surface roughness, thus reducing the adhesive force as the nitride is in contact with the poly-Si NW channel during the operation. Such a feature results in a reduction in pull-in voltage and sharper pull-out behavior. Moreover, this approach also greatly improves the endurance characteristics of the devices. [ABSTRACT FROM AUTHOR]

In this letter, we study the characteristics of n-type junctionless (JL) poly-Si thin-film transistors (TFTs) with an ultrathin and heavily phosphorous doped channel. The fabricated devices show excellent performance with a subthreshold swing of 240 mV/dec and an on/off current ratio of > \10^7. Moreover, the JL device shows 23 times increase in the on-state current at a gate overdrive of 4 V as compared with the conventional control device with an undoped channel. The significant improvement in the current drive is ascribed to the inherently high carrier concentration contained in the channel of the JL device. These results evidence the great potential of the JL poly-Si TFTs for the manufacturing of future 3-D and flat-panel electronic products. [ABSTRACT FROM PUBLISHER]

High-performance poly-Si-TFT-based TiN–alumina–nitride–vacuum–silicon (TANVAS) trapping-charge memory has been demonstrated utilizing high-k blocking oxide and vacuum tunneling layer for the first time. In particular, the vacuum, lowest k in nature, was introduced to replace the traditional tunneling oxide. Furthermore, the alumina high-k blocking oxide was applied to upgrade the electric field across the tunneling layer. Based on the enlarged k-value difference between the blocking and tunneling layers, the TANVAS featured considerable field enhancement across the tunneling layer, thus much improving the program/erase efficiencies. In addition, owing to the suppression of defect creation in the tunneling layer, the TANVAS also exhibited superior retention characteristics. These excellent memory characteristics of TANVAS are therefore promising for the 3-D Flash and system-on-panel applications. [ABSTRACT FROM AUTHOR]

We have analyzed the mechanism of off-leakage current in an lightly doped drain (LDD) poly-Si thin-film transistor by investigating the activation energy Ea. It is found that Ea decreases as the gate and drain voltages increase. We have also discussed the mechanism using a device simulator. It is found that a hole channel is lightly formed in the LDD region, and a pseudo p-n junction appears at the junction between the LDD and drain regions. The aforementioned experimental behavior of Ea is because the electric field increases there. These results suggest that the off-leakage current is caused by the phonon-assisted tunneling with Poole–Frenkel effect at the junction between the LDD and drain regions. [ABSTRACT FROM AUTHOR]

In the charge pumping (CP) measurement of poly-Si thin-film transistors (TFTs), the Elliot curve is found to be irrelevant to the flat-band voltage (Vfb) and threshold voltage (Vth) and hence does not follow the traditional MOSFET CP rule. Instead, a new correspondence between the TFT Elliot curve and device key parameters is observed. The critical onset voltages of the CP current are the threshold gate voltages for channel inversion and accumulation, which can be experimentally extracted by capacitance–voltage measurement. They are consistent with the general CP model and reduce to Vfb and Vth in MOSFETs. [ABSTRACT FROM AUTHOR]

Abstract: The dependence of off-leakage current on channel film quality in poly-Si thin-film transistors has been analyzed using two-dimensional device simulation. It is found that the off-leakage current decreases as the intragrain trap density decreases for the low V gs. This is because the Phonon-assisted tunneling with Poole–Frenkel effect is the dominant mechanism of the carrier generation and the generation rate of carrier pair decreases as the intragrain trap density decreases. On the other hand, the off-leakage current slightly increases as the intragrain trap density decreases for the high V gs. This is because the band-to-band tunneling is the dominant mechanism and the influence of the intragrain trap density to the carrier conductance is larger than that to the generation rate. [Copyright &y& Elsevier]

We propose a thermal sensor using a poly-Si thin-film transistor (TFT) with widened detectable temperature range. The cell circuit is composed of one transistor and one capacitor. The cell capacitor is charged during initializing periods and discharged during holding periods, and the dropped voltages are measured during detecting periods. The temperature is detected because the discharge current is subject to the temperature dependence of the transistor characteristic. The detectable temperature is expanded to -\10\ ^\circ\C–\140\ ^\circ\C by adding multiple holding periods. We think that it is promising to integrate this thermal sensor in some applications using TFTs. [ABSTRACT FROM PUBLISHER]

We have conducted chronoamperometry using an integrated potentiostat consisting of poly-Si thin-film transistors. An electrochemical measurement of enzymatic redox reaction using glucose oxidase and ferrocene mediator is attempted as a practical example. It is found that the chronoamperogram depends on the glucose concentration, and a glucose concentration as low as 2 mM can be detected by comparing the chronoamperogram without glucose. The glucose sensitivity of the chronoamperometry is similar to that of the cyclic voltammetry and sufficient for diabetic diagnosis. [ABSTRACT FROM AUTHOR]

A capacitorless single-transistor (1T) memory cell with a long data-retention time is demonstrated on polycrystalline silicon thin-film transistors (TFTs). A new operation mode using channel traps is employed to modulate the drain current in the accumulation region. The different drain current can be read by modulating the barrier height at the grain boundary. The extrapolated retention time at the half of the current window is \sim\!\!\10^7\ \s. There is no degradation after 2000 write/erase cycles by trap-assisted tunneling programming. The low-temperature process of the TFT cells is attractive for the 3-D integration. [ABSTRACT FROM PUBLISHER]

High-performance poly-Si thin-film transistors (TFTs) using an ultrathin high-κ metal gate stack with a subthreshold swing (SS) of 193 mV/dec when operating at room temperature and maximum thermal budget of 700 °C are readily compatible with monolithic 3-D integrated circuits (3D-ICs) and silicon-on-glass (SOG) applications. The SS is reduced to 31 mV/dec, and the on/off current ratio is increased to 108 at 77 K; the result is a significant reduction of leakage current and lower power consumption. Long-channel TFTs have a higher drain current noise spectral density SID and a smaller exponential frequency factor (γ) due to the influence of numerous grain boundaries on carrier transport, as confirmed by gap state density extraction. These devices may pave the way for high-performance circuit designs and applications, such as monolithic 3D-ICs, SOG, and active-matrix organic LED. [ABSTRACT FROM AUTHOR]

The novel gate-all-around (GAA) poly-Si thin-film transistors (TFTs) with multiple nanowire channels (MNCs) have been, for the first time, fabricated using a simple process to demonstrate high-performance electrical characteristics and high immunity to short-channel effects (SCEs). The nanowire channel with high body-thickness-to-width ratio (TFin/WFinl), which is approximately equal to one, was realized only with a sidewall-spacer formation. Moreover, the unique suspending MNCs were also achieved to build the GAA structure. The resultant GAA-MNC TFTs showed outstanding three-dimensional (3-D) gate controllability and excellent electrical characteristics, which revealed a high on/off current ratio (> 108), a low threshold voltage, a steep subthreshold swing, a near-free drain-induced barrier lowering, as well as an excellent SCE suppression. Therefore, such high-performance GAA-MNC TFTs are very suitable for applications in system-on-panel and 3-D circuits. [ABSTRACT FROM AUTHOR]