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Abstract High performance, low operating voltage and low temperature processed Hf-In-Zn-O/HfO 2 thin film transistors (HIZO/HfO 2 TFTs), using spin-coated polymethyl-methacrylate (PMMA) as passivation and etch-stop layer (ESL), were fabricated and characterized. Devices showed an average field-effect mobility of 15 cm2/Vs and threshold voltage (V T) of 0.2 V, working in the operating voltage range below 2 V. The I on/off ratio was 104. Device parameters remained without significant change after months of fabrication. Stability of PMMA passivated devices, after gate and gate-drain bias stress is compared with data reported for other materials used as ESL or passivation layer, showing similar or better performance in preventing threshold voltage shifts, hump, reduction of mobility or of the on/off current ratio. Graphical abstract Unlabelled Image Highlights • Highly stable HIZO TFTs with PMMA as etch-stop and passivation layer • High mobility HfO 2 /HIZO TFTs with operating voltage range of 2 V • High performance HfO 2 /HIZO TFTs with full fabrication process below 120 °C [ABSTRACT FROM AUTHOR]

Organic and inorganic thin film transistors (TFTs) are fabricated, simulated, and tested for circuit applications. The devices are based on polycrystalline cadmium sulfide (CdS) and pentacene thin films. Both devices are simulated and analyzed using two-dimensional finite element simulation methodology. For CdS, grain boundary and uniform trap distribution approaches are implemented. It is assumed that traps due to grain boundaries are uniformly distributed throughout the film. For pentacene a Poole–Frenkel mobility model is employed. After matching device simulation with experimental data, the SPICE model parameters are extracted for circuit simulation. The devices are tested for both analog and digital circuits. operational amplifier (OPAMP) and inverter circuits are tested. Two OPAMP topologies are compared and the results are discussed. One of the topologies is based on all n-type transistors using CdS TFT and the other topology is the two-stage Miller compensated CMOS design based on CdS and pentacene TFTs. The operational amplifiers have an open-loop voltage gain of 25.9 dB and 29.7 dB respectively. The performance of the CMOS design is found to be limited by performance of pentacene transistor. [ABSTRACT FROM AUTHOR]

In this work, the performance of inkjet-printed 6,13-bis(triisopropylsilylethynyl)pentacene (TIPS-pentacene)-based organic thin-film transistors (OTFTs) was studied under various printing conditions using photolithography-defined test structures. OTFTs were printed from TIPS-pentacene solutions with several concentrations, and the impact of printing temperature as well as the amount of material printed was studied. A hybrid approach that includes wells defined by a photolithography process and printed TIPS solution is demonstrated. The results show that the mobility of the printed OTFTs increases with increasing solution concentration, with a maximum mobility for concentration of 50 mg/mL and substrate temperature of 50°C. X-ray diffraction analysis showed the presence of the thin-film phase for all of the TIPS concentrations, with strong and sharp preferential orientation along the (001) direction without any disruption in molecular packing with increasing TIPS thickness. Optimized OTFTs fabricated with this technique show mobilities of 5 × 10 cm/V-s, threshold voltages ( V) in the range of −5 V, and subthreshold slopes of approximately 0.5 V/dec. On-off current ratios up to 10 were also achieved. [ABSTRACT FROM AUTHOR]

Abstract: The fabrication and characterization of transparent logic inverters based on zinc oxide (ZnO) thin film transistors (TFTs) is reported. The inverters are fabricated using standard photolithographic techniques on glass substrates, and the entire fabrication process temperature is maintained <100°C, which render the devices suitable for flexible and transparent electronics applications. Pulsed laser deposition is used to deposit aluminum-doped zinc oxide and ZnO as electrode and active semiconductor materials, respectively. Electrical characterization for individual TFTs demonstrate mobilities of ~10cm2/V-s, threshold voltages of 6V, sub-threshold slopes of 630mV/decade and I ON/I OFF ratios of 5×106. Films characterized by UV-Vis showed optical transmission >80% in the visible spectrum. The inverters are analyzed with AC input signals at frequencies of 100 and 500Hz. The AC response shows an average rise and fall time transitions of 0.65 and 0.44ms, respectively. Measured inverters delay is in the order of 0.21ms. [Copyright &y& Elsevier]

During thin film transistor (TFT) operation, gate dielectric is under a bias stress condition. In this work, bias stress effect for CdS TFT using HfO2 as gate dielectric is analyzed. Threshold voltage, Ion/Ioff ratio, and subthreshold slope were studied in order to understand changes produced at the dielectric semiconductor interface. We observed that threshold voltage shift is related with negative charge trapping in the dielectric/semiconductor interface and for this phenomenon we propose a trapping charge model. Finally, the TFT output characteristic was modeled considering a shift in the threshold voltage for each gate voltage curve. [ABSTRACT FROM AUTHOR]

Abstract: We have demonstrated a low temperature process for a ferroelectric non-volatile random access memory cell based on a one-transistor–one-capacitor (1T1C) structure for application in flexible electronics. The n-channel thin film transistors (TFTs) and ferroelectric capacitors (FeCaps) are fabricated using cadmium sulfide (CdS) as the semiconductor and poly(vinylidene fluoride-trifluoroethylene) [P(VDF-TrFE)] copolymer as the ferroelectric material, respectively. The maximum processing temperature for the TFTs is 100°C and 120°C for the FeCaps. The TFT shows excellent access control of the FeCap in the 1T1C memory cell, and the stored polarization signals are undisturbed when the TFT is off. The fabricated 1T1C memory cell was also evaluated in a FRAM circuit. The memory window on the bit line was demonstrated as 2.3V, based on the 1T1C memory cell with a TFT having dimensions of 80μm/5μm (W/L) and a FeCap with an area of 0.2×10−3 cm2 using a bit line capacitor of 1nF pre-charged at 17.2V. The 1T1C memory cell is fabricated using photolithographic processes, allowing the integration with other circuit components for flexible electronics systems. [Copyright &y& Elsevier]

Improved carrier mobility and threshold voltage (VT) stability in cadmium sulfide (CdS) thin film transistors (TFTs) were studied and attributed to larger grain clusters in thicker CdS films rather than individual crystallite size. Non-zero VT shifts (∼200 mV) in thicker films are attributed to the presence of cadmium hydroxide [Cd(OH)2] at the dielectric/CdS interface resulting from the chemical bath deposition process used to deposit the CdS films. VT and mobility analyses indicate that clusters of CdS grains have a larger impact on TFT performance and stability than the presence of impurities in the bulk of the CdS. TFTs using this fabrication method achieved mobilities of ∼22 cm2/Vs with VT of 7 V and ΔVT of <200 mV after testing. The maximum processing temperature is 100 °C which makes this process compatible with flexible substrates. [ABSTRACT FROM AUTHOR]

Abstract: In this work we present a new polymeric thin film transistor (PTFT), fabrication process where standard photolithographic and dry etching techniques are used to place gate contact on the upper surface of the device, and to access in an easy and reliable way the buried bottom drain and source contacts from the upper surface of the device. This fabrication technique benefits of all the advantages that photolithographic processes report, as device isolation, patterning of small dimensions and possibility of device integration on both rigid and flexible substrates. We also show that, since PMMA is placed as the outermost polymeric layer, it serves both as dielectric and as protective layer, allowing devices to work in ambient conditions with significantly less degradation than other PTFTs structures previously reported. Electrical characterization of the devices showed that this technological approach provides mobility values an order of magnitude higher than those previously reported by us, using the same polymeric layers, but with buried drain and source contacts. [Copyright &y& Elsevier]

Abstract: In this paper we present a detailed characterization of metal–isolator–semiconductor MIS structures and organic thin film transistors (OTFTs) using poly(methyl methacrylate) (PMMA) as gate dielectric on top of a semiconductor poly(3-hexylthiophene) (P3HT) layer. The PMMA layer was spin coated from a 6% dilution of PMMA in anisole. The P3HT layer was spin coated from a 0.66wt% dilution of P3HT in chloroform. OTFTs with upper gate were fabricated using photolithographic processes. The current density across the dielectric is below 1×10−6 A/cm2. The interface states density is below 1×1011 cm−2, while the flat band voltage shift is less than 0.5V for bias stress in the range of ±20V. Accumulation occurs for gate voltage below −10V, allowing OTFTs to work in the voltage range below −30V, with threshold voltage around −2.5V. Mobility was 2.5×10−3 cm2/Vs, which is among highest values reported for P3HT OTFTs working in this voltage range. [Copyright &y& Elsevier]

Graphical abstract Highlights • Low temperature processing of hybrid dielectric gate layers by sol-gel. • Al 2 O 3 -GPTMS-PMMA hybrid films for applications as dielectric gate in TFT. • ZnO-based thin-film transistors with high Ion/Ioff current ratio. Abstract In this work we evaluate the synthesis of inorganic-organic Al 2 O 3 -GPTMS-PMMA hybrid films using a low temperature sol-gel process and their use as gate dielectric for thin film transistors (TFTs). The hybrid films were deposited by dip coating process and then annealed at 150 °C in air. The analysis of the hybrid films was performed by UV–VIS spectroscopy, FTIR, AFM, SEM, C-V and I-V measurements. The optical transparency above 85% in the visible range and homogeneity of the hybrid films support the proper link between inorganic and organic phases with strong bonds. At microscopic level, the hybrid films have uniform surface roughness lower than 1 nm. The C-V and I-V measurements performed on MIM structures showed leakage current density in the order of 10−7 A/cm2 at 104 kV/cm electric field. Capacitance and dielectric constant measured at 1 kHz were 20.4 pF and of 6.2, respectively. TFTs were fabricated using bottom gate and aluminium top contacts to obtain mobilities of 4.5 cm2/Vs, threshold voltage of 0.7 V and I on /I off ratio of 107, while mantaining operating voltage under 8 V. [ABSTRACT FROM AUTHOR]

Thin film transistors (TFTs) with a bottom-gate configuration were fabricated using a photolithography process with chemically bath deposited (CBD) cadmium sulfide (CdS) films as the active channel. Thermal annealing in hydrogen was used to improve electrical stability and performance of the resulting CdS TFTs. Hydrogen thermal treatments results in significant VT instability (VT shift) improvement while increasing the Ion/Ioff ratio without degrading carrier mobility. It is demonstrated that after annealing VT shift and Ion/Ioff improves from 10 V to 4.6 V and from 105 to 109, respectively. Carrier mobility remains in the order of 14.5 cm2 V s−1. The reduced VT shift and performance is attributed to a reduction in oxygen species in the CdS after hydrogen annealing, as evaluated by Fourier transform infrared spectroscopy (FTIR). [ABSTRACT FROM AUTHOR]

Abstract: In this paper we demonstrate p-type thin film transistors fabricated with lead sulfide (PbS) as semiconductor deposited by chemical bath deposition methods. Crystallinity and morphology of the resulting PbS films were characterized using X-ray diffraction, atomic force microscopy and scanning electron microscopy. Devices were fabricated using photolithographic processes in a bottom gate configuration with Au as source and drain top contacts. Field effect mobility for as-fabricated devices was ~0.09cm2 V−1 s−1 whereas the mobility for devices annealed at 150°C/h in forming gas increased up to ~0.14cm2 V−1 s−1. Besides the thermal annealing, the entire fabrications process was maintained below 100°C. The electrical performance of the PbS-thin film transistors was studied before and after the 150°C anneal as well as a function of the PbS active layer thicknesses. [Copyright &y& Elsevier]

Abstract: In this paper we study the dependence of charge carrier mobility with temperature in polymeric TFTs, PTFTs, using an expression previously derived by us, which has the advantage with respect to previous expressions, that most model parameters represent physical device parameters. Upper gate PTFTs fabricated with polymethyl methacrylate, PMMA, on poly(3-hexyl thiophene), P3HT, and with PMMA on poly(9,9-dioctylfluorene-co-bithiophene), F8T2, working in the temperature range between 300K and 370K were used in this study. Each model parameter was extracted at each temperature to determine its variation with T, observing that the bias enhancement parameter for mobility varies much slower than expected, if the characteristic temperature of the distribution of states DOS is considered constant. In this work, this behavior, which has been noticed but not explained before, is analyzed and interpreted, concluding that it has to be considered to represent correctly the behavior of mobility in the normal temperature operating range of PTFTs. Comparison of experimental and calculated data demonstrates the good agreement obtained, showing an Arrhenius-type dependence of the charge carrier mobility with an activation energy in the order of 70meV and 120meV for P3HT and F8T2 PTFTs, respectively. [ABSTRACT FROM AUTHOR]

In this work, the specific contact resistance (ρ c ) between amorphous indium-gallium-zinc-oxide (IGZO) semiconductor and different contact electrodes was obtained from thin film transistors (TFTs). Ti/Au (10/100 nm), aluminum doped zinc oxide (AZO, 100 nm) and indium tin oxide (ITO, 100 nm) were used as source/drain electrodes to fabricate IGZO TFTs. Chemical states of the contacts/semiconductor interfaces were examined by depth profile X-ray photoelectron spectroscopy (XPS) analysis to explain the origin of the differences on specific contact resistance. The lowest ρ c achieved using Ti/Au was related to the formation of a TiO x interlayer due to oxygen atoms diffusing out from the semiconductor under layer, increasing the carrier concentration of IGZO at the interface and lowering the ρ c . On the contrary, no interfacial reactions were observed between IGZO and AZO or ITO source/drain. However, IGZO resistivity increased with ITO contacts likely due to oxygen vacancies filling during ITO deposition. This fact seems to be the origin of the high contact resistance between IGZO and ITO, compared to IGZO-AZO and IGZO-Ti/Au interfaces. [ABSTRACT FROM AUTHOR]

MIS structures using HfO 2 and HIZO layers, both deposited by room temperature RF magnetron sputtering are fabricated for TFTs application and characterized using capacitance-voltage. The relative dielectric constant obtained at 1 kHz was 11, the charge carrier concentration of the HIZO was in the range of (2–3) × 10 18 cm − 3 and the interface trap density at flat band was smaller than 2 × 10 12 cm − 2 . The critical electric field of the HfO 2 layer was higher than 5 × 10 5 V/cm, with a current density in the operating voltage range below 4 × 10 − 8 A/cm 2 . The hysteresis and bias stress behavior of RF-sputtered HfO 2 /HIZO MIS structures is presented. Fabricated HfO 2 /HIZO TFTs worked in the operation voltage range below 8 V. [ABSTRACT FROM AUTHOR]

Aluminum doped zinc oxide (AZO) films were deposited by confocal RF magnetron sputtering at different substrate temperatures. AZO films with a transparency up to 90% in the visible spectrum were obtained. Polycrystalline AZO films, with planes in the (002) and (103) orientations of the zincblende (hexagonal) structure, were obtained at substrate temperatures higher than 60 °C. The best AZO films, obtained at 75 °C, showed an electrical resistivity of 8.8 × 10 − 4 Ω-cm, with a carrier concentration of 4 × 10 20 cm − 3 and mobility of 20 cm 2 /V-s. These are appropriate values for solar cell applications. In addition, ZnO-based thin-film transistors (TFTs) were fabricated for evaluating the behavior of the AZO films as source and drain contacts on the transistors. The field effect mobility and the threshold voltage of the fabricated devices were 20 cm 2 /V-s and 7 V, respectively. The TFTs showed an I on / I off ratio of up to 9 orders of magnitude. A specific contact resistance of approximately 0.06 Ω-cm 2 was determined for the AZO/ZnO interface. This result corresponds to the first report of the ZnO/AZO specific contact resistance obtained with a maximum processing temperature of 100 °C. Therefore, this TFT technology is fully compatible with flexible substrates and can be used for transparent and large area electronics. [ABSTRACT FROM AUTHOR]

The impact on the electrical behavior of thin film transistors, TFTs, based on zinc oxide, ZnO-based TFTs, with temperature is analyzed. ZnO is deposited using pulsed laser deposition techniques and the temperature used during the entire fabrication process is kept below 100 °C. Up to 330 K, the transfer curves practically remain constant or slightly shifted toward more positive voltages. For temperatures up to 330 K, they show the combined effect of the threshold voltage shifting toward more negative voltages and the increase of series resistance. The drain current shows an Arrhenius-type dependence with temperature in subthreshold regime with activation energy of around 0.53 eV. In above threshold regime, for temperatures above 330 K, the activation energy is around 0.15 eV. [ABSTRACT FROM AUTHOR]

Lead sulfide (PbS) thin films were prepared by chemical bath deposition (CBD) as function of deposition time, pH and deposition rate and the impact of the resulting film structure on the thin film transistor (TFT) electrical characteristics was evaluated. Structure and morphology were investigated by X-ray diffraction (XRD) and scanning electron microscopy respectively (SEM). The deposited films show a cubic phase (galena) with an average crystallite size of ~25 nm. Three different PbS deposition conditions were evaluated in TFTs using source and drain gold contacts. The best electrical performance was observed for films deposited at high deposition rates. These transistors, showed field effect mobility and threshold voltage of ~3x10-3 cm²/V-s and ~6 V, respectivel.y [ABSTRACT FROM AUTHOR]